RU2553120C1 - Device for evaluating random variable distribution function and tolerance boundaries thereof on small samples - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device for evaluating a random variable distribution function and its tolerance boundaries on small samples comprises groups of input registers, input registers, delay elements, a multiplier unit, groups of delay elements, groups of subtractor units, a group of squaring devices, accumulating adders, divider units, square-rooting units, adders, shift registers, an exponentiation unit, groups of multiplier units, groups of adders, groups of comparator units, groups of NOT elements, groups of divider units, groups of registers, groups of coincidence circuits, groups of storage devices, a group of accumulating adders, groups of output registers, groups of display units, a unit for eliminating the fractional part of a number, a subtractor unit, a maximum value determining unit, a comparator unit, a group of modulo subtraction units, a display unit, a clock-pulse generator and a pulse distributor.

EFFECT: higher accuracy and broader functional capabilities owing to evaluation of tolerance boundaries of a random variable distribution function.

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Description

The invention relates to computer technology and can be used in calculations related to the assessment of the probability characteristics of random variables (CB), when there is a small amount of statistical data.

A device for determining the distribution parameters for small samples containing memory blocks, switches, synchronizers, a registration block, delay elements, OR elements, a counter, buffer registers, subtraction blocks, quadrants, comparison blocks, threshold elements, division blocks, adders, multiplication blocks , AND elements, NOT elements, shift registers, exponentiation blocks, and a square root extraction block (ed. certificate of the USSR No. 1591043, class G06F 15/36, 1990).

The disadvantage of this device is the low accuracy due to the lack of verification of the statistical hypothesis about the convergence of theoretical and experimental distributions.

The closest analogue, prototype, is a device for determining distribution parameters for small samples (ed. Certificate of the USSR No. 1702393, G06F 15/36, 1991), containing input register blocks, a switch, a registration unit, a synchronizer, registers, switching nodes, a group shift registers, comparison nodes, multiplication block, constant summation block, division block, multiplication nodes, constant subtraction block, delay element groups, element groups OR, division nodes, comparison block, distribution density calculation block group, group modulus subtraction blocks, summation nodes, constant subtraction block, and summation node.

The disadvantage of this device is the low accuracy, because the method of rectangular contributions and the lack of assessment of the tolerance limits of the distribution function of CB are not used.

The technical result of the claimed invention is to increase the accuracy and expand the functionality by evaluating the tolerance limits of the distribution function of CB.

определится по следующей формуле:You can improve accuracy by using the rectangular contribution method. With this approach, the distribution function F (x _j ) for the j-th section of the interval of variation of CB $$\widehat{x}$$

determined by the following formula:

where j = 1, ..., m (m is the number of discrete values of the argument of the distribution function on which it is constructed);

(интервал дискретизации);h is the step of dividing the interval of change of CB $$\widehat{x}$$

(sampling interval);

в j-m сечении ее изменения.f (x _j ) is the value of the distribution density of CB $$\widehat{x}$$

in jm section of its change.

The value of f (x _j ) is estimated as follows:

;where a and b are respectively the lower and upper boundaries of the interval of measurement of CB $$\widehat{x}$$

;

;x _i - ie CB value $$\widehat{x}$$

;

i = 1, ..., n (n is the sample size CB);

- функция вклада.

- contribution function.

The value of step h is determined by the formula:

where N is the number of subintervals of the partition of the interval CB [a, b].

The value of x _j is determined by the following formula:

Since it is planned to construct a rectangular contribution function around each ith value of a random variable and the contribution should not go beyond the boundaries of the interval [a, b], the contribution function can be determined using the following dependencies.

и $$x_i+\frac{S}{2}\ge b$$

, то:If $$x_i-\frac{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="00000044.png,00000045.png"\; state="\{\{state\}\}">S</figure-callout>}}{2}\ge a$$

and $$x_i+\frac{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="00000044.png,00000045.png"\; state="\{\{state\}\}">S</figure-callout>}}{2}\ge b$$

then:

, то:If $$x_i-\frac{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="00000044.png,00000045.png"\; state="\{\{state\}\}">S</figure-callout>}}{2}<a$$

then:

, то:If $$x_i+\frac{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="00000044.png,00000045.png"\; state="\{\{state\}\}">S</figure-callout>}}{2}>b$$

then:

Here S is the basis of the contribution function.

The boundaries of the interval [a, b] are determined by the following formulas:

;where x ₁ and x _n are, respectively, the first and last (n-th) selective value of CB

;

ε is the accuracy, which is estimated using the expression:

where β is the value determined from the table as a function of confidence probability γ and sample size n;

.d _x - estimate of variance of CB

.

The value of d _x is determined by the following formula:

, оцениваемое по формулеwhere m _x is the mathematical expectation of CB

estimated by the formula

The parameter ε can also be used to construct the tolerance boundaries of the CB distribution function. Using the method of mathematical induction for any relationship between the quantities ε and h, we can write formulas that evaluate the lower and upper tolerance boundaries in the following form:

where l - represents the integer part of the ratio ε / h.

In order to assess the correctness of the proposed principle of constructing a selective (empirical) distribution function of CBs, to determine the optimal basis of the contribution function, it is necessary to check the correspondence of empirical and theoretical distributions. Given the small sample size, it is advisable to verify compliance by the Kolmogorov criterion, according to which the parameter λ is calculated by the formula:

where D is the absolute value of the maximum difference between the theoretical F (x _j ) _T and the empirical F (x _j ) values of the distribution function.

Then λ is compared with the critical parameter λ _cr . If λ <λ _cr , then the hypothesis is accepted. When λ≥λ _{cr, the} hypothesis is rejected (the hypothetical distribution function is not consistent with empirical data). A criterion based on the modulus of the difference between theoretical and empirical values allows us to estimate the optimal value of the base of the contribution function. To solve this problem, we simulated a given number of CBs (sample size n) distributed according to a certain law. Then, empirical densities and distribution functions were constructed from these n values using the method described above. Moreover, the basis of the contribution function S varies. The concept of the relative basis of the contribution function K was introduced, which is determined by the formula:

where the value of S can be determined by the expression:

As a result of the simulation, the following approximating expression was obtained:

where C ₁ and C ₂ are constant coefficients.

The values of C ₁ and C ₂ were determined using the least squares method. As a result, the following numerical values were obtained for these constant coefficients: C ₁ = 0.686, C ₂ = 0.035. Then formula (16) can be rewritten in the following form:

To illustrate the developed approach, it is necessary to consider a numerical example. Let it be required to construct the density, distribution function, and its tolerance boundaries for the following experimental data (n = 6) located in the variational series: 33.02; 39.69; 46.08; 48.54; 60.47; 66.20. To verify the compliance of theoretical and empirical distributions, these values were obtained by modeling random numbers distributed according to the normal law with parameters m _x = 50; σ _x = 10 (standard deviation).

; $$d_x^{*}=\mathrm{105,06}$$

. Используя формулу (9) при доверительной вероятности γ=0,9, значении β=2,015, получим ε=8,39. Границы интервала изменения СВ определяется в соответствии с формулами (8): а=24,63; b=74,39. Этот интервал разбивается на 10 подинтервалов, характеризующихся границами (базовыми опорными точками x_j), в которых и будут оцениваться эмпирические и теоретические распределения. Значения этих точек определяются путем последовательного прибавления к величине значения а шага разбиения h интервала изменения СВ. В соответствие с формулой (3) h=4,996. Используя формулу (4) можно получить следующий ряд (11 значений) величин x_j: 24,63; 29,63; 34,62; 39,62; 44,61; 49,61; 54,61; 59,60; 64,60; 69,59; 74,59.In accordance with formulas (11) and (10), the values of mathematical expectation and variance are calculated: $$m_x^{*}=49.00$$

; $$d_x^{*}=105.06$$

. Using formula (9) with a confidence probability of γ = 0.9, a value of β = 2.015, we obtain ε = 8.39. The boundaries of the interval of change in SW are determined in accordance with formulas (8): a = 24.63; b = 74.39. This interval is divided into 10 subintervals, characterized by boundaries (base reference points x _j ), at which empirical and theoretical distributions will be estimated. The values of these points are determined by sequentially adding to the value of the value a of the step of dividing h the interval of variation of CB. In accordance with formula (3), h = 4.996. Using formula (4), one can obtain the following series (11 values) of the values of x _j : 24.63; 29.63; 34.62; 39.62; 44.61; 49.61; 54.61; 59.60; 64.60; 69.59; 74.59.

Since the sample size is n = 6, according to formula (17), the optimal relative basis of the contribution function K = 0.55 is obtained. Based on the formula (15), the value of the base of the contribution function is determined S = 27.48.

для различных вариантов соответствующих неравенств. По формуле (2) рассчитываются эмпирические значения плотности распределения f(x_j), которые представлены на фиг.1 в виде точек, соединенных ломаной линией. Теоретическая плотность распределения f(x) изображена плавной кривой, а экспериментальные данные x_i отмечены на оси абсцисс крестиками.Taking into account formulas (5), (6), (7), the values of the contribution function are estimated

for various variants of the corresponding inequalities. According to the formula (2), empirical values of the distribution density f (x _j ) are calculated, which are presented in Fig. 1 in the form of points connected by a broken line. The theoretical distribution density f (x) is shown by a smooth curve, and the experimental data x _i are marked with crosses on the abscissa axis.

Empirical values for the distribution function and its tolerance boundaries are estimated by formulas (1), (12) and (13), respectively. 2, the values of the empirical distribution function are indicated by triangles, and the theoretical distribution function of the representation of a continuous curve. The values of empirical tolerance boundaries (upper and lower) are shown by dashed lines.

According to formula (14), the value of the parameter λ is determined to verify compliance with the Kolmogorov criterion: λ = 0.343, (D = 0.140, n = 6). The critical value of the parameter at a significance level of α = 0.10, λ _cr = 1.224. A comparison of λ _cr with λ indicates a good agreement between the theoretical and empirical distributions, which indicates the correctness of the proposed approach for estimating the distribution function of CB over small samples.

, информационные входы второй группы входных регистров являются входами задания исходной информации, на которые поступают величины F(x_j)_T, характеризующие теоретические значения функции распределения CB $$\widehat{x}$$

, информационные входы с первого по четвертый входных регистров являются входами задания исходной информации, на которые поступают соответственно значение n, характеризующее объем выборки CB, величина β, характеризующая значение, выбираемое из таблицы в зависимости от доверительной вероятности и объема выборки, значение N, характеризующее число подинтервалов разбиения интервала изменения CB, и величина λ_кр, характеризующая критическое значение параметра λ, выходы первой группы входных регистров соединены с входами первой и второй групп ЭЗ, выходы которых подключены к входам уменьшаемого соответственно первой и второй групп блоков вычитания, выходы которых соединены соответственно с входами группы квадраторов и с информационными входами третьей и четвертой групп блоков сравнения, выходы каждого элемента первой группы входных регистров подключены к входам, с первого по n-й, первого накопительного сумматора, а выходы первого и n-го элементов этой группы соединены с входами соответственно первого и второго ЭЗ, выходы которых подключены соответственно к входу уменьшаемого второго блока вычитания и к первому входу первого сумматора, выход которого соединены с входом десятого ЭЗ и входом уменьшаемого третьего блока вычитания, выход которого подключены к входам шестого блока деления, восьмого блока ЭЗ и входу делимого второго блока деления, вход делителя которого соединен с выходом третьего входного регистра, а выход - с входом седьмого ЭЗ, выход которого подключен к входам первой группы блоков умножения и входу пятнадцатого ЭЗ, выход первого входного регистра соединен с входами первого блока вычитания, первого блока извлечения квадратного корня, второго блока умножения, второго сумматора и с входом делителя первого блока деления, вход делимого которого подключен к выходу первого накопительного сумматора, а выход - к входам вычитаемого первой группы блоков вычитания, выход второго входного регистра соединен с первым входом первого блока умножения, выход которого подключен к входу делимого третьего блока деления, а второй вход - выходу второго блока извлечения квадратного корня, вход которого соединен с выходом пятого блока деления, вход делителя которого подключен через третий ЭЗ к выходу первого блока вычитания, а вход делимого - к выходу второго накопительного сумматора, с первого по n-й входы которого соединены с выходами, с первого по n-и, элементов группы квадраторов, выход первого блока извлечения квадратного корня подключен к входам четвертого и пятого ЭЗ, выходы которых соединены соответственно с первым входом шестого блока умножения и с входом делителя третьего блока деления, выход которого подключен к второму входу первого сумматора, к входам шестнадцатого и семнадцатого ЭЗ и к входу вычитаемого второго блока вычитания, выход которого соединен с входом вычитаемого третьего блока вычитания, а также с входами одиннадцатого и девятого ЭЗ, выход которого подключен к первым входам первой группы сумматоров, вторые входы которой соединены с выходами первой группы блоков умножения, а выходы - с информационными входами первой и второй групп блоков сравнения, с пороговыми входами четвертой и шестой групп блоков сравнения, выход второго сумматора подключен к входу шестого ЭЗ, выход которого соединен с входами делителя третьей группы блоков деления, выход второго блока умножения подключен к входу блока возведения в степень, выход которого соединен с входом третьего блока умножения, выход которого подключен к первому входу четвертого блока умножения, второй вход которого соединен с выходом восьмого ЭЗ, а выход - с входом первого регистра сдвига и входом четвертого блока деления, выход которого подключен к информационным входам первой группы регистров, выход первого регистра сдвига соединен с входом двенадцатого ЭЗ, выход которого подключен к входам уменьшаемого четвертой группы блоков вычитания, к первым входам второй группы сумматоров и к входам вычитаемого второй группы блоков вычитания, выход одиннадцатого ЭЗ соединен с пороговыми входами первой и третьей групп блоков сравнения и с входом тринадцатого ЭЗ, выход которого подключен к входам вычитаемого третьей группы блоков вычитания, выходы которого соединены с входами первой группы блоков деления, выходы которой подключены к информационным входам второй группы регистров, выходы которой соединены с седьмыми входами группы накопительных сумматоров, выход десятого ЭЗ подключен к пороговым входам второй и пятой групп блоков сравнения и к первым входам третьей группы сумматоров, выходы которой соединены с входами второй группы блоков деления, выходы которой подключены к информационным входам третьей группы регистров, выходы которой соединены с восьмыми входами группы накопительных сумматоров, выходы второй группы ЭЗ подключены к входам уменьшаемого второй группы блоков вычитания, к входам вычитаемого четвертой группы блоков вычитания и ко вторым входам второй группы сумматоров, выходы которой соединены с информационными входами пятой и шестой групп блоков сравнения и с входами уменьшаемого третьей группы блоков вычитания, выходы первой, второй, третьей, четвертой, пятой и шестой групп блоков сравнения подключены к входам соответственно первой, второй, третьей, четвертой, пятой и шестой групп элементов НЕ, выходы первой группы блоков сравнения соединены также со вторыми входами первой группы схем совпадения, выходы которых подключены к входам считывания первой группы ЗУ, выходы которой соединены со вторыми входами группы накопительных сумматоров, выходы второй группы блоков сравнения подключены также ко вторым входам девятой группы схем совпадения, выходы которой соединены с входами считывания шестой группы ЗУ, выходы которой подключены к шестым входам группы накопительных сумматоров, выходы третьей группы блоков сравнения, соединены также с первыми входами второй, пятой и четвертой групп схем совпадения, выходы которых подключены к входам считывания соответственно первой группы регистров, пятой и второй групп ЗУ, выходы которых соединены соответственно с девятыми, пятыми и четвертыми входами группы накопительных сумматоров, выходы четвертой группы блоков сравнения подключены также ко вторым входам четвертой и седьмой групп схем совпадения, выходы которой соединены с входами считывания четвертой группы ЗУ, выходы которой подключены к третьим входам группы накопительных сумматоров, выходы пятой группы блоков сравнения соединены также с третьими входами четвертой, второй и пятой групп схем совпадения, выходы шестой группы блоков сравнения подключены также ко вторым входам пятой и шестой групп схем совпадения, выходы которой соединены с входами считывания третьей группы ЗУ, выходы которой подключены к первым входам группы накопительных сумматоров, выходы первой группы элементов НЕ соединены со вторыми входами третьей группы схем совпадения, выходы которой подключены к входам считывания второй группы регистров, выходы которой соединены с седьмыми входами группы накопительных сумматоров, выходы второй группы элементов НЕ подключены к третьим входам восьмой группы схем совпадения, выходы которой соединены с входами считывания третьей группы регистров, выходы которой подключены к восьмым входам группы накопительных сумматоров, выходы третьей грумы элементов НЕ соединены с первыми входами третьей, шестой и первой групп схем совпадения, выходы четвертой группы элементов НЕ подключены ко вторым входам второй и восьмой групп схем совпадения, выходы пятой группы элементов НЕ соединены с первыми входами седьмой, восьмой и девятой групп схем совпадения, выходы шестой группы элементов НЕ подключены к четвертым входам второй группы схем совпадения и к третьим входам третьей группы схем совпадения, выходы группы накопительных сумматоров соединены с первыми входами четвертой группы сумматоров, вторые входы которой через четырнадцатый ЭЗ подключены к выходу шестого блока деления, а выходы - к входам делимого третьей группы блоков деления, выходы которой соединены с информационными входами первой группы выходных регистров, выходы которой подключены к входам первой группы блоков индикации и к первым входам второй группы блоков умножения, вторые входы которой соединены с выходом пятнадцатого ЭЗ, выход которого подключен также к входу делителя седьмого блока деления и к входу восемнадцатого ЭЗ, выход которого соединен с входом девятнадцатого ЭЗ и с первым входом пятого блока умножения, второй вход которого подключен к выходу блока ликвидации дробной части числа, вход которого соединен с выходом седьмого блока деления, вход делимого которого подключен к выходу шестнадцатого ЭЗ, выход семнадцатого ЭЗ соединен с входом уменьшаемого четвертого блока вычитания, вход вычитаемого которого подключен к выходу пятого блока умножения, а выход - к входу делимого восьмого блока деления, вход делителя которого соединен с выходом девятнадцатого ЭЗ, а выход - с первыми входами третьей и четвертой групп блоков умножения, выходы первого и m-го элементов второй группы блоков умножения подключены к входам соответственно второго и третьего регистров сдвига, выход последнего из которых соединен с первым входом m-го элемента пятой группы сумматоров, выход второго регистра сдвига подключен к информационному входу первого элемента второй группы выходных регистров, к входу уменьшаемого первого элемента пятой группы блоков вычитания, к входу первого элемента третьей группы ЭЗ и ко второму входу первого элемента пятой группы сумматоров, первые входы которой, кроме последнего элемента, соединены с выходами соответствующих элементов второй группы блоков умножения, а выходы каждого элемента пятой группы сумматоров, кроме последнего, - со вторыми входами последующих элементов, выходы каждого последующего элемента этой группы подключены к входам уменьшаемого соответствующих элементов пятой группы блоков вычитания, а выходы каждого предыдущего элемента пятой группы сумматоров - к входам вычитаемого тех же элементов пятой группы блоков вычитания, выходы которой соединены со вторыми входами третьей группы блоков умножения, выходы пятой группы сумматоров подключены также к входам третьей группы ЭЗ и к информационным входам второй группы выходных регистров, выходы которых соединены с входами четвертой группы ЭЗ, второй группы блоков индикации, и с входами вычитаемого группы блоков вычитания по модулю, выходы каждого последующего элемента второй группы выходных регистров подключены к входам уменьшаемого соответствующих элементов шестой группы блоков вычитания, а выходы каждого предыдущего элемента второй группы выходных регистров - к входам вычитаемого тех же элементов шестой группы блоков вычитания, выходы которой соединены со вторыми входами четвертой группы блоков умножения, выходы которой подключены к первым входам шестой группы сумматоров, вторые входы которой соединены с выходами четвертой группы ЭЗ, а выходы - с информационными входами четвертой группы выходных регистров, выходы которой подключены к входам четвертой группы блоков индикации, выходы третьей группы блоков умножения соединены с входами вычитаемого седьмой группы блоков вычитания, входы уменьшаемого которой подключены к выходам третьей группы ЭЗ, а выходы - к информационным входам третьей группы выходных регистров, выходы которой соединены с входами третьей группы блоков индикации, выходы второй группы входных регистров подключены к входам уменьшаемого группы блоков вычитания по модулю, выходы которой соединены с первым по m-й входами блока определения максимального значения, выход которого подключен ко второму входу шестого блока умножения, выход которого соединен с информационным входом блока сравнения, пороговый вход которого подключен к выходу четвертого входного регистра, а выход - к входу блока индикации.The technical result is achieved by the fact that the device for evaluating the distribution function of random variables and its tolerant boundaries over small samples contains a first group of input registers consisting of n elements, a second group of input registers consisting of m elements, from the first to nineteenth delay elements (EI) , the first to fourth input registers, the first to sixth multiplication blocks, the first and second groups of EZ, each of which consists of n elements, the third and fourth groups of EZ, each of which consists of m elements, first th group of subtraction blocks, consisting of n elements, from the second to seventh groups of subtraction blocks, each of which consists of m elements, a group of quadrators, consisting of n elements, the first and second accumulative adders, from the first to eighth division blocks, the first and second square root extraction blocks, first and second adders, first, second and third shift registers, exponentiation block, from the first to fourth groups of multiplication blocks, each of which consists of m elements, from the first to sixth groups of adders of the first consists of m elements, from the first to the sixth group of comparison blocks, each of which consists of m elements, from the first to the sixth group of NOT elements, each of which consists of m elements, the first, second and third groups of division blocks, each of which consists of m elements, the first, second and third groups of registers, each of which consists of m elements, from the first to the ninth group of matching schemes, each of which consists of m elements, from the first to the sixth group of storage devices (memory), each of which consists of m elements, gru PPU accumulative adders, consisting of m elements, from the first to fourth groups of output registers, each of which consists of m elements, from the first to fourth groups of display units, each of which consists of m elements, the elimination unit of the fractional part of the number, from the first to the fourth subtraction blocks, the maximum value determination block, the comparison block, the group of modulus subtraction blocks, consisting of m elements, an indication block, a clock generator and a pulse distributor (RI), the clock input of which is connected to the output ohm of a clock pulse generator, the first output of the RI is with the recording inputs of the first and second groups of input registers, the first, second, third and fourth input registers, the second output is with the read inputs of the first group of input registers, the third, fourth and fifth outputs are with read inputs respectively, the first, second and third input registers, the sixth, seventh and eighth outputs - with write inputs of the first, second and third groups of registers, respectively, the ninth and tenth outputs - with inputs of write and read the first r, respectively groups of output registers, eleventh and twelfth outputs - with inputs respectively of writing and reading of the second group of output registers, thirteenth and fourteenth outputs - with inputs of respectively writing and reading of the third group of output registers, fifteenth and sixteenth outputs - with inputs of respectively writing and reading of the fourth group of output registers, seventeenth and eighteenth outputs - with read inputs, respectively, of the second group of input registers and fourth input register, information inputs of the first nth group of input registers are inputs of the input source information, which receives the values of x _i characterizing the values of a random variable (CB) $$\widehat{x}$$

, the information inputs of the second group of input registers are inputs for setting the initial information to which the quantities F (x _j ) _T , which characterize the theoretical values of the distribution function CB $$\widehat{x}$$

, the information inputs from the first to the fourth input registers are inputs of the input source information, which respectively receive a value n, which characterizes the sample size CB, value β, which characterizes the value selected from the table depending on the confidence probability and sample size, value N, which characterizes the number sub-intervals of the partition of the change interval CB, and the quantity λ _cr characterizing the critical value of the parameter λ, the outputs of the first group of input registers are connected to the inputs of the first and second groups EZ, the outputs of which are connected to the inputs of the first and second groups of subtraction blocks reduced respectively, the outputs of which are connected respectively to the inputs of the quad group and to the information inputs of the third and fourth groups of comparison blocks, the outputs of each element of the first group of input registers are connected to the inputs, from the first to n -th, of the first accumulative adder, and the outputs of the first and nth elements of this group are connected to the inputs of the first and second EZ, respectively, the outputs of which are connected respectively to the input of the reduced the second block of subtraction and to the first input of the first adder, the output of which is connected to the input of the tenth EZ and the input of the reduced third subtraction block, the output of which is connected to the inputs of the sixth division block, the eighth block of the EZ and the input of the dividend second division block, the input of the divider connected to the output of the third input register, and the output with the input of the seventh EZ, the output of which is connected to the inputs of the first group of multiplication units and the input of the fifteenth EZ, the output of the first input register is connected to the inputs of the first subtraction unit, per of the second square root extraction block, the second multiplication block, the second adder and with the input of the divider of the first division block, the input of which is divisible is connected to the output of the first accumulative adder, and the output is to the inputs of the subtracted first group of subtraction blocks, the output of the second input register is connected to the first input of the first multiplication unit, the output of which is connected to the input of the divisible third division unit, and the second input is the output of the second square root extraction unit, the input of which is connected to the output of the fifth division unit, the input de whose amplifier is connected through the third EZ to the output of the first subtraction unit, and the input of the dividend is connected to the output of the second accumulative adder, from the first to the n-th inputs of which are connected to the outputs from the first to n-th elements of the quadrator group, the output of the first square block the root is connected to the inputs of the fourth and fifth EZ, the outputs of which are connected respectively to the first input of the sixth multiplication unit and to the input of the divider of the third division unit, the output of which is connected to the second input of the first adder, to the inputs of the sixteenth and seventh of the ninth EZ and to the input of the subtracted second subtraction block, the output of which is connected to the input of the subtracted third subtraction block, and also to the inputs of the eleventh and ninth EZ, the output of which is connected to the first inputs of the first group of adders, the second inputs of which are connected to the outputs of the first group of multiplication blocks, and the outputs are with information inputs of the first and second groups of comparison blocks, with threshold inputs of the fourth and sixth groups of comparison blocks, the output of the second adder is connected to the input of the sixth EZ, the output of which is connected to the inputs the divider of the third group of division blocks, the output of the second multiplication block is connected to the input of the exponentiation block, the output of which is connected to the input of the third multiplication block, the output of which is connected to the first input of the fourth multiplication block, the second input of which is connected to the output of the eighth EZ, and the output - the input of the first shift register and the input of the fourth division block, the output of which is connected to the information inputs of the first group of registers, the output of the first shift register is connected to the input of the twelfth EZ, the output of which is connected to the moves of the reduced fourth group of subtraction blocks, to the first inputs of the second group of adders and to the inputs of the subtracted second group of subtraction blocks, the output of the eleventh EZ is connected to the threshold inputs of the first and third groups of comparison blocks and the input of the thirteenth EZ, the output of which is connected to the inputs of the subtracted third group of blocks subtraction, the outputs of which are connected to the inputs of the first group of division blocks, the outputs of which are connected to the information inputs of the second group of registers, the outputs of which are connected to the seventh inputs of the py accumulators, the output of the tenth EZ is connected to the threshold inputs of the second and fifth groups of comparison blocks and to the first inputs of the third group of adders, the outputs of which are connected to the inputs of the second group of division blocks, the outputs of which are connected to the information inputs of the third group of registers, the outputs of which are connected to the eighths the inputs of the group of accumulative adders, the outputs of the second group of EZ are connected to the inputs of the reduced second group of subtraction blocks, to the inputs of the subtracted fourth group of subtraction blocks and to the second inputs the second group of adders, the outputs of which are connected to the information inputs of the fifth and sixth groups of comparison blocks and with the inputs of the reduced third group of subtraction blocks, the outputs of the first, second, third, fourth, fifth and sixth groups of comparison blocks are connected to the inputs of the first, second, third, the fourth, fifth and sixth groups of elements NOT, the outputs of the first group of comparison units are also connected to the second inputs of the first group of matching circuits, the outputs of which are connected to the read inputs of the first group of memory, the outputs of which connected to the second inputs of the group of accumulative adders, the outputs of the second group of comparison blocks are also connected to the second inputs of the ninth group of matching circuits, the outputs of which are connected to the read inputs of the sixth group of memory, the outputs of which are connected to the sixth inputs of the group of accumulative adders, the outputs of the third group of comparison blocks are connected also with the first inputs of the second, fifth and fourth groups of matching circuits, the outputs of which are connected to the reading inputs of the first group of registers, the fifth and second groups of memory, respectively the outputs of which are connected respectively to the ninth, fifth and fourth inputs of the group of accumulative adders, the outputs of the fourth group of comparison units are also connected to the second inputs of the fourth and seventh groups of matching circuits, the outputs of which are connected to the read inputs of the fourth group of memory, the outputs of which are connected to the third inputs of the group of accumulative adders, the outputs of the fifth group of comparison blocks are also connected to the third inputs of the fourth, second and fifth groups of matching circuits, the outputs of the sixth group of comparison blocks are connected They are also connected to the second inputs of the fifth and sixth groups of matching circuits, the outputs of which are connected to the reading inputs of the third group of memory, the outputs of which are connected to the first inputs of the group of accumulative adders, the outputs of the first group of elements are NOT connected to the second inputs of the third group of matching circuits, the outputs of which are connected to read inputs of the second group of registers, the outputs of which are connected to the seventh inputs of the group of accumulative adders, the outputs of the second group of elements are NOT connected to the third inputs of the eighth group of circuits the outputs of which are connected to the read inputs of the third group of registers, the outputs of which are connected to the eighth inputs of the group of accumulative adders, the outputs of the third element cells are NOT connected to the first inputs of the third, sixth and first groups of matching circuits, the outputs of the fourth group of elements are NOT connected to the second inputs of the second and the eighth group of matching circuits, the outputs of the fifth group of elements are NOT connected to the first inputs of the seventh, eighth and ninth groups of matching circuits, the outputs of the sixth group of elements are NOT connected to the fourth input m of the second group of coincidence circuits and to the third inputs of the third group of coincidence circuits, the outputs of the group of accumulative adders are connected to the first inputs of the fourth group of adders, the second inputs of which through the fourteenth EZ are connected to the output of the sixth division block, and the outputs to the inputs of the divisible third group of division blocks, the outputs of which are connected to the information inputs of the first group of output registers, the outputs of which are connected to the inputs of the first group of display units and to the first inputs of the second group of multiplication blocks, the second inputs to otoroy connected to the output of the fifteenth EZ, the output of which is also connected to the input of the divider of the seventh division unit and to the input of the eighteenth EZ, the output of which is connected to the input of the nineteenth EZ and the first input of the fifth multiplication block, the second input of which is connected to the output of the elimination unit of the fractional part of the number, the input of which is connected to the output of the seventh division block, the input of the dividend of which is connected to the output of the sixteenth EZ, the output of the seventeenth EZ is connected to the input of the reduced fourth subtraction block, the input of which is subtracted by is connected to the output of the fifth multiplication block, and the output to the input of the divisible eighth division block, the input of the divider of which is connected to the output of the nineteenth EZ, and the output to the first inputs of the third and fourth groups of multiplication blocks, the outputs of the first and mth elements of the second group of multiplication blocks connected to the inputs of the second and third shift registers, respectively, the output of the last of which is connected to the first input of the mth element of the fifth group of adders, the output of the second shift register is connected to the information input of the first element of the second group s of output registers, to the input of the reduced first element of the fifth group of subtraction blocks, to the input of the first element of the third group of EZs and to the second input of the first element of the fifth group of adders, the first inputs of which, except for the last element, are connected to the outputs of the corresponding elements of the second group of multiplication blocks, and the outputs of each element of the fifth group of adders, except the last, with the second inputs of subsequent elements, the outputs of each subsequent element of this group are connected to the inputs of the reduced corresponding element nts of the fifth group of subtraction blocks, and the outputs of each previous element of the fifth group of adders to the inputs of the same elements of the fifth group of subtraction blocks, the outputs of which are connected to the second inputs of the third group of multiplication blocks, the outputs of the fifth group of adders are also connected to the inputs of the third group of EZ and the information inputs of the second group of output registers, the outputs of which are connected to the inputs of the fourth group of EZs, the second group of display units, and the inputs of the subtracted group of subtraction blocks modulo, the outputs of each the next element of the second group of output registers are connected to the inputs of the reduced corresponding elements of the sixth group of subtraction blocks, and the outputs of each previous element of the second group of output registers are connected to the inputs of the deductible of the same elements of the sixth group of subtraction blocks, the outputs of which are connected to the second inputs of the fourth group of multiplication blocks, the outputs which are connected to the first inputs of the sixth group of adders, the second inputs of which are connected to the outputs of the fourth group of EZ, and the outputs to the information inputs the fourth group of output registers, the outputs of which are connected to the inputs of the fourth group of indication blocks, the outputs of the third group of multiplication blocks are connected to the inputs of the subtracted seventh group of subtraction blocks, the inputs of which are reduced are connected to the outputs of the third group of EZ, and the outputs are to the information inputs of the third group of output registers, the outputs of which are connected to the inputs of the third group of indication blocks, the outputs of the second group of input registers are connected to the inputs of the reduced group of subtraction blocks modulo, the outputs of which dineny first to m-th block inputs determine the maximum value, the output of which is connected to the second input of the sixth multiplier, whose output is connected to the data input of the comparator, a threshold input connected to the output of the fourth input register, and an output - to the input of the indication unit.

Figure 1 presents the empirical (broken line) and theoretical (smooth curve) distribution density of a random variable; figure 2 shows the empirical and theoretical values of the distribution function and its tolerant boundaries; figure 3, 4, 5, 6, 7 and 8 presents a functional diagram of a device for evaluating the distribution function of random variables and its tolerance boundaries for small samples (to eliminate the cumbersome connection between the RS and the control inputs of the corresponding blocks are not shown completely, but are indicated by numbering of inputs and outputs); figure 9 shows the sequence diagram of the operation of the claimed device (the ordinates indicate the numbers of the outputs of the RI, and the abscissa axis indicates the number of ticks), and the duration of various computational operations (addition, calculation, comparison and shift - one clock cycle, multiplication and squaring - eight measures, division — twelve measures, extraction of the square root and exponentiation — twenty measures) - in the upper part of Fig. 9 (for the possibility of execution of the cyclogram, m = 11, n = 6, although these values can take arbitrary values.

A device for evaluating the distribution function of random variables and its tolerance boundaries in small samples (Figs. 3, 4, 5, 6, 7 and 8) contains the first 1 input registers, consisting of n elements, the second group of 2 input registers, consisting of m elements , first 3, second 4, third 5 and fourth 6 input registers, first 7, second 8, third 9, fourth 10, fifth 11, sixth 12, seventh 13, eighth 14, ninth 15, tenth 16, eleventh 17, twelfth 18 , thirteenth 19, fourteenth 20, fifteenth 21, sixteenth 22, seventeenth 23, eighteenth 24 and nineteenth 25 EZ, per the 26th, the second 27th, the third 28th, the fourth 29th, the fifth 30th and the sixth 31th multiplication blocks, the first 32, the second 33 groups of the EZ, each of which consists of n elements, the third 34 and the fourth 35 of the group of EZ, each of which consists of m elements, the first group of 36 subtraction blocks, consisting of n elements, the second 37, third 38, fourth 39, fifth 40, sixth 41 and seventh 42 groups of subtraction blocks, each of which consists of m elements, a group of 43 quadrators, consisting of n elements , first 44 and second 45 accumulative adders, first 46, second 47, third 48, fourth 49, fifth 50, sixth 51, seventh 52 and eighth 53 division blocks, first 54 and second 55 square root extraction blocks, first 56 and second 57 adders, first 58, second 59 and third 60 shift registers, exponentiation block 61, first 62, second 63, the third 64 and the fourth 65 groups of multiplication blocks, each of which consists of m elements, the first 66, the second 67, the third 68, the fourth 69, the fifth 70 and the sixth 71 groups of adders, each of which consists of m elements, the first 72, the second 73 , third 74, fourth 75, fifth 76 and sixth 77 groups of comparison blocks, each of which consists of m elements first 78, second 79, third 80, fourth 81, fifth 82 and sixth 83 groups of elements NOT, each of which consists of m elements, the first 84, second 85 and third 86 groups of division blocks, each of which consists of m elements first 87, second 88 and third 89 groups of registers, each of which consists of m elements, the first 90, second 91, third 92, fourth 93, fifth 94, sixth 95, seventh 96, eighth 97 and ninth 98 groups of matching schemes, each of which consists of m elements, the first 99, second 100, third 101, fourth 102, fifth 103 and sixth 104 of the memory group, each of which consists of m elements, a group of 105 accumulative adders, consisting of m elements, the first 106, second 107, third 108 and fourth 109 groups of output registers, each of which consists of m elements, first 110, second 111, third 112 and fourth 113 groups indication blocks, each of which consists of m elements, a fractional part elimination block 114, a first 115, a second 116, a third 117 and a fourth 118 subtraction blocks, a maximum value determining block 119, a comparison block 120, a group of 121 subtracting blocks modulo consisting of m elements, block 122 indication a clock generator 123 and a pulse distributor 124.

The presence of only one input at the second multiplication block 27 is explained by the fact that the second factor is a constant number equal to -0.035, which is “sewn” in advance in this block. The absence of a second input at the exponentiation block 61 indicates that the degree is based on a constant number equal to e (2.718), which is “wired” in advance in this block. The presence of only one input at the third block 28 of the multiplication is explained by the fact that the second factor is a constant number equal to 0.686, which is “wired” in this block. The absence of a second input at the fourth 49th and sixth 51th division blocks indicates that a constant number equal to one that is “sewn” in advance in these blocks serves as a dividend. The presence of only one input at the second adder 57 is explained by the fact that the second term is a constant number equal to one, which is “wired” in advance in this block. The absence of a second input at the first subtraction block 115 indicates that a constant number equal to one, which is “sewn” in advance in this block, serves as the subtraction. The presence of only one input for each element of the first group of 62 multiplication blocks is explained by the fact that the second factor of these elements is a constant number equal to one (for the first element), equal to m (for the mth element), which is “sewn” in advance in the corresponding elements . The absence of second inputs at the first 84 and second 85 groups of division blocks indicates that a constant number equal to one serves as a dividend, which is “wired” in advance in the elements of these groups. The first 99, second 100, third 101, fourth 102, fifth 103 and sixth 104 of the memory group have only a read input. The lack of an information input and a recording input is explained by the fact that in these blocks a value of zero is “sewn” in advance.

Block 114 elimination of the fractional part of the number is non-standard and can be built from the following standard elements: triggers and registers.

. На информационные входы каждого из элементов второй группы 2 входных регистров подаются теоретические величины F(x_j)_T функции распределения СВ $$\widehat{x}$$

. На информационные входы первого 3, второго 4, третьего 5 и четвертого 6 входных регистров засылаются соответственно объем выборки n СВ $$\widehat{x}$$

, величина β, определяемая из таблицы как функция доверительной вероятности и объема выборки СВ, число N подинтервалов разбиения интервала изменения СВ и критическое значение λ_кр для использования критерия Колмогорова. При этом управляющий сигнал на входы записи групп 1 и 2 и регистров 3, 4, 5 и 6 подается с первого выхода РИ 124, темп работы которого задается генератором 123 тактовых импульсов.A device for evaluating the distribution function of random variables and its tolerance boundaries for small samples works as follows (Figs. 3, 4, 5, 6, 7, and 8). The information inputs of each of the elements of the first group 1 of the input registers are written values x _i CB $$\widehat{x}$$

. At the information inputs of each of the elements of the second group of 2 input registers, the theoretical values F (x _j ) _{T of} the distribution function of CB $$\widehat{x}$$

. At the information inputs of the first 3, second 4, third 5 and fourth 6 input registers, respectively, the sample size n CB $$\widehat{x}$$

, the value of β, which is determined from the table as a function of the confidence probability and sample size of the CB, the number N of sub-intervals of the partition of the interval of change of the CB and the critical value of λ _cr for using the Kolmogorov criterion. Moreover, the control signal to the recording inputs of groups 1 and 2 and registers 3, 4, 5 and 6 is supplied from the first output of RI 124, the pace of which is set by the generator 123 clock pulses.

, направляется на вход делимого первого блока 46 деления, на вход делителя которого по сигналу с третьего выхода РИ 124 на вход считывания первого входного регистра 3 с его выхода подается значение объема выборки n. Это значение засылается также на входы первого блока 115 вычитания, первого блока 54 извлечения квадратного корня, второго блока 27 умножения и второго сумматора 57.According to the signal from the second output of RI 124 to the reading inputs of the first group 1 of the input registers, the values x _i from their outputs are sent to the inputs of the first 32 and second 33 groups of EZ, to the inputs from the first to the n-th, first accumulative adder. In addition, the values of x ₁ and x _{n are} sent to the inputs of the first 7 and second 8 EZ, respectively. From the output of the first accumulative adder 44 value $${\displaystyle \sum _{i=\mathrm{one}}^n{x}_i}$$

is sent to the input of the dividend first division block 46, the input of the divider of which, according to the signal from the third output of RI 124, the value of the sample size n is supplied to the read input of the first input register 3 from its output. This value is also sent to the inputs of the first subtraction block 115, the first square root extracting block 54, the second multiplication block 27, and the second adder 57.

, определяемое по формуле (11), направляется на входы вычитаемого первой группы 36 блоков вычитания. На входы уменьшаемого этой группы подается с выходов первой группы 32 ЭЗ величины x_i. С выходов группы 36 значения (x_i-m_x) записывается на входы группы 43 квадраторов, с выходов которой величины (x_i-m_x)² направляются на входы, с первого по n-й, второго накопительного сумматора 45, с выхода которого значение $${\displaystyle \sum _{i=1}^n{\left(x_i=m_x\right)}^2}$$

подается на вход делимого пятого блока 50 деления. На вход делителя этого блока через третий ЭЗ 48 с выхода первого блока 115 вычитания засылается величина (n-1). С выхода пятого блока 50 значение дисперсии d_x СВ $$\widehat{x}$$

, оцениваемое по формуле (10), направляется на вход второго блока 55 извлечения квадратного корня, с выхода которого величина $$\sqrt{d_x}$$

подается на второй вход первого блока 26 умножения. По сигналу с четвертого выхода РИ 124 на вход считывания второго входного регистра 4 с его выхода направляется значение β на первый вход первого блока 26 умножения, с выхода которого величина $$\beta \sqrt{d_x}$$

засылается на вход делимого третьего блока 48 деления.From the output of the first division unit 46, the value of the mathematical expectation m _x CB $$\widehat{x}$$

determined by the formula (11), is sent to the inputs of the deductible first group of 36 blocks of subtraction. The inputs of this group to be reduced are supplied from the outputs of the first group of 32 EZ values of x _i . From the outputs of group 36, the values (x _i -m _x ) are written to the inputs of the group of 43 quadrators, from the outputs of which the values (x _i -m _x ) ^{2 are} sent to the inputs from the first to the nth, second accumulative adder 45, from the output of which value $${\displaystyle \sum _{i=\mathrm{one}}^n{\left(x_i=m_x\right)}^2}$$

fed to the input of the divisible fifth division block 50. At the input of the divider of this block through the third EZ 48 from the output of the first block 115 subtraction is sent the value (n-1). From the output of the fifth block 50, the dispersion value d _x CB $$\widehat{x}$$

, estimated by the formula (10), is sent to the input of the second square root extraction unit 55, from the output of which the value $$\sqrt{d_x}$$

fed to the second input of the first block 26 multiplication. The signal from the fourth output of RI 124 to the read input of the second input register 4 from its output sends the value β to the first input of the first block 26 of multiplication, from the output of which the value $$\beta \sqrt{d_x}$$

sent to the input of the divisible third division block 48.

подается на входы четвертого 10 и пятого 11 ЭЗ, с выхода последнего из которых это значение направляется на вход делителя третьего блока 48 деления. С выхода этого блока значение точности ε, оцениваемое в помощью выражения (9), засылается на второй вход первого сумматора 56, на вход вычитаемого второго блока 116 вычитания и на входы шестнадцатого 22 и семнадцатого 23 ЭЗ. С выхода первого ЭЗ 7 величина x₁ подается на вход уменьшаемого второго блока 116 вычитания, с выхода которого нижняя граница а интервала изменения СВ $$\widehat{x}$$

направляется на вход вычитаемого третьего блока 117 вычитания и на входы девятого 15 и одиннадцатого 17 ЭЗ. С выхода второго ЭЗ 8 величина x_n засылается на первый вход первого сумматора 56, с выхода которого верхняя граница b интервала изменения СВ $$\widehat{x}$$

подается на вход уменьшаемого третьего блока 117 вычитания и на вход десятого ЭЗ 16. Величины а и b определены в соответствии с формулами (8).From the output of the first square root block 54 $$\sqrt{n}$$

fed to the inputs of the fourth 10 and fifth 11 EZ, from the output of the last of which this value is sent to the input of the divider of the third block 48 division. From the output of this block, the accuracy value ε, estimated using expression (9), is sent to the second input of the first adder 56, to the input of the subtracted second subtraction block 116, and to the inputs of the sixteenth 22 and seventeenth 23 EZ. From the output of the first EZ 7, the quantity x ₁ is supplied to the input of the reduced second subtraction block 116, from the output of which the lower boundary of the interval of change of CB $$\widehat{x}$$

is sent to the input of the deductible third subtraction unit 117 and to the inputs of the ninth 15 and eleventh 17 EZ. From the output of the second EZ 8, the quantity x _{n is} sent to the first input of the first adder 56, from the output of which the upper boundary b of the interval of variation of CB $$\widehat{x}$$

fed to the input of the reduced third subtraction unit 117 and to the input of the tenth EZ 16. The values of a and b are determined in accordance with formulas (8).

The difference (b-a) from the output of block 117 is directed to the inputs of the sixth block 51 of division and the eighth EZ 14 and to the input of the dividend second block 47 of division, to the input of the divider of which from the output of the third input register 5 the number N of sub-intervals of partitioning the interval of variation of CB is sent. The control signal to the read input of this register is supplied from the fifth output of RI 124. From the output of block 47, the value h of the step of dividing the interval of change of CB determined by formula (3) is sent to the input of the seventh EZ 13.

From the output of the second multiplication unit 27, the quantity (-0.035n) is supplied to the input of the exponentiation block 61, from the output of which the value exp (-0.035n) is sent to the input of the third multiplication unit 28. From the output of this block, the value of K, determined by formula (16), is sent to the first input of the fourth block 29 of multiplication, to the second input of which the value (b-a) is supplied from the output of the eighth EZ 14. From the output of block 29, the base of the contribution function S, determined by formula (15), is sent to the inputs of the first shift register 58 and the fourth division block 49. From the output of block 58, the value of S / 2 is sent to the input of the twelfth EZ 18, and from the output of block 49, the value 1 / S is fed to the information inputs of the first group of 87 registers.

засылаются на информационные входы первой 72 и второй 73 групп блоков сравнения и на пороговые входы четвертой 75 и шестой 77 групп блоков сравнения. На пороговые входы групп 72 и 73 направляются соответственно величины а и b с выходов одиннадцатого 17 и десятого 16 ЭЗ. Блоки сравнения группы 72 настроены следующим образом: если x_j<a, то на выходах будет сигнал; когда x_j≥а - сигнал будет отсутствовать. Блоки сравнения группы 73 настроены так: если x_j>b, то на их выходах появится сигнал; в противном случае, когда x_j≤b - сигнал будет отсутствовать.From the output of the seventh EZ 13, the value of h is sent to the input of the fifteenth EZ 21 and to the inputs of the first group 62 of multiplication, from the outputs of which the values (j-1) · h are sent to the second inputs of the first group 66 of adders. At the first inputs of this group, the value a is supplied from the output of the ninth EZ. Consequently, from the outputs of group 66, the values of the jth section estimated by formula (4), the densities and density distribution functions, and the CB distribution functions $$\widehat{x}$$

are sent to the information inputs of the first 72 and second 73 groups of comparison blocks and to the threshold inputs of the fourth 75 and sixth 77 groups of comparison blocks. At the threshold inputs of groups 72 and 73, values a and b, respectively, are sent from the outputs of the eleventh 17 and tenth 16 EZ. The comparison blocks of group 72 are configured as follows: if x _j <a, then there will be a signal at the outputs; when x _j ≥а - there will be no signal. The comparison blocks of group 73 are configured as follows: if x _j > b, then a signal will appear at their outputs; otherwise, when x _j ≤b - the signal will be absent.

направляется на информационные входы третьей группы 89 регистров.From the output of the twelfth EZ 18, the S / 2 value is supplied to the inputs of the subtracted second group of 37 subtraction blocks, to the inputs of the reduced fourth group of 39 subtraction blocks, and to the first inputs of the second group of 67 adders. From the output of the second group of 33 EZs, the values of x are sent to the second inputs of the second group of 67 adders, to the inputs of the reduced second group of 37 subtraction blocks, and to the inputs of the subtracted fourth group of 39 subtraction blocks, from the outputs of which the values (S / 2-x _j ) are sent to the second inputs of the third group of 68 adders. At the first inputs of this group, the value b is supplied from the output of the tenth EZ 16. Therefore, from the output of group 68, the values (S / 2 + bx _i ) are sent to the inputs of the third group 85 of division blocks, from the outputs of which the value $$\frac{\mathrm{one}}{S/2+b-x_i}$$

sent to the information inputs of the third group of 89 registers.

подается на информационные входы второй группы 88 регистров. Следует подчеркнуть, что управляющие сигналы на входы записи первой 87, второй 88 и третьей 89 групп регистров засылаются соответственно с шестого, седьмого и восьмого выходов РИ 124.From the outputs of the second group of 67 adders, the values (x _i + S / 2) are fed to the information inputs of the fifth 76 and sixth 77 groups of comparison blocks, to the inputs of the reduced third group 38 of subtraction blocks, the value of a is sent to the inputs of the subtracted one from the output of the thirteenth EZ 19. From the output of group 38, the values (S / 2 + x _i -a) are sent to the inputs of the first group of 84 division blocks, from the outputs of which the value $$\frac{\mathrm{one}}{S/2+x_i-a}$$

fed to the information inputs of the second group of 88 registers. It should be emphasized that the control signals to the recording inputs of the first 87, second 88 and third 89 groups of registers are sent respectively from the sixth, seventh and eighth outputs of RI 124.

From the outputs of the second group of 37 subtraction blocks, the values (x _i -S / 2) are sent to the information inputs of the fourth 75 and third 74 groups of comparison blocks, the threshold inputs of which are supplied from the output of the eleventh EZ 17 as a. The value b is sent to the threshold inputs of the fifth group 76 comparison blocks from the output of the tenth EZ 16. The comparison blocks of the third group 74 are configured as follows: if x _i -S / 2≥а, then there will be a signal at their outputs; when x _i -S / 2 <a - the signal will be absent. The comparison blocks of the fourth group 75 are configured as follows: if x _j ≤x _i -S / 2, then a signal will appear at their outputs; otherwise, when x _j > x _i -S / 2 - the signal will be absent. The comparison blocks of the fifth group 76 are configured as follows: if b≥x _i + S / 2, then there will be a signal at their outputs; when b <x _i + S / 2 - the signal will be absent. The comparison blocks of the sixth group of 77 are configured as follows: if x _j ≥x _i + S / 2, then a signal will appear at their outputs; otherwise, when x _j <x _i + S / 2 - the signal will be absent.

в соответствии с формулами (5), (6) и (7). Значения

направляются на входы соответствующего j-го накопительного сумматора группы 105, где осуществляется суммирование по i.Six groups of elements NOT during the operation of the device plays the following role. In some cases, a signal is necessary at the inputs of groups of matching circuits when it is not at the outputs of the corresponding group of comparison blocks. In this situation, you can use a group of elements NOT. Subsequently, using the first 72, second 73, third 74, fourth 75, fifth 76 and sixth 77 groups of comparison blocks, the first 78, second 79, third 80, fourth 81, fifth 82 and sixth 83 groups of elements NOT, the first 87, second 88 and third 89 groups of registers, the first 90, second 91, third 92, fourth 93, fifth 94, sixth 95, seventh 96, eighth 97 and ninth 98 groups of matching patterns, first 99, second 100, third 101, fourth 102, fifth 103 and sixth 104 groups of memory is carried out determination of the contribution function

in accordance with formulas (5), (6) and (7). Values

are sent to the inputs of the corresponding j-th accumulative adder of group 105, where summation over i is carried out.

подаются на первые входы четвертой группы 69 сумматоров, на вторые входы которой засылается с выхода четырнадцатого ЭЗ 20 величина 1{b-d}. С выхода группы 69 значения $$\frac{1}{\left(b-a\right)}+{\displaystyle \sum _{i=1}^n{P}_{x_i}\left(x_j\right)}$$

направляются на входы делимого третьей группы 86 блоков деления, на входы делителя которой с выхода шестого ЭЗ 13 подается величина (n+1). Следовательно, с выходов группы 86 на информационные входы первой группы 106 выходных регистров засылаются значения плотности распределения f(x_j) СВ $$\widehat{x}$$

, определяемой по формуле (2). При этом управляющий сигнал на входы записи группы 106 направляется с девятого выхода РИ 124. По сигналу на входы считывания первой группы 106 выходных регистров с десятого выхода РИ 124 значения f(x_j) подаются на входы первой группы 110 блоков индикации и на первые входы второй группы 63 блоков умножения, на вторые входы которой засылается величина шага разбиения h интервала изменения СВ.From the outputs of the group 105 accumulative adders values $${\displaystyle \sum _{i=\mathrm{one}}^n{P}_{x_i}}\left(x_j\right)$$

fed to the first inputs of the fourth group of 69 adders, the second inputs of which are sent from the output of the fourteenth EZ 20 value 1 {bd}. From the output of group 69 values $$\frac{\mathrm{one}}{\left(b-a\right)}+{\displaystyle \sum _{i=\mathrm{one}}^n{P}_{x_i}\left(x_j\right)}$$

are sent to the inputs of the divisible third group 86 of division blocks, to the inputs of the divider of which the value (n + 1) is supplied from the output of the sixth EZ 13. Therefore, from the outputs of group 86 to the information inputs of the first group 106 of output registers, the distribution density values f (x _j ) CB are sent $$\widehat{x}$$

defined by the formula (2). In this case, the control signal to the recording inputs of group 106 is sent from the ninth output of RI 124. By the signal to the read inputs of the first group 106 of output registers from the tenth output of RI 124, the values f (x _j ) are supplied to the inputs of the first group 110 of indication blocks and to the first inputs of the second group 63 blocks of multiplication, on the second inputs of which the value of the step of partition h of the interval of change of CB is sent.

From the outputs of the first and mth elements of the second group of 63 blocks of multiplication, the quantities f (x ₁ ) · h and f (x _m ) · h are supplied to the inputs of the second 59 and third 60 shift registers, respectively, where they are multiplied by 0.5 ( division into two). From the outputs of the remaining elements of group 63, the quantities f (x _j ) · h are sent to the first inputs of the fifth group of 70 adders, to the second inputs of which information from the previous elements is sent. From the outputs of the second register 59 and group 70, the values of the distribution function F (x _j ) determined by formula (1) are supplied to the information inputs of the second group 107 of output registers. In this case, the control signal is sent to the recording inputs of the group 107 from the eleventh output of the RI 124. By the signal to the read inputs of the second group 107 of the output registers from the twelfth output of the RI 124, the values F (x _j ) are sent to the inputs of the second group 111 of indication blocks, to the inputs of the subtracted group 121 units of subtraction modulo, to the inputs of the fourth group of 35 EZ, to the inputs of the reduced subsequent and to the inputs of the subtracted previous elements of the sixth group of 41 blocks of subtraction. In addition, the values of F (x _j ) are fed from the outputs of the adders of the fifth group 70 to the inputs of the previous ones being reduced, to the inputs of the subsequent elements of the fifth group 40 of the subtraction blocks and to the inputs of the third group 34 of the EZ.

Subsequently, using the fifteenth 21, sixteenth 22, seventeenth 23, eighteenth 24 and nineteenth 25 EZ, the fifth block 30 of the multiplication, the third 34 and the fourth 35 groups of EZ, the fifth 40, the sixth 41 and the seventh 42 groups of subtraction blocks, the seventh 52 and the eighth 53 division blocks, third 64 and fourth 65 groups of multiplication blocks, sixth group 71 adders, block 114 eliminating the fractional part of the number, and fourth subtraction block 118, the lower F (x _j -ε) _l and the upper F (x _j + ε) _l tolerant are determined boundaries in accordance with formulas (12) and (13). These values are sent to the information inputs of the third 108 and fourth 109 groups of output registers, respectively. In this case the control signals on the inputs of these registers are saved into the recording respectively with the outputs of the thirteenth and fifteenth RI 124. Based on the signals from the outputs of the fourteenth and sixteenth groups RI 124 to read input values 108 and 109 F (x _j -ε) _l and F (x _j + ε) _l are fed to the inputs of the third 112 and fourth 113 groups of indication blocks, respectively.

. С выхода блока 31 величина λ, определяемая по формуле (14), подается на информационный вход блока 120 сравнения, на пороговый вход которого засылается с выхода четвертого входного регистра 6 по сигналу на его вход считывания с восемнадцатого выхода РИ 124 критическое значение λ_кр параметра λ. Блок 120 сравнения настроен следующим образом: если λ<λ_кр, то на его выходе будет сигнал; в противном случае, когда λ≥λ_кр - сигнал будет отсутствовать. Наличие сигнала, который будет направляться на вход блока 122 индикации, приведет к его зажиганию, что свидетельствует о согласовании эмпирического и теоретического значений функции распределения. При отсутствии сигнала блок 122 будет темным: теоретическая функция распределения не согласуется с эмпирическими данными, т.е. гипотеза отклоняется. Порядок функционирования блоков устройства представлен на циклограмме его работы (фиг.9).Based on the signal from the seventeenth output of RI 124, the theoretical values of the distribution function F (x _j ) _T are fed to the read inputs of the second group of 2 input registers from their outputs to the inputs of the reduced group of 121 subtraction blocks. From the outputs of group 121, the differences between the theoretical and empirical values of F (x _j ) are sent to the inputs (from the first to the mth) of the maximum value determination unit 119, from the output of which the modulus of the maximum difference D between F (x _j ) _T and F ( x _j ) is sent to the second input of the sixth multiplication unit 31. On the first input of this block is sent from the output of the fourth block 10 EZ value $$\sqrt{n}$$

. From the output of block 31, the quantity λ determined by formula (14) is supplied to the information input of comparison block 120, the threshold input of which is sent from the output of the fourth input register 6 by a signal to its read input from the eighteenth output of RI 124, the critical value λ _{cr of} parameter λ . The comparison unit 120 is configured as follows: if λ <λ _cr , then there will be a signal at its output; otherwise, when λ≥λ _cr - the signal will be absent. The presence of a signal that will be sent to the input of the display unit 122 will lead to its ignition, which indicates the agreement of the empirical and theoretical values of the distribution function. In the absence of a signal, block 122 will be dark: the theoretical distribution function is not consistent with empirical data, i.e. the hypothesis is rejected. The functioning order of the device blocks is shown in the cyclogram of its operation (Fig. 9).

Thus, the technical result is achieved not at the expense of the mathematical apparatus, but at the expense of the technical means (blocks and elements) mentioned in the process of describing the operation of the device, which improves accuracy and enhances functionality by evaluating the tolerance limits of the distribution function of the CB.

The industrial applicability of the invention is justified by the fact that it can be used in different areas (industries) in the calculations associated with the assessment of the probabilistic characteristics of SW, when there is a small amount of statistical data.

Claims (1)

A device for evaluating the distribution function of random variables and its tolerance boundaries in small samples, containing the first group of input registers consisting of n elements, the second group of input registers consisting of m elements, from the first to nineteenth delay elements (ES), from first to fourth input registers, from the first to the sixth multiplication blocks, the first and second groups of EZ, each of which consists of n elements, the third and fourth groups of EZ, each of which consists of m elements, the first group of subtraction blocks, consisting of n elements, from the second to the seventh group of subtraction blocks, each of which consists of m elements, a group of quadrators consisting of n elements, the first and second accumulative adders, the first to eighth division blocks, the first and second square root blocks, the first and second adders, first, second and third shift registers, exponentiation block, from the first to fourth groups of multiplication blocks, each of which consists of m elements, the first to sixth groups of adders, each of which consists of m elements, the first to w there is a group of comparison blocks, each of which consists of m elements, the first to sixth groups of elements NOT, each of which consists of m elements, the first, second and third groups of division blocks, each of which consists of m elements, the first, second and the third group of registers, each of which consists of m elements, from the first to the ninth group of matching patterns, each of which consists of m elements, the first to sixth groups of storage devices (memory), each of which consists of m elements, a group of accumulative adders consisting of m elements, the first to fourth groups of output registers, each of which consists of m elements, the first to fourth groups of display units, each of which consists of m elements, the elimination unit of the fractional part of the number, the first to fourth subtraction blocks, block determine the maximum value, the comparison unit, the group of subtraction units modulo consisting of m elements, the display unit, the clock generator and the pulse distributor (RI), the clock input of which is connected to the output of the clock generator, is the first RI output - with write inputs of the first and second groups of input registers, first, second, third and fourth input registers, second output - with read inputs of the first group of input registers, third, fourth and fifth outputs - with read inputs of the first, second and third input registers, sixth, seventh and eighth outputs - with write inputs of the first, second and third groups of registers, respectively, ninth and tenth outputs - with write and read inputs of the first group of output registers, respectively, eleventh and twelfth outputs - with inputs of writing and reading respectively of the second group of output registers, thirteenth and fourteenth outputs - with inputs of writing and reading respectively of the third group of output registers, fifteenth and sixteenth outputs - with inputs of respectively writing and reading of the fourth group of output registers, seventeenth and eighteenth outputs - with read inputs, respectively, of the second group of input registers and the fourth input register, the information inputs of the first group of input registers are inputs given initial information on which the quantities x _i characterizing the values of the random variable (CB)

, the information inputs of the second group of input registers are inputs for setting the initial information, to which the quantities F (x _j ) _T are received, which characterize the theoretical values of the distribution function of CB

, the information inputs from the first to the fourth input registers are inputs of the input of the initial information, to which respectively a value n characterizes the sample size CB, a value β characterizing a value selected from the table depending on the confidence probability and sample size, a value N characterizing the number of the intervals of partitioning the interval of change of CB, and the quantity λ _cr characterizing the critical value of the parameter λ, the outputs of the first group of input registers are connected to the inputs of the first and second PP EZ, the outputs of which are connected to the inputs of the first and second groups of subtraction blocks reduced respectively, the outputs of which are connected respectively to the inputs of the quadrator group and to the information inputs of the third and fourth groups of comparison blocks, the outputs of each element of the first group of input registers are connected to the inputs, from the first to of the nth, first accumulative adder, and the outputs of the first and nth elements of this group are connected to the inputs of the first and second EZ, respectively, the outputs of which are connected respectively to the input, we decrease of the second second subtraction block and to the first input of the first adder, the output of which is connected to the input of the tenth EZ and the input of the reduced third subtraction block, the output of which is connected to the inputs of the sixth division block, the eighth block of the EZ and the input of the divisible second division block, the input of the divider of which is connected to the output the third input register, and the output with the input of the seventh EZ, the output of which is connected to the inputs of the first group of multiplication units and the input of the fifteenth EZ, the output of the first input register is connected to the inputs of the first subtraction block, p the first square root extraction unit, the second multiplication unit, the second adder and with the input of the divider of the first division unit, the input of the dividend of which is connected to the output of the first accumulative adder, and the output to the inputs of the subtracted first group of subtraction blocks, the output of the second input register is connected to the first input of the first multiplication unit, the output of which is connected to the input of the divisible third division unit, and the second input is the output of the second square root extraction unit, the input of which is connected to the output of the fifth division unit, the input whose divider is connected through the third EZ to the output of the first subtraction unit, and the input of the dividend to the output of the second accumulative adder, from the first to the n-th inputs of which are connected to the outputs, from the first to the n-th, of elements of the quadrator group, the output of the first square block the root is connected to the inputs of the fourth and fifth EZ, the outputs of which are connected respectively to the first input of the sixth multiplication unit and to the input of the divider of the third division unit, the output of which is connected to the second input of the first adder, to the inputs of the sixteenth and sem of the eleventh EZ and to the input of the subtracted second subtraction block, the output of which is connected to the input of the subtracted third subtraction block, and also to the inputs of the eleventh and ninth EZ, the output of which is connected to the first inputs of the first group of adders, the second inputs of which are connected to the outputs of the first group of multiplication blocks, and the outputs are with information inputs of the first and second groups of comparison blocks, with threshold inputs of the fourth and sixth groups of comparison blocks, the output of the second adder is connected to the input of the sixth EZ, the output of which is connected to the input mi of the divider of the third group of division blocks, the output of the second multiplication block is connected to the input of the exponentiation block, the output of which is connected to the input of the third multiplication block, the output of which is connected to the first input of the fourth multiplication block, the second input of which is connected to the output of the eighth EZ, and the output is with the input of the first shift register and the input of the fourth division block, the output of which is connected to the information inputs of the first group of registers, the output of the first shift register is connected to the input of the twelfth EZ, the output of which is connected to the inputs of the reduced fourth group of subtraction blocks, to the first inputs of the second group of adders and to the inputs of the subtracted second group of subtraction blocks, the output of the eleventh EZ is connected to the threshold inputs of the first and third groups of comparison blocks and the input of the thirteenth EZ, the output of which is connected to the inputs of the subtracted third group subtraction blocks, the outputs of which are connected to the inputs of the first group of division blocks, the outputs of which are connected to the information inputs of the second group of registers, the outputs of which are connected to the seventh inputs of UPPA of accumulative adders, the output of the tenth EZ is connected to the threshold inputs of the second and fifth groups of comparison blocks and to the first inputs of the third group of adders, the outputs of which are connected to the inputs of the second group of division blocks, the outputs of which are connected to the information inputs of the third group of registers, the outputs of which are connected to the eighths the inputs of the group of accumulative adders, the outputs of the second group of EZ are connected to the inputs of the reduced second group of subtraction blocks, to the inputs of the subtracted fourth group of subtraction blocks and to the second inputs of the second group of adders, the outputs of which are connected to the information inputs of the fifth and sixth groups of comparison blocks and the inputs of the reduced third group of subtraction blocks, the outputs of the first, second, third, fourth, fifth and sixth groups of comparison blocks are connected to the inputs of the first, second, third , the fourth, fifth and sixth groups of elements NOT, the outputs of the first group of comparison units are also connected to the second inputs of the first group of matching circuits, the outputs of which are connected to the read inputs of the first group of memory, the outputs of which oh are connected to the second inputs of the group of accumulative adders, the outputs of the second group of comparison blocks are also connected to the second inputs of the ninth group of matching circuits, the outputs of which are connected to the read inputs of the sixth group of memory, the outputs of which are connected to the sixth inputs of the group of accumulative adders, the outputs of the third group of comparison blocks, also connected to the first inputs of the second, fifth and fourth groups of coincidence circuits, the outputs of which are connected to the read inputs of the first group of registers, the fifth and second groups 3, respectively Y, the outputs of which are connected respectively to the ninth, fifth and fourth inputs of the group of accumulative adders, the outputs of the fourth group of comparison units are also connected to the second inputs of the fourth and seventh groups of matching circuits, the outputs of which are connected to the read inputs of the fourth group of memory, the outputs of which are connected to the third inputs groups of accumulative adders, the outputs of the fifth group of comparison blocks are also connected to the third inputs of the fourth, second and fifth groups of matching circuits, the outputs of the sixth group of comparison blocks under are also connected to the second inputs of the fifth and sixth groups of matching circuits, the outputs of which are connected to the reading inputs of the third group of memory, the outputs of which are connected to the first inputs of the group of accumulative adders, the outputs of the first group of elements are NOT connected to the second inputs of the third group of matching circuits, the outputs of which are connected to read inputs of the second group of registers, the outputs of which are connected to the seventh inputs of the group of accumulative adders, the outputs of the second group of elements are NOT connected to the third inputs of the eighth group of matching circuits the outputs of which are connected to the read inputs of the third group of registers, the outputs of which are connected to the eighth inputs of the group of accumulative adders, the outputs of the third elements are NOT connected to the first inputs of the third, sixth and first groups of matching circuits, the outputs of the fourth group of elements are NOT connected to the second inputs of the second and the eighth group of matching circuits, the outputs of the fifth group of elements are NOT connected to the first inputs of the seventh, eighth and ninth groups of matching circuits, the outputs of the sixth group of elements are NOT connected to the fourth input I will give the second group of coincidence circuits to the third inputs of the third group of coincidence circuits, the outputs of the group of accumulative adders are connected to the first inputs of the fourth group of adders, the second inputs of which through the fourteenth EZ are connected to the output of the sixth division block, and the outputs to the inputs of the divided third group of division blocks, the outputs of which are connected to the information inputs of the first group of output registers, the outputs of which are connected to the inputs of the first group of display units and to the first inputs of the second group of multiplication blocks, the second input which are connected to the output of the fifteenth EZ, the output of which is also connected to the input of the divider of the seventh division unit and to the input of the eighteenth EZ, the output of which is connected to the input of the nineteenth EZ and the first input of the fifth multiplication block, the second input of which is connected to the output of the elimination unit of the fractional part of the number, the input of which is connected to the output of the seventh division block, the input of the dividend of which is connected to the output of the sixteenth EZ, the output of the seventeenth EZ is connected to the input of the reduced fourth subtraction block, the input of which is subtracted connected to the output of the fifth multiplication block, and the output to the input of the divisible eighth division block, the input of the divider of which is connected to the output of the nineteenth EZ, and the output to the first inputs of the third and fourth groups of multiplication blocks, the outputs of the first and mth elements of the second group of multiplication blocks connected to the inputs of the second and third shift registers respectively, the output of the last of which is connected to the first input of the mth element of the fifth group of adders, the output of the second shift register is connected to the information input of the first element of the second pp of output registers, to the input of the reduced first element of the fifth group of subtraction blocks, to the input of the first element of the third group of EZs and to the second input of the first element of the fifth group of adders, the first inputs of which, in addition to the last element, are connected to the outputs of the corresponding elements of the second group of multiplication blocks, and the outputs of each element of the fifth group of adders, except the last, with the second inputs of subsequent elements, the outputs of each subsequent element of this group are connected to the inputs of the diminished corresponding ele cops of the fifth group of subtraction blocks, and the outputs of each previous element of the fifth group of adders to the inputs of the same elements of the fifth group of subtraction blocks, the outputs of which are connected to the second inputs of the third group of multiplication blocks, the outputs of the fifth group of adders are also connected to the inputs of the third group of EZ and information inputs of the second group of output registers, the outputs of which are connected to the inputs of the fourth group of EZ, the second group of display units, and the inputs of the subtracted group of subtraction blocks modulo, the outputs of each of the next subsequent element of the second group of output registers are connected to the inputs of the reduced corresponding elements of the sixth group of subtraction blocks, and the outputs of each previous element of the second group of output registers are connected to the inputs of the subtracted same elements of the sixth group of subtraction blocks, the outputs of which are connected to the second inputs of the fourth group of multiplication blocks, the outputs of which are connected to the first inputs of the sixth group of adders, the second inputs of which are connected to the outputs of the fourth group of EZ, and the outputs are with information inputs the fourth group of output registers, the outputs of which are connected to the inputs of the fourth group of indication blocks, the outputs of the third group of multiplication blocks are connected to the inputs of the subtracted seventh group of subtraction blocks, the inputs of which are reduced are connected to the outputs of the third group of EZ, and the outputs are to the information inputs of the third group of output registers, the outputs of which are connected to the inputs of the third group of indication blocks, the outputs of the second group of input registers are connected to the inputs of the reduced group of subtraction blocks modulo, the outputs of which oedineny first through m-th input block to determine the maximum value, the output of which is connected to the second input of the sixth multiplier, whose output is connected to the data input of the comparator, a threshold input connected to the output of the fourth input register and the output to the input of the indication unit.

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