RU2467377C1 - Method and device for multiplying numbers in "1 out of 4" code - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to computation and can be used to construct computing means in data processing and control systems. The device has a multiplicand register, a multiplier register, an adder, a result register and a "1-4" control circuit, a control device, a register for storing the result of multiplying the multiplicand by two, a register for storing the result of multiplying the multiplicand by three and two data transmission lines.

EFFECT: faster operation and higher reliability of the processed information, fewer hardware components used and low power consumption.

2 cl, 2 dwg

Description

The invention relates to the field of computer technology and can be used to build high-speed computing tools in systems with increased reliability of the processed and issued data.

A multiplication device is known (RU patent for invention No. 2148270, filed on 05.27.1998, published 04/27/2000, IPC G06F 7/49), containing the register of the first multiplier, the register of the second multiplier, two multipliers, the register of private products, combiner, the result block, clock distributor (control device).

The disadvantages of this multiplication device are:

- in the process of obtaining the product, the operations of obtaining partial works, summing and fixing the result of the multiplication are sequentially performed, which entails large time costs, corresponding volumes of equipment and power consumption;

- lack of control in the operating mode, which reduces the reliability of the information received.

A device for multiplying numbers is known (RU patent for invention No. 2021633, filed July 10, 1991, published October 15, 1994, IPC G06F 7/52), containing n single-digit multiplication nodes (n is the length of the multiplicand), two groups of n buffer registers, n combination adders of the first group, (n + 1) combination adders of the second group, (n + 1) registers of the intermediate result, n transfer triggers.

This device has all the disadvantages of the previous one.

The closest technical solution (prototype) with respect to the claimed one is a device for multiplying numbers in the code “1 of 4” (RU patent for the invention No. 2251144, filed October 28, 2003, published April 27, 2005, IPC G06F 7/52), containing the register multiplicative, a notebook shift register (multiplier register), a partial product block, an adder block (adder), a result register and a control block (control scheme “1-4”).

The disadvantage of this multiplication device that works with numbers in the “1 out of 4” code is the need to perform the operation of forming partial products when obtaining the final result — the product of two numbers, which leads to certain time costs, thereby limiting the speed of operation of the multiplication device, increases its volume and power consumption.

The problem to which the proposed technical solution is directed is to create a device for multiplying numbers in the code "1 of 4", in which the disadvantages of the prototype are eliminated in the process of obtaining the product of two numbers.

The feasibility of creating devices, systems that work with the numbers presented in the code “1 of 4” is sufficiently justified, shown in the materials of inventions for which patents RU No. 22251143 IPC G06F 7/49, No. 22251144 IPC G06F 7/52, etc.

When representing a number in the “1 of 4” code, each of the n quadruple digits of the number has only one unit in its composition, i.e. all possible combinations of this code are of the form: 0 = 0001, 1 = 0010, 2 = 0100, 3 = 1000.

Therefore, the procedure for obtaining a partial product is reduced to multiplying the multiplicable by one of these values.

The specified result is achieved by the fact that in the multiplication device containing the register of the multiplier, the register of the multiplier, the adder, the register of the result and the control circuit "1-4", a control device, a register for storing the result of the multiplication of the multiplier by two, a register for storing the result of multiplying the multiplier by three , and the first M1 and second M2 data transmission lines, while

the multiplier on the buses X1 ÷ Xn goes to the input of the register of the multiplier (Rg. 1), the multiplier on the buses U1 ÷ Un goes to the input of the register of the multiplier (Rg. 2), the output of the “Record” signal goes to the first inputs of the register of the multiplier, register of the multiplier, register of the result (Section 3) and the control device, the synchronizing pulses are fed to the second input of the control device, in the control device, the first output of the control signals is coupled to the second input of the result register, the second output to the second input of the register of the multiplicand, the third output to the second input of the register multiplier, the fourth output - with the first input of the register for storing the result of multiplying the multiplicable by two (Rg. 0100), the fifth output - with the first input of the register for storing the result of multiplying the multiplicable by three (Rg. 1000), the four outputs of the least four-digit digit of the multiplier register are paired with four inputs of the control device, information transfer from registers Рg.1, Рg.0100 and Рg.1000 to the first group of adder inputs (See) is carried out along the M1 highway, information is transmitted from the output of register Рg.3 to the input of registers Рg.0100, Рг .1000, to an external device (WU) to the second group of inputs of the adder is carried out via the M2 highway, along the same highway to the second group of inputs of the adder information is transmitted from the second output of Rg.1, bitwise from the 1st to n + 1 the outputs of the adder go to the corresponding inputs of Rg.3, from the outputs of which (1 ÷ n) information is fed to the corresponding inputs of the control circuit "1-4" (Sc. To "1-4"), Sc.k. “1-4” bitwise (Osh.1 ÷ Osh.n) gives signs of error to an external device.

The invention is illustrated in the drawing (Figure 1), which shows a structural diagram of the multiplication device and a time diagram (Figure 2) of its operation.

Figure 1 marked:

1 - register of the multiplicative (Rg. 1);

2 - register of the multiplier (Rg.2);

3 - control device;

4 - control circuit in the code “1 of 4” (c.k. “1-4”);

5 - result register (Rg.3);

6 - adder (See);

7 - register for storing the result of multiplying the multiplicable by two (Rg.0100);

8 - register for storing the result of multiplying the multiplicable by three (Rg. 1000);

M1 - data transmission line from Rg.1, Rg.0100, Rg.1000 to See;

M2 - data transmission line from Rg.3 to See, Rg.0100, Rg.1000 and VU.

The proposed device multiplication works as follows. At the input Рg.1 1 and Рg.2 2, the data of the multiplier (on the buses X1 ÷ Xn) and the multiplier (on the buses У1 ÷ Уn) are set.

On the trailing edge of the “Record” signal, data is recorded in Rg1 1, Rg2.2, set to “0” Rg3 5 and the control device 3 is started, which connects the first to M1 highway, and the second Rg.1 1 outputs to the M2 highway, those. feeds the first and second inputs of the adder 6 data from the specified register. The adder 6 is combination, therefore, after the transition process, a code similar to twice the code in the register Рg.1 is installed at its output. The leading edge of the clock following the “Write” pulse, the data from the adder 6 are overwritten in Рg.3 5. The trailing edge of this pulse Rg1 1 is disconnected from the M2 highway, and the register of Rg.3 5 is connected to this highway. The leading edge of the second (after the “Record” pulse) clock is the contents of Pr 3 5 are rewritten in Pr 0100 7, and the trailing edge of this clock is the new contents of adder 6 (the triple content Pr 1 1) is rewritten in Pr 35.

By the rising edge of the third (after the “Recording” pulse) clock, the contents of Pr.3 5 are rewritten into Pr.1000 8. The trailing edge of this pulse is set to “0” Pr.3.5, and the output of Pr.1 1 is disconnected from the M1 trunk. The preparatory cycle for obtaining the product of two numbers is completed. It should be noted that Rg.3 5, adder 6, Rg.0100 7 and Rg.1000 8 have a bit capacity of n + 1, since during the addition operations transfer can occur.

The process of obtaining the product of two numbers consists of n cycles, where n is the number of bits of the multiplier. Each of the cycles begins with the control device analyzing the 3 states of the least four-digit position of the register of the factor Р.2.2 2. As mentioned above, each of the bits of the number represented in the code “1 of 4” contains only one of the combinations - 0001, 0010,0100 and 1000.

At most, each of the cycles of obtaining the product contains the following operations:

- analysis of the low order of Rg.2 2;

- transfer of information from Rg.1 1 (Rg.0100 7, Rg.1000 8) to See 6;

- summation of the values of Pr.1 1 (Pr.0100 7, Pr.1000 8) and Pr.3 5;

- transmission See 6 → Рg.3 5;

- a shift by one bit in the direction of the lower digits Rg.2 2 and Rg.3 5.

This volume of operations is performed when one of the values 0010, 0100 and 1000 is recorded in the low order of Rg.2 2, while: the value 0010 corresponds to the transfer of information from Rg.1 1;

- value 0100 - from Pr.0100 7;

- value 1000 - from Rg. 1000 8.

In the case when the value 0001 is recorded in the junior bit of Pr.2.2, the cycle of obtaining the product is reduced to performing two operations: analysis of the state of the least significant digit of Pr.2.2;

- shift towards the lower digits Rg.2 2 and Rg.3 5.

Thus, the proposed method and device for multiplying numbers in the code “1 of 4” allows you to create a device in which the time of the multiplication cycle does not depend on the value of the number code, but is determined only by the number of operations of summation, with a sufficiently high degree of reliability of operation, a relatively low amount of used elemental base and power consumption.

The presented drawing and description of the multiplication device, as well as the existing elemental base, make it possible to manufacture it industrially and, most importantly, in the form of LSI.

Claims (2)

1. The method of multiplying numbers in the code “1 of 4”, which consists in receiving the data of the multiplier and the multiplier, storing them, obtaining the result of multiplying the multiplier by the factor, monitoring and outputting the results of multiplication to external devices, characterized in that, in order to reduce execution time the procedure of multiplying two numbers in the code “1 of 4”, the operation of obtaining partial works is excluded from this procedure, in preparatory mode, the previous procedure for receiving the work, double and triple values are generated and stored multiplicand and the result of analysis of the contents of each quaternary discharge (0001, 0010, 0100, 1000) carried out a factor summation intermediate product values with one value of the second term - zero to the value of the multiplicand, doubling or tripling the value of the multiplicand. 2. The device of multiplication of numbers in the code “1 of 4”, containing the register of the multiplier, the register of the multiplier, the adder, the register of the result and the control circuit, characterized in that it additionally includes a control device, a register for storing the result of the multiplication of the multiplier by two, a register for storing the result multiplying the multiplier by three and the first and second data transmission lines, while the multiplier on the buses X1 ÷ Xn goes to the input of the register of the multiplier, the multiplier on the buses U1 ÷ Уn goes to the input of the multiplier register, the output of the “Record” signal goes to the first the inputs of the register of the multiplier register of the multiplier, the register of results and the control device, the synchronizing pulses are fed to the second input of the control device, in the control device, the first output of the control signals is coupled to the second input of the result register, the second output is with the second input of the register of multiplied, the third output is with the second the input of the register of the multiplier, the fourth output - with the first input of the register for storing the result of multiplying the multiplier by two, the fifth output - with the first input of the register for storing the result of multiplying of the multiplier, three, four outputs of the least four-digit discharge of the register of the multiplier are interfaced with the four inputs of the control device, information is transmitted from the register of the multiplier, the register for storing the result of multiplying the multiplier by two, the register for storing the result of multiplying the multiplier by three by the first group of adder inputs is carried out along the first data transmission line , transferring information from the output of the result register to the input of the storage register of the result of multiplying the multiplicable by two, the register of storing the result of multiplying the multiplicative three, an external device and a second group of inputs of the adder are carried out on the second data transmission line, on the same line information is transferred to the second group of inputs of the adder from the second output of the register of the multiplier, bitwise from the 1st to n + 1 outputs of the adder are fed to the corresponding inputs of the register of the result, the outputs from the 1st to n of which are interfaced with the corresponding inputs of the control circuit, the control circuit, bit by bit (Osh 1 ÷ Osh.n), gives signs of error to the external device.

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