RU2510072C1 - Apparatus for performing division and square-rooting - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus enables to perform division and square-rooting in a floating point format according to the IEEE 754 standard with single or double accuracy. Input operands can be presented in a floating point format with both single and double accuracy. The apparatus includes a unit for selecting the power and mantissa of input operands, a circuit for controlling a three-step conveyor of an input register unit, an input register unit, a circuit for controlling an adder unit and a multiplier unit, a multiplier unit, an adder unit and a unit for generating computation results.

EFFECT: faster operation, enabling execution the function of a device for division and a device for square-rooting in a single apparatus.

1 dwg, 1 tbl

Description

Technical field

The invention relates to computer technology and can be used in digital computers and structures, in arithmetic coprocessors of floating point information and measuring systems, in systems for calculating the position and motion parameters of robotic systems as an arithmetic unit.

State of the art

[1], в котором вычисление функции производится за n циклов (n - число разрядов двоичного кода значения квадратного корня) с вычислением за каждый цикл одной значащей цифры результата путем выполнения в каждом цикле трех операций с разрядной цифрой а_i результата.A device for calculating the square root $$\left(\sqrt{x}\right)$$

[1], in which the calculation of the function is performed in n cycles (n is the number of bits of the binary code of the square root value) with the calculation for each cycle of one significant digit of the result by performing three operations in each cycle with the digit digit a _{i of the} result.

The method for implementing the function calculation corresponds to the method of converting analog signals to a digital code by successive bitwise approximations with the calculation of a single significant digit at each clock cycle.

The disadvantage of this method and device is the low speed. For one iterative cycle, it is necessary to square the test value of the operand, compare it with the value of x, and based on the result of the comparison, get one binary digit of the square root value, and the device does not have the possibility of a division operation.

A device for extracting the square root [2], containing the input and output registers block squaring, a comparison circuit and a block for selecting numbers of the result.

The disadvantage of this device is the low speed, since the calculations are carried out by the method of successive iterations, also in the device there is no possibility of a division operation.

A device for extracting the square root [3], containing a multiplication unit, a division unit, a first memory unit, a register of the result. The disadvantage of this device is the difficulty of implementation, due to the need to use a large capacity memory block, which is associated with the use of casting interpolation method to calculate the values of the function between the reference points. So for the described device having the length of the bit grid of the input and output words equal to (n + 1), including the sign bit, a storage device with a capacity of Q ₀ = (n + 1) · 2 ^n-4 bits is required. The device also does not allow division operations on input numbers.

A device for dividing [4] is known, comprising two remainder registers, a divisor register, a private register, a forced rounding adder, an inverse computation unit, two adders, two multiplication units, a first switch, a selector, a subtractor, a NOT element and a microprogram control unit, the device data input is connected to the information input of the divider register and to the first information input of the first switch, the output of which is connected to the information input of the first remainder register, the output of the first adder is are output by the result of the device and connected to the input of the reduced subtracter, the inputs of the subtracted and the loan of which are connected to the outputs of the first and second groups of the first multiplication block, respectively, the outputs of the difference and the loan of the subtractor are connected to the second information input of the first switch and the information input of the second register, respectively, the outputs of the senior the bits of the first and second registers of the remainder are connected to the first and second information inputs of the second adder, respectively, the output of the least significant bits of which connected to the first information input of the second multiplication block, the second information input of which is connected to the output of the reciprocal calculation unit, the input of which is connected to the output of the forced rounding adder, the information input of which is connected to the output of the upper bits of the divider register, the output of which is connected to the first information input of the first block multiplication, the second information input of which is connected to the information input of the least significant bits of the register of private and the output of the selector, the information input which is connected to the output of the second multiplication block, the transfer input of the forced rounding adder is the input of the logical unit of the device, the high-order output of the second adder is connected to the input of the element NOT, the output of which is connected to the control input of the selector, the synchronization input of the device is connected to the sync inputs of the first and second balance registers, register divider, private register and microprogram control unit, the first output of which is connected to the first control input of the first switch and the input set to “O” of the second remainder register, the second output of the firmware control unit is connected to the second control input of the first switch and the write enable entries of the second remainder register and private register, the third and fourth outputs of the firmware control unit are connected to the write enable inputs of the first remainder register and divider register accordingly, the fifth output of the microprogram control unit is the output of the sign of the end of the division of the device, characterized in that the second and t there are switches, wherein the output of the first remainder register is connected to the first information input of the second switch, the second information input of which is connected to the first output of the private register, the output of the second remainder register is connected to the first information input of the third switch, the second information input of which is connected to the second output of the private register, the output of the second switch is connected to the first information input of the first adder, the second information input of which is connected to the output of the third switch, p The first control inputs of the second and third switches are connected to the second output of the microprogram control unit, the sixth output of which is connected to the second control inputs of the second and third switches.

The disadvantage of this device is the design complexity and the inability to perform the square root extraction operation.

The closest in technical essence to the proposed technical solution is a device for division [5], containing a dividend register, a divisor register, a private adder, a forced rounding-off adder, a truncated number division unit, a private digits register, three switches and a control unit, the divider outputs and dividends through the data bus, the devices are connected to the information inputs of the divider register and the information inputs of the first group of the first switch, respectively, the outputs of the first switch are connected with the information inputs of the dividend register, the information inputs of the first group of the second switch are connected to the outputs of the highest bits of the dividend via the device data bus, the output of the highest bits of the divider register is connected to the information inputs of the first group of the third switch, the information inputs of the second group of which are connected to the outputs of the senior bits of the divider device data bus, the outputs of the third switch are connected to the information inputs of the adder forced rounding of the divider the nose of which is connected to the input of the logical unit of the device, the outputs of the compulsory rounding adder are connected to the inputs of the divider of the truncated numbers division unit, the divisible inputs of which are connected to the outputs of the second switch, the outputs of the truncated numbers division unit are connected to the information inputs of the private digits register, the outputs of which are connected to the junior inputs bits of the adder private, the synchronization input of the device is connected to the sync inputs of the divisible and divisor registers, the adder private, the register of digits private and b control lock, the first output of the control unit is connected to the enable input of the register of the divider and the input to the setting “O” of the private adder, as well as to the first control inputs of the first, second and third switches, the second output of the control unit is connected to the second control inputs of the first, second and the third switch and the admission write enable input of the adder private, the third output of the control unit is connected to the enable input of the register of the dividend and register of digits of the private, the fourth output of the control unit is One of the signs of the end of the division of the device, the outputs of the adder private are the output of the private device, characterized in that the device comprises a partial product shaper, an adder, two adders and an OR element NOT, the output of the divider register being connected to the first information input of the partial product shaper, the second information the input of which is connected to the output of the register of digits of quotient, the output of the register of the dividend is connected to the first information input of the summing unit, the second information One of the summing unit is connected to the output of the partial product shaper, the outputs of the sums and transfers of the summing unit are connected to the inputs of the first and second terms of the first adder, respectively, the outputs of the highest bits of the sums and transfers of the summing unit are connected to the inputs of the first and second terms of the second adder, respectively, the output of the second adder is connected with the information inputs of the second group of the second switch, the output of the first adder is connected to the information inputs of the second group of the first switch, Exit significant bit of the first adder is connected to a first input of OR - NOT whose output is connected to the setting input of a "O" digit register private, the first control unit output is connected to the second input of OR - NOT.

The disadvantages of the device are the inability to perform the operation of extracting the square root, operations in formats that comply with the IEEE 754 standard, and high complexity, low speed.

Disclosure of invention

Solved by the claimed invention, the task is to eliminate the disadvantages of analogues.

The claimed device for dividing and extracting the square root allows the calculation in floating point format in accordance with the IEEE 754 standard with single (the result is represented by a 32-bit binary number) and double (the result is represented by a 64-bit binary number) accuracy, and the input operands can be presented in floating point format as single or double precision.

The technical result consists in increasing speed, adding new functionality without complicating the device, namely the functionality of the device for dividing and the device for extracting the square root in a single device.

The technical result is achieved by the fact that the square root division and extraction device contains a degree and mantissa extraction unit for input operands, the first input of which is the device input, a three-stage conveyor control circuit, the input of which is connected to the output degree and mantissa extraction unit input operands, fifth output of the control circuit a three-stage conveyor is connected to the second input of the degree and mantissa allocation unit of the input operands, the input register block connected to the three-stage conveyor, the odes / outputs of which are connected to the first, second and third inputs / outputs of the three-stage conveyor control circuit, respectively, the adder and multiplier control circuit, the first input of which is connected to the fourth output of the three-stage conveyor control circuit, a multiplier unit whose input is connected to the first output of the circuit control blocks of the adder and multiplier, and the output is connected to the second input of the control circuit of the blocks of the adder and multiplier, the adder block, the input of which is connected to the second output of the control circuit units of the adder and multiplier, and the output with the third input of the control circuit of the adder and multiplier blocks, a block for generating calculation results, the input of which is connected to the third output of the control circuit of the adder and multiplier blocks, and the output is the output of the device.

Brief Description of the Drawings

The features and essence of the claimed invention are explained in the following detailed description, illustrated by drawings, which shows the following:

Figure 1 - structural diagram of the claimed device for dividing and extracting the square root, where:

1 - block allocation of the degree and mantissa of the input operands;

2 is a control diagram of a 3-stage conveyor block input registers;

3 - block input registers;

4 is a control circuit of an adder block and a multiplier block;

5 - block multipliers;

6 - block adders;

7 - unit for generating calculation results.

The implementation of the invention

, где P - делимое или число, из которого извлекается квадратный корень, A_i-1 - промежуточный результат, полученный на предыдущей итерации, B_i,j - вектор приближений текущей операции, f(A_i-1+B_i,j) - арифметическая операция, обратная вычисляемой, для операции деления - умножение на делитель, для операции извлечения квадратного корня - возведение в степень, при этом результатом i итерации является число $$A_i=A_{i-1}+B_{i,k}(2)$$

, где B_i,k - значение приближения из вектора B_i,j, удовлетворяющее условию (1), одна итерация вычисления содержит операцию умножения и операцию вычитания промежуточных результатов, отличающиеся тем, что с целью повышения быстродействия операция извлечения квадратного корня может выполняться одновременно над двумя независимыми входными числами, результат и входные данные, флаги выполнения операций соответствуют стандарту IEEE 754 для чисел в формате плавающей точки одинарной и двойной точностей.The division and extraction of the square root occurs on the same elements of the device in order to improve performance. The 3-stage conveyor allows you to download the source data and transfer it for further processing from any stage, being guided by loading blocks of multipliers and adders, blocks of multipliers and adders together with conveyor registers produce calculation according to the division algorithm “with preservation of the remainder”, and the extraction of the square root “without preservation of the remainder” in order to unify the relations of the blocks of multipliers and sum s operations for division and square root extraction, the result of each iteration is determined by the condition: $$\min \left(P-f\left(A_{i-\mathrm{one}}+B_{i,j}\right)\right)>0(\mathrm{one})$$

, where P is the dividend or the number from which the square root is extracted, A _i-1 is the intermediate result obtained at the previous iteration, B _{i, j} is the approximation vector of the current operation, f (A _i-1 + B _{i, j} ) is the arithmetic operation is the inverse of the calculated one, for the division operation is multiplication by the divisor, for the square root extraction operation is raising to a power, and the result of the iteration i is the number $$A_i=A_{i-\mathrm{one}}+B_{i,k}(2)$$

, where B _{i, k} is the approximation value from the vector B _{i, j} satisfying condition (1), one calculation iteration contains the operation of multiplication and the operation of subtracting intermediate results, characterized in that, in order to improve performance, the square root extraction operation can be performed simultaneously on two independent input numbers, the result and the input data, operation flags correspond to the IEEE 754 standard for single and double precision floating point numbers.

The degree and mantissa allocation unit of the input operands 1 parses the binary numbers received at the input in the floating point format. It extracts the degree and mantissa from them from the input operands, determines the signs of the result, such as division by zero, a sign of zero result, etc. Data from the output of the degree and mantissa selection block of the input operands 1 goes to one of the stages of the register conveyor block of the input registers 3, free from calculation. In the case of filling all stages of the conveyor 3, the control circuit of the 3-stage conveyor of the block of input registers 2 generates a busy signal that impedes further input of numbers to the input of the parsing unit and preparation of input data. The busy signal is removed immediately after the completion of the first operation. Each block of input registers 3 contains latches of a divisor, dividend or number, from which the square root, degrees of the result, sign of the result, signs of the result, as well as the number of the iteration cycle and the intermediate value of the result, are extracted.

Data from the input / output of one of the blocks of the input registers 3 through the control circuit of the 3-stage conveyor of the block of the input registers 2 and the control circuit of the adder block and the block of multipliers 4 are supplied to calculate the intermediate result of dividing or extracting the square root. Based on the iteration cycle number and the intermediate value of the result obtained from the previous cycle, the control circuit of the adder block and the block of multipliers 4 forms a vector of possible results of the current cycle by bitwise merging the intermediate value of the result obtained from the previous cycle and a set of approximation constants. The approximation constants are members of the series 0, 1, ... 2 ^K - 1, where K is the number of bits of the result determined in one iteration. The position for merging is determined by the control circuit of the adder block and the multiplier block 4 based on the iteration cycle number. The data from the output of the control circuit of the adder block and the multiplier block 4 is fed to the input of the multiplier block 5, where in the case of division of two numbers, the divider and the vector of possible results of the current cycle are multiplied, and in the case of root extraction, the vectors of possible results of the current cycle are squared. The result is recorded in the control circuit of the adder block and the block of multipliers 4 in the first step of the iteration. In the second step of the iteration, a test subtraction and determination of the intermediate value of the result as an element of the vector of possible results, providing the minimum positive remainder from the subtraction, are performed. In the case of division, the result of the multiplication is subtracted from the dividend, and in the case of extracting the square root, the subtraction is performed from the number from which the square root is extracted. The minimum positive residue from the subtraction is determined by the control circuit of the adder block and the block of multipliers 4 by changing the sign of the difference result using the logical combinational circuit included in the control circuit of the adder block and the block of multipliers. The blocks of the adder 6 and the blocks of the multipliers 5 to perform the division on the first and second clock cycles, the calculations perform the operations included in the current and next iteration cycle, and in the case of extracting the square root within one iteration cycle, the operations are performed sequentially in the first and second cycles. To speed up the extraction of the square root, blocks 5 and 6 have the ability to extract the square root of 2 numbers at the same time, while the numbers at the input of the blocks of multipliers 5 and blocks of adders 6 are received in turn for each calculation step. The calculation of the quotient is carried out in 11 cycles to obtain a double precision result (the total capacity of the operands is 64, the mantissa is 53 bits), and the total division cycle is 15 cycles. The calculation of the square root of one number is also 11 cycles with a total duration of 24 cycles, while calculating the square root of two numbers simultaneously, the average calculation time is 12 cycles.

The unit for generating calculation results 7 normalizes the calculation result, packs the results into a floating point format in accordance with the IEEE 754 standard, and generates all the necessary flags.

Implementation examples

The claimed device for dividing and extracting the square root was used in the floating point coprocessor of the SPARC V8 processor, the results of comparison with similar devices [6] are presented in table 1.

Table 1 Division blocks Operation Extraction Advantage Advantage multiplication of various floating point coprocessors (FPUs) division, measures (double precision operation) square root (double precision operation) fission performance when extracting the square root GRFPU 16 (16) 23 (24) 6.66% 0/100% * ARM VFP9-S 28 (31) There is no data 86.66% - ARMVFP11 29 (33) There is no data 93.33% - AMD K7 17 (20) There is no data 13.33% - MEIKO fifty There is no data 233.33% - Claimed 15 (15) 24/12 (12) * Comparison object device

* - for group square root extraction

The claimed device was also used as an arithmetic unit in the system for calculating the position of the module based on micro drives, which allowed to increase the overall speed of the device, according to expert estimates, up to 2 times.

Thus, the use of the claimed device allows to provide a solution to the problem of dividing and extracting the square root with the achievement of an unexpected technical result.

Bibliography

1. A.S. USSR No. 842806. A device for calculating the square root / V.V. Chekushkin. - Publ. 1981. Bull. Number 24.

2. A.S. USSR No. 611208, class G 06 F7 / 38 1978 A device for calculating the square root.

3. A.S. USSR No. 656055, class G 06 F7 / 38 1979. A device for calculating the square root.

4. Safonova E.M., Shostak A.A. “DEVICE FOR DIVISION”, Patent No.2018933, class. G06F7 / 52, publication date 08/30/1994.

5. Safonova E.M., Shostak A.A. “DEVICE FOR DIVISION”, Patent No. 2018934, class. G06F7 / 52, publication date 08/30/1994.

6. Edvin Catovic “GRFPU - High Performance IEEE-754. Floating-Point Unit” Gaisler Research, Första Långgatan 19, SE-413 27 Göteborg, Sweden edvin @ gaisler. Com

Claims (1)

The square root division and extraction device contains a degree and mantissa extraction unit for input operands, the first input of which is an input to the device, a three-stage conveyor control unit of the input register block, the input of which is connected to the output of the degree and mantissa extraction unit of the input operands, the second output of the control circuit of the three-stage conveyor block input registers connected to the second input of the block allocation degree and mantissa of the input operands, the block of input registers connected to a three-stage con yer, the inputs / outputs of which are connected to the first, second and third inputs / outputs of the control circuit of the three-stage conveyor block of the input registers, respectively, the control circuit of the adder block and the multiplier block, the first input of which is connected to the first output of the control circuit of the three-stage conveyor of the block of input registers, the multiplier block the input of which is connected to the first output of the control circuit of the adder block and the multiplier block, and the output is connected to the second input of the control circuit of the adder block and the multiplier block, bl ok adders, the input of which is connected to the second output of the control circuit of the adder block and the multiplier block, and the output with the third input of the control circuit of the adder and multiplier blocks, the unit for generating the results of dividing and extracting the square root, the input of which is connected to the third output of the control circuit of the adder and multiplier multiplier, and the output is the output of the device.