RU2460130C1 - Method for digital recursive band-pass filtering and digital filter for realising said method - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: digital filtering method enables to pick up a signal in conditions with powerful broadband interference and can be realised in a digital filter. The method involves successive transformation of the filtered signal such that in each filtration step, fourth-order transformation is carried out, having transformation members only during even steps for signal sampled values. As a result of such signal transformation, the number of operations is reduced and operating speed is increased during filtration. The digital filter has a simple design and can be made using standard components.

EFFECT: higher speed of operation during band-pass filtering.

3 cl, 7 dwg

Description

The invention relates to computer technology and can be used in digital information processing systems with high requirements for frequency selectivity of filtering to select a useful signal in the presence of powerful broadband interference.

, путем определения разностного сигнала

, а выходной сигнал

формируют в виде суммы предыдущего значения

, и дополнительного сигнала Δ_i, причем дополнительный сигнал Δ_i выбирают равным значению Δ, если Δx_i≥Δ, значению (-Δ), если Δx_i≤Δ, и нулю, если -Δ<Δ_i<Δ, где Δ соответствует максимально допустимому превышению сигнала помехи над полезным сигналом [1] или цене единицы младшего разряда цифрового кода x_i [2].Known methods of digital recursive filtering of signals that allow you to select a useful signal in the presence of interference [1; 2]. These digital filtering methods are based on a comparison of the filtered digital signal x _i with the output signal

by determining the difference signal

, and the output signal

form as the sum of the previous value

, and an additional signal Δ _i , and the additional signal Δ _{i is} chosen equal to the value Δ if Δx _i ≥Δ, to the value (-Δ) if Δx _i ≤Δ, and to zero if -Δ <Δ _i <Δ, where Δ corresponds to the maximum allowable excess of the interference signal over the useful signal [1] or the unit price of the least significant digit of the digital code x _i [2].

The disadvantage of these methods is the inability to perform digital recursive bandpass filtering, since they use first-order signal transformations based on the formation of the first differences x _i -x _i-1 with delays of one sampling frequency period. Such a conversion provides smoothing of the filtered signal against the background of interference lying in the lower frequency region than the useful signal and does not solve the band-pass filtering problem, for which, in the simplest version, the conversion must be performed in accordance with the second-order difference control.

In the case where high selectivity of bandpass filtering is required to extract a useful signal from interference, a higher order transform is used.

Closest to the proposed is a digital filtering method that uses sequential (cascade) conversion of the filtered signal [3], taken as a prototype of the proposed method. The known method of digital recursive filtering includes r successive stages of conversion of the filtered signal, in each of which weighted summation of the delayed values of the input (x _n ) and output (y _n ) signals is performed so that the filtered signal of the i-th filtering stage (i = 0, 1 , ... r) is the input signal for the (i + 1) -th conversion step. The signal conversion of the i-th stage in the prototype method is performed according to the rule:

where x _ni , y _ni are the values of the input and output signals of the i-th stage of conversion;

β _ki , α _ki are the values of the weight coefficients of the i-th stage of the transformation.

Transformation (1) corresponds to the transfer function ([3], p. 52),

For a filter with the number of conversion steps equal to r, the transfer function of the filter:

The disadvantage of this method is the low speed when performing band-pass filtering due to the need to perform transformation of the form in each i-th link: β _1i x _{n-1, i} , α _1i y _{n-1, i} , and the longer the filtering time is , the higher the requirements for selectivity of bandpass filtering (the more the number of conversion steps r is required). So, for example, when performing band recursive filtering in a known manner with four conversion steps, in which each step performs signal conversion according to rule (1), the slope of the slopes of the amplitude-frequency characteristic (AFC) is only 40 decibels per octave ([3], p. .144, 145). This requires the execution of twenty operations of multiplying multi-digit numbers and sixteen operations of arithmetic addition, which is why the performance of the known filtering method is low.

Known software-controlled digital filter [4], which implements the known method of filtering. The filter contains a coefficient setting block, two memory blocks, an arithmetic block, two multiplexers, an adder, an output register, a control unit, a counting trigger, an inverter, AND and OR elements. The program-controlled digital filter is made in accordance with the cascade form of implementing digital recursive filters on second-order links. Each link of this filter converts the signal in accordance with the difference equation (1). The filter, depending on the weight coefficients loaded into its memory, can perform low-pass, high-pass and band-pass filtering.

The disadvantage of this filter is the large amount of necessary equipment for its implementation. In addition, when implementing bandpass filtering, the filter performance turns out to be low, since it uses sequential switching of the low and high frequencies, which leads to the need to perform more arithmetic operations.

Known recursive bandpass filter [5]. This filter contains two delay units, three adders and three multipliers. The filter operates in accordance with a second order difference equation. To perform band-pass filtering in this device, there is the possibility of mutually independent tuning of the filter according to the passband and resonant frequency by changing the values of its weight coefficients.

The disadvantage of such a filter is its low selectivity, limited by the selective capabilities of second-order filters, which for a band-pass filter does not exceed the steepness of the slopes of the frequency response of 10 decibels per octave (10 dB / oct).

Closest to the proposed digital recursive bandpass filter is a programmable digital filter [6], which is selected as a prototype device. This filter contains a register for storing the current value of the input signal, four multiplication units, four adders, two delay elements, two multiplexers, four code converters, a decoder, a transmission coefficient calculation unit, a filter status storage register, two inverters and a synchronization unit that provides filter operation control . The filter prototype before starting to perform filtering is configured for low-pass filtering, bandpass or notch filtering by selecting one of the four second-order equations.

The disadvantage of the filter prototype is the low selectivity when performing bandpass filtering. In addition, the prototype filter is difficult to implement and has a low speed.

The prototype filter [6] is the same as the known filters [4; 5], implements the known method of digital filtering [3].

The objective of the invention is to create a new method of recursive digital bandpass filtering and a digital filter to implement this method, which allows to increase the speed of performing bandpass filtering while ensuring high selectivity and ease of implementation.

The essence of the invention lies in the fact that a method is proposed comprising r successive stages of conversion of the filtered signal, in each of which weighted summation of the delayed values of the input (x _ni ) and output (y _ni ) signals is performed so that the filtered signal of the ith filtering stage ( i = 0, 1, ... r) is the input signal for the (i + 1) -th stage, characterized in that the signal conversion of the i-th stage is performed according to the rule:

moreover, pre-calculated filtering weights are selected based on the required values of the passband Δf and the central passband f _c , and the values of the sampling frequency are set four times the central frequency of the passband.

The values of the weighting filtration coefficients are calculated by the formulas:

K ₀ = (K ₁ + K ₂ +1) ² ,

In contrast to the known prototype method [3], the proposed method performs fourth-order conversion in each conversion step (3), and for the formation of the filtered signal of the i-th step, fewer arithmetic operations are required than in the prototype to perform the second-order conversion (in prototype - 5 multiplications and four arithmetic additions of multi-digit numbers, in the proposed method - three multiplications of multi-digit numbers, one multiplication by 2 and four arithmetic additions of multi-digit numbers).

As a result, one conversion step in the proposed method provides significantly greater selectivity and at the same time requires less time for performing computational operations. To achieve the same selectivity of the proposed method and the prototype method in the prototype method, it is required to use several times more number of conversion steps, which provides the proposed method with a significant gain in speed.

In the proposed method, the signal conversion (3) when performing filtering corresponds to the transfer function obtained by applying the z-transformation to (3). Given r successive stages of conversion, the transfer function is determined by the expression:

, представляется следующим выражением:Frequency response of a digital filter with such a transfer function, defined as H (f) = | H (Z) | at

is represented by the following expression:

- нормированная частота;Where

- normalized frequency;

f is the signal frequency;

f _D = 4f _C - sampling rate;

f _c is the center frequency of the passband;

To ₀ , K ₁ , K ₂ - the coefficients that determine the values of the passband and the center frequency of the passband, are calculated by the formulas (4).

Examples of frequency response calculated by the expressions (6) and (4) are shown in Fig.6 and Fig.7.

From consideration of the frequency response, it is seen that the proposed method allows for extremely high frequency selectivity of bandpass filtering. So two stages of conversion (Fig.6) provide the slope of the slopes of the frequency response of about 75 dB / oct. Already with four stages of conversion of the filtered signal (3) (Fig. 7) in the proposed method, the slope of the slopes of the frequency response is approximately 130 dB / oct, which exceeds the value of 100 dB / oct, which provides the required high degree of separation of the useful signal from interference.

As mentioned above, in the known prototype method, the four stages of conversion (1) provide, when band pass filtering, the slope of the slopes of the frequency response of 40 dB / oct, i.e. about 3.25 times lower selectivity with lower speed. To achieve a selectivity of 100 dB / oct in the prototype method, at least ten stages of conversion are necessary. In this case, the speed of the prototype method is approximately 5.2 times lower than the speed of the proposed method with the same selectivity.

As a result, the task is solved of creating a new method that allows to increase the speed of performing band pass filtering while ensuring high selectivity.

To implement the new method, a digital filter is proposed.

The technical problem solved by the proposed digital filter is to improve performance and simplify the filter when performing band-pass filtering.

The specified technical problem is achieved by the fact that a digital, recursive bandpass filter is proposed, containing three multiplication units, two adders, two registers, a multiplexer and a control unit, the first output of which is connected to the recording input of the first register, the information input of which is the filter input, the multiplexer output is connected with the first input of the first adder, and the output of the first multiplication unit is connected to the first input of the second adder, characterized in that two blocks of storage of sample signal values are introduced into it , a unit for multiplying by two, a third register, and a coefficient storage unit, the three outputs of which are connected to the first inputs of the first, second, and third multiplication units, the second inputs of which respectively correspond to the first output of the second unit for storing the sampled signal values, the output of the first adder, and the second output of the second block storage of sample values of the signal, the outputs of the second and third blocks of multiplication are connected to the second and third inputs of the second adder, the output of which is connected to the input of the second register, the output of which is connected the information input of the second block of storage of sample values of the signal, with the input of the third register and the first input of the multiplexer connected by the second input to the output of the first register, the control input to the second input of the control unit, and the output to the information input of the first block of storage of sample signal values, the first output which is connected through a multiplier by two to the second input of the first adder, the second output to the third input of the first adder, the control input to the control input of the second storage unit the sample values of the signal and the third input of the control unit, and the recording input is with the fourth output of the control unit, the input of which is the input for setting the filter number, and the fifth, sixth, seventh and eighth outputs of the control unit are connected respectively to the input of the coefficient storage unit, the recording input of the second register , the recording input of the second block for storing the sampled signal values and the recording input of the third register, the output of which is the output of the filter.

The invention consists in a new construction of a digital filter circuit, which allows for the implementation of any given number of sequentially switched fourth-order filtering stages by reusing a set of the same blocks, the composition of which and the connections between them are different from the prototype, while the filter uses a new inventive method band-pass filtering, which provides improved performance, and a reduced composition of blocks provides a simplified filter.

Figure 1 presents the structural diagram of a digital recursive bandpass filter, figure 2 is a structural diagram of a block for storing sampled signal values, Fig. 3 is a structural diagram of a block of shift registers, Fig. 4 is a structural diagram of a control unit, Fig. 5 - Timing diagrams of the digital filter.

Fig.6 and Fig.7 shows the frequency response of a digital filter consisting of two and four stages of conversion, respectively.

Figure 1 marked:

1, 12, 14 - registers;

2 - multiplexer;

3, 13 - blocks for storing sampled signal values;

4 - multiplier by 2;

5, 11 - adders;

6 - control unit;

7 - block storage coefficients;

8, 9, 10 - blocks of multiplication.

Figure 2 marked:

15 - demultiplexer;

16, 17, 18, 19 - blocks of shift registers;

20, 21 - multiplexers.

Figure 3 marked:

22 ₁ - 22 _е - shift registers.

In figure 4 are indicated:

23 - pulse generator;

24, 29, 34 - delay elements;

25 - frequency divider;

26, 30, 33 - registers;

27 - read-only memory (ROM);

28, 31 - counters;

32 - block subtraction;

35 - zero decoder.

Figure 5 marked:

a is a signal for recording the filter number in register 30;

b - write signal to register 1;

in - the recording signal in the block 3 of the storage of sample values of the signal;

g is the write signal to the register 12;

d is a recording signal in block 13 for storing sampled signal values;

e is a write signal to register 14;

g - control signal of multiplexer 2;

h, and is a two-bit (digital) control signal for blocks 3 and 13 for storing sampled signal values (h is the low-order signal, and is the high-order signal).

The digital recursive bandpass filter (Fig. 1) contains a register 1 for storing the current value of the input signal, the information input of which is the filter input, the recording input is connected to the first output of the control unit 6, and the output is connected to the first input of the multiplexer 2. The second input of the multiplexer 2 is connected to the output of the register 12, the inputs of the unit 13 for storing sampled signal values and the register 14, the control input of the multiplexer 2 is connected to the second output of the control unit 6. The output of the multiplexer 2 is connected to the first input of the adder 5 and the information input of the signal sample storage unit 3, the control input of which is combined with the control input of the signal sample value storage unit 13 and connected to the third output of the control unit 6, the fourth output of which is connected to the recording input of block 3 storing sampled signal values. The first output of block 3 for storing sampled signal values through two is connected to the second input of adder 5, the third input of which is connected to the second output of block 3, and the output is connected to the second input of block 9, connected by the first input to the second output of coefficient storage 7 , the first and third outputs of which are connected to the first inputs of the units 8 and 10 of multiplication, respectively, and the input is connected to the fifth output of the control unit 6. The second inputs of the blocks 8 and 10 of the multiplication are connected with the first and second outputs of the block 13 storing sample values of the signal. The outputs of the multipliers 8, 9, 10 are connected respectively to the first, second and third inputs of the adder 11, the output of which is connected to the information input of the register 12, connected by the recording input to the sixth output of the control unit 6. The input of the control unit 6 is the input of setting the filter number. The seventh and eighth outputs of the control unit 6 are connected respectively to the recording inputs of the unit 13 for storing the selected values of the signal and register 14, the output of which is the output of the filter.

In adder 5, the first and third inputs are summing, and the second input is subtracting.

In the adder 11, the first and third inputs are subtracting, and the second input is summing.

Blocks 3 and 13 storing sampled signal values have the same composition and structure (figure 2).

Block 3 (13) for storing sampled signal values contains a demultiplexer 15, the control input of which is combined with the control inputs of multiplexers 20, 21 and is the control input 2 of block 3 (13). The information input of the demultiplexer 15 is the input 3 of the recording unit 3 (13) storing sample values of the signal.

The four outputs of the demultiplexer 15 are connected respectively to the synchronization inputs 2 of the blocks 16, 17, 18, 19 of the shift registers, the information inputs 1 of which are combined and connected to the information input 1 of the block 3 (13) for storing the sample signal values.

The outputs 3 of the blocks 16, 17, 18, 19 of the shift registers are connected to the inputs of the multiplexer 20, the output of which is the output 4 of the block 3 (13) for storing sampled signal values. The outputs of 4 blocks 16, 17, 18, 19 of the shift registers are connected to the inputs of the multiplexer 21, the output of which is the output 5 of the block 3 (13) for storing sample signal values.

Each of the blocks 16, 17, 18, 19 of the shift registers contains e four-digit shift registers 22 (22 ₁ 22 _e ) (e is the bit depth of the binary numbers when performing filtering) (Fig.3). The information inputs of the shift registers 22 ₁ -22 _e form a multi-bit information input 1 of the block 16 (17, 18, 19) of the shift registers.

The combined synchronization inputs of the shift registers 22 ₁ -22 _e form the synchronization input 2 of the block 16 (17, 18, 19) of the shift registers. The outputs of the second bits of the registers 22 ₁ -22 _e form the multi-bit output 3 of the block 16. 17, 18, 19 the outputs of the fourth bits of the registers 22 ₁ -22 _e form the multi-bit output 4 of the block 16 (17, 18, 19).

In control unit 6 (Fig. 4), the output of the pulse generator 23 is connected to the input of the frequency divider 25. The output of the divider 25 is connected to the counting input of the counter 28 and is connected to the write input of the register 26 through the delay element 24. The output of the counter 28 is connected to the address input of the permanent memory device 27, whose output is connected to the input of the register 26. The MSB output of register 26 is connected to an input write register 30 and via the delay element 29 is connected to the input setting to zero of the counter register 28. The input 30 is an input of the digital filter number (N _f ) The outputs of the first m bits of the register 30 are connected to the input of the setting of the division ratio of the frequency divider 25 (the maximum division ratio is 2 ^m ). The outputs of the next two bits of the register 30 are connected to the input of the register 33. The outputs of the remaining bits of the register 30 form the fifth output of the control unit 6. The input of the register register 33 is connected to the output of the first bit of the register 26, which is the first output of the control unit 6. The output of the register 33 is connected to the first input of the subtracting unit 32, the second input of which is connected to the output of the counter 31, and the output through the zero decoder 35 and the delay element 34 is connected to the zero setting input of the counter 31. The counting input of the counter 31 is connected to the output of the fifth digit of the register 26, which is the fourth output of the control unit. The output of the second bit of the register 26 is the second output of the control unit 6. The outputs of the third and fourth bits of the register 26 form the third two-bit output of the control unit 6. The outputs of the sixth, seventh and eighth bits of the register 26 are respectively the sixth, seventh and eighth outputs of the control unit 6.

The digital filter implements the proposed method of digital filtering. The filter is made in accordance with a cascade implementation. Each conversion step in the filter works according to the rule defined by the fourth-order difference equation (3).

In the digital filter, it is possible to set the required bandwidth, central bandwidth and slope of the frequency response by storing in block 7 a set of coefficients for various filters and selecting a filter number before starting filtering. In accordance with expression (6), in order to obtain the required frequency response, sets of coefficients calculated by formulas (4) and the parameter r must be specified. The calculated sets of coefficients for different values of the passband and the center frequency of the passband are stored in the coefficient storage unit 7. Since for any number of conversion steps to obtain a filter with any specific value of the passband and the center frequency of the passband, only three coefficients are required, when using modern memory elements that run the coefficient storage unit 7, it can store the required number of sets of coefficients for implementation of almost any requirements for the restructuring of the filter.

Information about the required characteristics of the filter is contained in the information word "filter number" (N _f ) received at the input of control unit 6. In the information word N _f contains the following data.

1) A binary number that determines how many times the filter sampling frequency is less than the maximum possible (first m bits of the information word). This allows you to set the desired filter sampling rate.

2) A binary number that defines the number of conversion steps r performed by the filter (bits m + 1, m + 2 in the information word; in practice, r≤4, which ensures the implementation of filters up to 16 orders of magnitude inclusive). This allows you to set the desired high slope of the slopes of the frequency response of the filter.

3) A binary number that defines the number of a set of filter coefficients (high order bits in an information word). This allows you to set the desired value of the passband and center frequency of the passband of the filter.

The operation of the digital filter consists of several cycles. The number of filter operation cycles is determined by the value of the parameter r, which determines the slope of the slopes of the frequency response. 5, a timing diagram explaining a filtering sequence is shown for r = 4. The signals shown in FIG. 5 are generated by the control unit 6.

The principle of generating control signals is as follows.

The pulses generated by the pulse generator 23 are supplied through the frequency divider 25 to the counter 28. The number at the output of the counter 28 is the address of the permanent memory device 27. The number of bits of the permanent memory device 27 is equal to the number of generated control signals, and the number of cells is determined by the minimum interval between the generated pulses. In the cells of the permanent storage device, the signals of a logical unit are recorded in those bits for which the corresponding value of the control signal takes a high level. In the remaining bits of the cells, logical zero signals are recorded. The contents of the cells of the permanent storage device 27 are sequentially recorded in the register 26 by a signal from the frequency divider 25, delayed by the delay element 24. After recording the contents of the last cell in the register 26 at the output of its last digit, a signal of a logical unit appears, which, through the delay element 29, sets the counter 28 to its initial state, after which the process of generating control signals is repeated.

In the first cycle of operation, the information word "filter number" N _f received at the input of the control unit is recorded in register 30 by a write signal (signal a in Fig. 5). In this case, the division factor of the frequency divider 25 is set, which determines the value of the sampling frequency during the filter operation, the parameter r, which determines the slope of the ramps, and the number that determines the filter number. At the output 5 of the control unit 6, a number is set that determines the number of the coefficient set, which is the address of the coefficient storage unit 7. The filter is ready to receive an input signal. The next value of the input signal is written to register 1 by the signal from the first output of the control unit 6 (signal 6 in FIG. 5). The same signal is used to record the parameter r in the register 33 of the control unit 6. At the output of the subtraction block 32, a difference is formed between the number recorded in the counter 31 and the register 33. The value of this difference in the filter automatically determines whether or not this cycle of operation is the last in this sampling period. The last filter cycle is if the difference is zero. The value of the filtered signal from register 1 enters through the multiplexer 2, open in this direction (see signal W in Fig. 5, generated at the second output of the control unit 6), to the unit 3 for storing sample signal values.

The demultiplexer 15 of the block 3 for storing sampled signal values is connected in such a way (see signals h, and in Fig. 5, the control of the demultiplexer 15 and multiplexers 20, 21 generated at the third output of the control unit 6), that the recording signal is from the fourth output of the control unit 6 ( the signal in figure 5) is input to the recording block 16 of the shift registers. The received value is shifted bitwise in the shift registers 22 of the block 16 of the shift registers. The present (x _{n, 1} ) and previous values, delayed by two (x _{n-2, 1} ) and four periods of the sampling frequency (x _{n-4, 1} ), are stored respectively in register 1 and shift registers 22 of block 16 of the shift registers of the block 3, they enter directly and through multiplexers 20 and 21 to the first input of adder 5, the input of the multiplier by two 4 and the third input of adder 5. Since the first and third inputs of adder 5 are summing, and the second input is subtracting, the value of the output of adder 5 is formed non-recursive part of difference equation (3) for the first stage of pre formations x _{n, 1} -2x _{n-2, 1} + x _{n-4, 1} . The multiplication units 8 and 10 perform the multiplication of the previous values delayed by two (y _{n-2, 1} ) and four (y _{n-4, 1} ) periods of the sampling frequency stored in the block 13 for storing sample signal values by the coefficients K ₁ and K _2, respectively, stored in the coefficient storage unit 7. Block 9 multiplication performs the multiplication of the number coming from the adder 5 by the coefficient K ₀ stored in block 7 storing the coefficients. After summing the numbers coming from the outputs of the multiplication blocks 8, 9, 10, the output of the adder 11 turns out to be the result of filtering the first stage of the transformation (y _n1 ). The generated value y _{n1 is} recorded in the register 12 by a write signal from the sixth output of the control unit 6 (signal r in FIG. 5). The value of y _{n1 is} pushed into the block 16 of the shift registers of the block 13 storing sample values of the signal for use in the next period of the sampling frequency. The control and recording signals to the demultiplexer 15 of block 13 are received respectively from the third and seventh outputs of the control block 6. This completes the first filter cycle.

In subsequent cycles, the filter of a given sampling period operates in a similar manner. In this case, the multiplexer 2 is switched by a signal coming from the second output of the control unit 6 to a state in which the information input of the unit 3 for storing the sampled signal values is connected to the output of the register 12 (signal w in Fig. 5), and the control signal coming from the third output control unit 6 changes when moving to the next cycle, taking values 10, 01, 11 (signals h, and in FIG. 5). As a result of such switching of the control signals of the multiplexer 2 and the storage units 3 and 13 of the sample signal values, the signal values filtered at the first cycle of the filter operation are recorded:

- on the second cycle into blocks of 17 shift registers;

- on the third cycle in blocks of 18 shift registers;

- on the fourth cycle in blocks of 19 shift registers.

When switching from cycle to cycle in the counter 31 of the control unit 6, a unit is added by the signal from the fifth output of the register 26. In the last cycle, the number in the counter 31 becomes equal to r. At the output of the difference block 32, a number is formed equal to zero, meaning that this cycle is the last. A signal is generated at the output of the zero decoder 35, which sets the counter 31 to the zero state through the delay element 34.

At the end of the fourth cycle, the filtered signal from register 12 is recorded by the signal from the eighth output of the control unit 6 (signal e in FIG. 5) into register 14, the output of which is the output of a digital filter.

In subsequent periods of the sampling frequency, the filter operates in a similar manner.

Compared with the known technical solutions, the proposed method and a digital filter for implementing this method provide improved performance and simplified filter when performing band-pass filtering.

The improvement of these technical characteristics is achieved by the following new solutions incorporated into the invention.

1. When filtering is performed, each stage of the signal conversion is performed in accordance with a fourth-order difference equation containing terms only with even powers for sample signal values. As a result, the number of multiplication and addition operations is reduced by about half. This provides increased performance and reduced number of multiplication blocks.

2. Weights K ₀ , K ₁ , K ₂ , for specific values of the passband and the center frequency of the passband are the same in all stages of filtering. This simplifies filtering, reduces the amount of memory for storing coefficients, and allows you to store the required number of sets of coefficients, providing the implementation of a large number of bandwidth options and center frequencies of bandwidths.

3. Ensured the implementation of almost any given number of sequentially connected filtering stages by reusing a set of the same blocks, which allows for high selectivity without complicating the filter.

The proposed set of features in the solutions considered by the author was not found to solve the problem and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step".

A digital filter for implementing the proposed method is performed on a standard elemental base for computer technology, mass-produced by the domestic industry.

Sources used

1. Patent for the invention of the Russian Federation No. 2188499, class. H03H 17/02, 04/07/2000.

2. Patent for the invention of the Russian Federation No. 2187883, class. H03H 17/02, 06/19/2000.

3. L.M. Goldenberg, B.D. Matyushkin, M.N. Polyak. Digital signal processing. Directory. M .: Radio and communications, 1985, p. 52, 94, 144, 145 - a prototype of the method.

4. Copyright certificate of the USSR No. 1338006, cl. H03H 17/04, 07/22/1985.

5. Copyright certificate of the USSR No. 1224980, cl. H03H 17/04, 12/13/1984.

6. Patent for the invention of the Russian Federation No. 2057364, class. G06F 17/14, 11/25/1992 - a prototype device.

Claims (3)

1. A method of digital recursive bandpass filtering, comprising r successive stages of conversion of the filtered signal, in each of which weighted summation of the delayed values of the input (x _ni ) and output (y _ni ) signals is performed so that the filtered signal of the ith filtering stage (i = 0, 1, ... r) is the input signal for the (i + 1) -th stage, characterized in that the signal conversion of the i-th stage is formed according to the rule
y _ni = K ₀ (x _ni -2x _{n-2, i} + x _{n-4, i} ) -K ₁ y _{n-2, i} -K ₂ y _{n-4, i} ,
moreover, the pre-calculated filtering weights are selected based on the required values of the passband Δf and the central passband f _c , and the values of the sampling frequency are set four times the central frequency of the passband. 2. The method according to claim 1, characterized in that the filtration weights are calculated by the formulas:

K ₀ = (K ₁ + K ₂ +1) ² . 3. A digital recursive bandpass filter containing three multiplication units, two adders, two registers, a multiplexer and a control unit, the first output of which is connected to the recording input of the first register, the information input of which is a filter input, the multiplexer output is connected to the first input of the first adder, and the output of the first multiplication block is connected to the first input of the second adder, characterized in that two blocks of storage of sampled signal values, a block of multiplication by two, a third register and a coefficient storage block are introduced into it entents, the three outputs of which are connected to the first inputs of the first, second and third multiplication units, the second inputs of which are connected respectively to the first output of the second block of storing the sampled signal values, the output of the first adder and the second output of the second block of storing sampled signal values, the outputs of the second and third blocks multiplications are connected to the second and third inputs of the second adder, the output of which is connected to the input of the second register, the output of which is connected to the information input of the second storage unit the initial values of the signal, with the input of the third register and the first input of the multiplexer connected by the second input to the output of the first register, the control input to the second output of the control unit, and the output to the information input of the first block for storing sample values of the signal, the first output of which is through the multiplication unit by two is connected to the second input of the first adder, the second output to the third input of the first adder, the control input to the control input of the second block for storing the selected signal values and the third input of the block board, and the recording input - with the fourth output of the control unit, the input of which is the input of setting the filter number, and the fifth, sixth, seventh and eighth outputs of the control unit are connected respectively to the input of the coefficient storage unit, the recording input of the second register, the recording input of the second selective storage unit signal values and the input of the third-register entry, the output of which is the filter output.

Images