RU2458431C2 - Module of semiconductor element and method of its manufacturing - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: in a module of a semiconductor element, at least, one semiconductor element is placed between the first insulating pad, having a high specific heat conductivity, and the second insulating pad, comprising high specific heat conductivity, and the external peripheral part between the first insulating substrate and the second insulating substrate is sealed with the help of a sealing element, at the same time the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by adhesion of the first insulating substrate with the help of a sealing element with the help of binding at ambient temperature, in order to adhere the first surface of interconnections with the first through interconnections, and adhesion of the semiconductor element electrode surfaces with the first surface of interconnections and the second surface of interconnections with the help of adhesion at room temperature.

EFFECT: result of invention consists in providing a semiconductor element module with high reliability, an electric connection and a thermal connection, and providing for sufficient cooling efficiency, offering a method for its manufacturing.

12 cl, 9 dwg

Description

FIELD OF THE INVENTION

The invention relates to a module of a semiconductor element and a method for its manufacture and is suitable for a semiconductor element having a high output power, such as, for example, a power transistor.

State of the art

Power semiconductor elements that have significant power output but generate large amounts of heat, such as insulated gate bipolar transistors (hereinafter referred to as IGBTs), must be cooled in order to ensure reliability and service life for their functions. In recent years, the use of such power semiconductor elements has been expanded since they are used in the control of electric motors of electric cars, etc. Therefore, in addition to increasing the output power, an increase in reliability, an increase in the service life, etc. are required.

Patent Document 1. Publication of Patent Application (Japan) No. Hei 6-188363.

Patent document 2. Brochure for the publication of the international patent application number 98/43301.

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

A modular structure of a power semiconductor element is provided, for example, in which the element is mounted directly or indirectly on a substrate made of metal that has excellent thermal radiation, and wire connections to external contact terminals are formed separately from each other by wire bonding (Patent Document 1). Since this structure is open on the side of the upper surface of the element, the structure has the problem of being unable to achieve sufficient cooling efficiency. In addition, the method of forming wire connections with external contact pins separately from each other by wire bonding requires complex and difficult processes, as well as a large number of processes. Therefore, there is also the problem of high production costs.

Meanwhile, there is also a modular structure in which substrates made of a metal that has excellent thermal radiation are placed on top and bottom of the power semiconductor element, allowing heat to be released from the upper and lower surfaces of the element (Patent Document 2). In this structure, however, the electrical connection is not established by bonding, but by bringing the metal substrates into pressure contact with the element in order to weaken the loads caused by heat generation. Therefore, the electrical connection of the metal substrates with the element is insufficient, which makes it difficult to apply a modular structure to elements with high output power. In addition, the thermal connection of metal substrates with the element is also insufficient (the condition for the specific thermal conductivity between the various elements interconnected is defined in this document as a thermal connection). Accordingly, there is a problem of inability to achieve the expected thermal radiation efficiency.

Additionally, in the above modular structures, the limit of improvement of the entire module is determined by the limits of solder and wires for interconnects, polymer for sealing, etc. in terms of their heat resistance, thermal cyclic resistance and vibration resistance. Given the inability to meet the heat resistance, thermal cyclic resistance and vibration resistance required for electric cars and the like, these modular structures do not allow sufficient reliability. For example, an element in a module may be operational, but interconnects may be damaged, impairing the functions of the module as a whole and thereby reducing the reliability and life of the module.

Additionally, there is a problem for the above modular structures and the like. in achieving both thermal radiation efficiency and reliability regarding binding between the substrate (s) and the element and / or between the substrate and the thermal radiation rib. For example, the use of a binding agent for binding can lead to the problem of a certain degree of low thermal conductivity and an increase in the number of processes. The use of diffuse bonding or anodic bonding for bonding can lead to such problems that the types of materials are limited for bonding purposes and that since heating is involved in bonding, a certain amount of time is required for cooling, and the module is also affected by heat (generates thermal stress).

The present invention has been made in the light of the above problems and is intended to provide a semiconductor cell module having high reliability, excellent electrical connection and thermal connection and providing sufficient cooling efficiency, and also provide a method for manufacturing the module.

Problem Solver

A semiconductor element module according to the first invention for solving problems is a semiconductor element module in which at least one semiconductor element is interposed between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while the semiconductor element includes a plurality of surfaces of the electrodes formed on a part of the surface of the semiconductor element on one side, the first insulating substrate includes a plurality of first interconnect surfaces formed on the surface of the first insulating substrate on one side so as to correspond to each of the electrode surfaces of the semiconductor element, and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the surface of the semiconductor element on about the bottom side with the first insulating substrate by bonding at room temperature so that the electrode surfaces of the semiconductor element are set so as to be opposite the first surfaces of the interconnects, and bonding the surface of the semiconductor element on the other side with the second insulating substrate by bonding at room temperature.

The semiconductor cell module according to the second invention for solving problems is a semiconductor cell module in which at least one semiconductor cell is interposed between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while the semiconductor element includes a plurality of surfaces of electrodes formed on part of the surfaces of the semiconductor element on both sides, the first insulating substrate includes a first interconnect surface formed on the surface of the first insulating substrate on one side so as to correspond to the surfaces of the electrodes of the semiconductor element on one side, the second insulating substrate includes a second interconnect surface formed on the surface of the second insulating substrate on one side so that s correspond to the electrode surfaces of the semiconductor element on the other side, and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the surface of the semiconductor element on one side to the first insulating substrate by bonding at room temperature such that the electrode surfaces of the semiconductor element are on one side are mounted so as to be opposite the first surface of the interconnects, and the bonding I the surface of the semiconductor element on the other side with the second insulating substrate by bonding at room temperature so that the electrode surfaces of the semiconductor element on the other side are set so as to be opposite the second surface of the interconnects.

The module of the semiconductor element according to the third invention for solving problems is a module of the semiconductor element in which at least one semiconductor element is placed between the first insulating substrate having high thermal conductivity and the second insulating substrate having high thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while the semiconductor element includes a plurality of of the electrodes formed on the entire surface of the semiconductor element on one side, the first insulating substrate includes a plurality of first interconnect surfaces formed on the surface of the first insulating substrate on one side so as to correspond to each of the electrode surfaces of the semiconductor element, and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the surfaces of the semiconductor electrodes lementa with the first wiring surfaces by means of binding at room temperature, and the bonding surface of the semiconductor element on the other side to the second insulating substrate by means of bonding at room temperature.

The semiconductor element module according to the fourth invention for solving problems is a semiconductor element module in which at least one semiconductor element is interposed between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while the semiconductor element includes many of the electrodes formed on all surfaces of the semiconductor element on both sides, the first insulating substrate includes a first interconnect surface formed on the surface of the first insulating substrate on one side so as to correspond to the surfaces of the electrodes of the semiconductor element on one side, the second insulating substrate includes a second interconnect surface formed on the surface of the second insulating substrate on one side so that They correspond to the electrode surfaces of the semiconductor element on the other side, and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element on the one side to the first interconnect surface by bonding at room temperature and bonding the electrode surfaces of the semiconductor element on the other side with a second interconnect surface by binding at room temperature Terature.

The semiconductor cell module according to the fifth invention for solving problems is the semiconductor cell module according to any of the first to fourth inventions, in which at least one of the first insulating substrate and the second insulating substrate includes wired interconnects that are connected to the corresponding one from the first surface of the interconnects and the second surface of the interconnects and which are interconnected with the external environment, and the wired interconnects are formed so as to penetrate at least through one of the first insulating substrate and the second insulating substrate in the direction of its thickness.

A semiconductor cell module according to the sixth invention for solving problems is a semiconductor cell module according to any one of the first to fourth inventions, wherein at least one of the first insulating substrate and the second insulating substrate includes wired interconnects that are connected to the corresponding one from the first surface of the interconnects and the second surface of the interconnects and which are interconnected with the external environment, and the wired interconnects are any of the following A: wiring, which are formed so as to move away from the surface of any of the first insulating substrate and the second insulating substrate in the lateral direction and also to penetrate through the outer peripheral portion between the first insulating substrate and the second insulating substrate in a lateral direction; and wire connections that are formed in a groove formed so as to extend laterally from the surface of any of the first insulating substrate and the second insulating substrate, and also penetrate at least one of the first insulating substrate and the second insulating substrate in the side direction.

The semiconductor cell module according to the seventh invention for solving problems is the semiconductor cell module according to any one of the first to sixth inventions, in which at least one of the electrode surfaces, the first interconnect surface and the second interconnect surface is formed so as to have a flat surface.

A semiconductor cell module according to the eighth invention for solving problems is a semiconductor cell module according to any of the first to seventh inventions, in which at least one of the surfaces of the electrodes, the first surface of the interconnects and the second surface of the interconnects is made of metal.

The semiconductor cell module according to the ninth invention for solving problems is a semiconductor cell module in which at least one semiconductor cell is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second insulating substrate is sealed with a sealing element, while the semiconductor element The ent includes metal and flat surfaces of the electrodes formed on all or almost all surfaces of the semiconductor element on both sides, the first insulating substrate includes a metal and flat first interconnect surface formed on the surface of the first insulating substrate on one side so that correspond to the surfaces of the electrodes of the semiconductor element on one side, the sealing element includes a metal first through the joints connected to the first surface of the interconnects and provided so as to penetrate the sealing element, the second insulating substrate includes a metal and flat second surface of the interconnects formed on the surface of the second insulating substrate on one side so as to correspond to the surfaces of the electrodes of the semiconductor element on the other side, metal second through wiring connected to the second surface of the wiring and provided so that would penetrate the second insulating substrate, and metal third through interconnects connected to the first through interconnects and provided so as to penetrate the second insulating substrate, and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the first insulating substrate using a sealing element by bonding at room temperature to thereby bind the first surface of the interconnects to the first through interconnects, and bonding the electrode surfaces of the semiconductor element to the first interconnect surface and the second interconnect surface by bonding at room temperature.

A semiconductor cell module according to the tenth invention for solving problems is a semiconductor cell module according to any of the third to ninth inventions, wherein a plurality of deformable and thin column electrodes are provided on surfaces of either the first and second interconnect surfaces, or the electrode surfaces of the semiconductor element, or those and others, and at least one of the first surface of the interconnects and the second surface of the interconnects associated with the surfaces of the ele ctrodes of a semiconductor element with a plurality of columnar electrodes between them by binding at room temperature.

The semiconductor cell module according to the eleventh invention for solving problems is the semiconductor cell module according to the tenth invention, in which the shoulders on the edges of the column bonding portions are rounded, and the shoulders are either on the sides closer to the first and second surfaces of the interconnects, or on the sides closer to the surfaces of the electrodes semiconductor element, either on both sides.

A semiconductor cell module according to the twelfth invention for solving problems is a semiconductor cell module according to any of the fifth to eleventh inventions, in which cooling means for cooling the semiconductor cell module is provided for an outer surface of at least one of the first insulating substrate and the second insulating substrate by bonding at room temperature, if both the first insulating substrate and the second insulating substrate are either I insulating substrate or the second insulating substrate has no wiring penetrating therethrough in the thickness direction.

A method for manufacturing a semiconductor cell module according to a thirteenth invention for solving problems is a method for manufacturing a semiconductor cell module in which at least one semiconductor cell is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high high thermal conductivity thermal conductivity and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, the method comprises: forming a plurality of electrode surfaces on a part of the surface of the semiconductor element on one side, forming a plurality of first interconnect surfaces on the surface of the first insulating substrate on one side so that the first interconnecting surfaces correspond to each of the electrode surfaces of the semiconductor element, and mounting the semiconductor element on the first insulating the substrate and the second insulating substrate by bonding the surface of the semiconductor element on one side to the first insulating substrate by means of bonding at room temperature so that the surface of the semiconductor element electrodes are set so as to be located opposite the first wiring surfaces, and bonding a surface of the semiconductor element on the other side to the second insulating substrate by bonding at room temperature.

A method for manufacturing a semiconductor cell module according to the fourteenth invention for solving problems is a method for manufacturing a semiconductor cell module in which at least one semiconductor cell is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while b comprises: forming a plurality of electrode surfaces on part of surfaces of the semiconductor element on both sides; forming a first interconnect surface on the surface of the first insulating substrate on one side such that the first interconnect surface corresponds to the electrode surfaces of the semiconductor element on one side; forming a second interconnect surface on the surface of the second insulating substrate on one side such that the second interconnect surface corresponds to the electrode surfaces of the semiconductor element on the other side; and the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the surface of the semiconductor element on one side to the first insulating substrate by bonding at room temperature so that the electrode surfaces of the semiconductor element on one side are defined so as to be opposite the first surface of the interconnects and bonding the surface of the semiconductor element on the other side with the second insulating substrate binding dstvom at room temperature so that the surface of the semiconductor element on the other side electrodes are set so as to be positioned opposite the second surface of the interconnect.

A method for manufacturing a semiconductor cell module according to the fifteenth invention for solving problems is a method for manufacturing a semiconductor cell module in which at least one semiconductor cell is interposed between a first insulating substrate having high thermal conductivity and a second insulating substrate having high high thermal conductivity thermal conductivity and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, the method contains: the formation of many surfaces of the electrodes over the entire surface of the semiconductor element on one side; forming a plurality of first interconnect surfaces on the surface of the first insulating substrate on one side such that the first interconnect surfaces correspond to each of the electrode surfaces of the semiconductor element on one side; and mounting the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element to the first interconnect surfaces by bonding at room temperature and bonding the surface of the semiconductor element on the other side with the second insulating substrate by bonding at room temperature.

A method for manufacturing a semiconductor element module according to a sixteenth invention for solving problems is a method for manufacturing a semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed, while It comprises: forming a plurality of electrode surfaces over all surfaces of the semiconductor element on both sides; forming a first interconnect surface on the surface of the first insulating substrate on one side such that the first interconnect surface corresponds to the electrode surfaces of the semiconductor element on one side; forming a second interconnect surface on the surface of the second insulating substrate on one side such that the second interconnect surface corresponds to the electrode surfaces of the semiconductor element on the other side; and mounting the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element on one side to the first interconnect surface by bonding at room temperature and bonding the electrode surfaces of the semiconductor element on the other side to the second interconnect surface by bonding at room temperature.

A method for manufacturing a semiconductor element module according to the seventeenth invention for solving problems is a semiconductor element module according to any of the thirteenth to sixteenth inventions, in which wire interconnects are formed in at least one of the first insulating substrate and the second insulating substrate so that connect to the corresponding one of the first surface of the interconnects and the second surface of the interconnects and penetrate at least one of the first isolates the substrate and the second insulating substrate in the direction of its thickness so that the wired interconnects are connected to the external environment.

A method for manufacturing a semiconductor element module according to the eighteenth invention for solving problems is a semiconductor element module according to any of the thirteenth to sixteenth inventions, in which wire interconnects that connect to any of the first surface of the interconnects and the second surface of the interconnects and which are connectable to the external environment are formed by the following: the formation of interconnects so that the interconnects protrude from the surface of any first insulating substrate and the second insulating substrate in the lateral direction, and penetrate through an outer peripheral portion between the first insulating substrate and the second insulating substrate in a lateral direction; or forming a groove and interconnects in a groove such that the groove and interconnects extend laterally from the surface of any of the first insulating substrate and the second insulating substrate and penetrate at least one of the first insulating substrate and the second insulating substrate in the lateral direction.

A method for manufacturing a semiconductor cell module according to the nineteenth invention for solving problems is a semiconductor cell module according to any of the thirteenth to eighteenth inventions, in which at least one of the surfaces of the electrodes, the first surface of the interconnects and the second surface of the interconnects is formed to have flat surface.

A method for manufacturing a semiconductor cell module according to the twentieth invention for solving problems is a semiconductor cell module according to any of the thirteenth to nineteenth inventions, in which at least one of the surfaces of the electrodes, the first surface of the interconnects and the second surface of the interconnects is made of metal.

A method for manufacturing a semiconductor cell module according to the twenty-first invention for solving problems is a method for manufacturing a semiconductor cell module in which at least one semiconductor cell is interposed between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate is sealed with metiziruyuschego element, the method comprising: forming metallic and planar electrode surfaces in all or almost all the surfaces of the semiconductor element on both sides; forming a metallic and flat first surface of the interconnects on the surface of the first insulating substrate on one side such that the first surface of the interconnects corresponds to the electrode surfaces of the semiconductor element on one side; the formation of the metal first end-to-end interconnects penetrating through the sealing element and connected to the first surface of the interconnects; forming a metallic and flat second interconnect surface on the surface of the second insulating substrate on one side such that the second interconnect surface corresponds to the electrode surfaces of the semiconductor element on the other side; the formation of metallic second through interconnects penetrating through the second insulating substrate and connected to the second surface of the interconnects; the formation of metallic third through interconnects penetrating through the second insulating substrate and connected to the first through interconnects; and mounting the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the first insulating substrate with the sealing element by bonding at room temperature, thereby thereby bonding the first surface of the interconnects to the first through interconnects, and bonding the surfaces of the electrodes of the semiconductor element to the first surface of the interconnects and a second interconnect surface by binding at room temperature.

A method for manufacturing a semiconductor cell module according to the twenty-second invention for solving problems is a semiconductor cell module according to any of the fifteenth to twenty-first inventions, in which a plurality of deformable and thin column electrodes are formed on surfaces from either the first and second surfaces of the interconnects, or the surfaces of the electrodes a semiconductor element, or both, and others, and at least one of the first surface of the interconnects and the second surface of the inter Connections binds to the electrode surfaces of the semiconductor element with a plurality of columnar electrodes therebetween by linking at room temperature.

A method for manufacturing a semiconductor cell module according to the twenty-third invention for solving problems is a semiconductor cell module according to the twenty-second invention, in which the shoulders are rounded at the edges of the column-bonding parts of the column electrodes, and the shoulders are either on the sides closer to the first and second surfaces of the interconnects, or the sides are closer to the electrode surfaces of the semiconductor element, or on both sides.

A method for manufacturing a semiconductor cell module according to the twenty-fourth invention for solving problems is a semiconductor cell module according to any one of the inventions seventeenth to twenty-third, in which cooling means for cooling the semiconductor cell module is coupled to an outer surface of at least one of the first insulating the substrate and the second insulating substrate by binding at room temperature, in the case where both the first insulating substrate and the second I insulating substrate or either the first insulating substrate or the second insulating substrate has no wiring penetrating therethrough in the thickness direction.

Advantage of the invention

According to the present invention, electrode surfaces are formed on the surface (s) of the semiconductor element, and also interconnect surfaces are formed on ceramic substrates having high thermal conductivity. Then, the semiconductor element binds to the substrates by binding at room temperature. This allows you to get a module of a semiconductor element having a structure in which an electrical connection is provided and the efficiency of thermal radiation is high. In addition, since the bonding is carried out by bonding at room temperature, the bond strength between the bonding elements becomes equivalent to the bonding strength of dry materials, so that high rigidity is achieved. In addition, binding at room temperature does not require heating in the manufacturing steps, so that thermal stress is not generated. Therefore, the resistance to thermal cyclic effects and vibration resistance are increased, which allows to increase the wear resistance and reliability of the module of the semiconductor element. Additionally, with this structure, the process of forming interconnects, as well as the installation process are simplified, reducing the number of required components. This makes it possible to significantly reduce production costs for manufacturing processes.

Brief Description of the Drawings

FIG. 1 shows a cross-sectional diagram illustrating an exemplary embodiment (embodiment 1) of a semiconductor element module according to the present invention.

FIG. 2 shows cross-sectional diagrams illustrating another exemplary embodiment (embodiment 2) of a semiconductor element module according to the present invention.

FIG. 3 shows cross-sectional diagrams illustrating modifications to the module of the semiconductor element illustrated in Embodiment 2.

FIG. 4 shows a configuration diagram illustrating another exemplary embodiment (embodiment 3) of a semiconductor cell module according to the present invention.

FIG. 5 shows a diagram for explaining the structure of a method for manufacturing modules of semiconductor elements shown in embodiments 1 and 2.

FIG. 6 shows diagrams for explaining the details of a method for manufacturing modules of semiconductor elements shown in embodiments 1 and 2.

FIG. 7 shows diagrams for explaining the details of a method for manufacturing modules of semiconductor elements shown in embodiments 1 and 2.

FIG. 8 shows diagrams for explaining the details of a method for manufacturing modules of semiconductor elements shown in embodiments 1 and 2.

FIG. 9 shows diagrams illustrating some examples of electrode surface layouts of each semiconductor element used in the semiconductor element module of the present invention.

Explanation of Numbered Links

1, 21 - module of the semiconductor element

2 - IGBT (semiconductor element)

2c, 2e, 2g - electrode surface

3 - diode (semiconductor element)

3c, 3e - electrode surface

4, 5, 6 - interconnect layer

7, 8 - ceramic substrate

9, 10, 12 - end-to-end interconnects

11 - sealing element

13 - polymer

22, 23, 24, 31 - interconnect layer

41 - rib for thermal radiation

The optimal mode of carrying out the invention

The following describes the module of the semiconductor element according to the present invention and the method for its manufacture with reference to FIG. 1-8.

First Embodiment

FIG. 1 shows a block diagram illustrating an example embodiment of a semiconductor cell module according to the present invention.

It should be noted that the semiconductor element module 1 of this embodiment is configured to include IGBT 2 and the diode 3 as semiconductor elements, but may be configured to include at least one semiconductor element. The semiconductor 1 is particularly suitable for a semiconductor element that has a large amount of heat generation.

As shown in FIG. 1, the semiconductor element module 1 of this embodiment includes IGBT 2, a diode 3, a plate-like flat ceramic substrate 7 (a second insulating substrate), a plate-shaped flat ceramic substrate 8 (a first insulating substrate), and a sealing element 11. IGBT 2 and a diode 3 have flat electrode surfaces formed on both of their surfaces. The ceramic substrate 7 has a high thermal conductivity and has flat layers 4 and 5 of the interconnect circuit (second interconnect surface) formed on its surface on one side. Layers 4 and 5 of the interconnect circuit must communicate with the surfaces of the IGBT 2 electrodes and diode 3 on one side. The ceramic substrate 8 has a high thermal conductivity and has a flat layer 6 of the interconnect circuit (the first interconnect surface) formed on its surface on one side. The interconnect layer 6 is connected to the surfaces of the IGBT 2 electrodes and the diode 3 on the other side. The sealing element 11 is placed between the outer edge parts of the ceramic substrates 7 and 8, thereby thereby sealing the inner part. The semiconductor element module 1 is formed by directly bonding the interfaces of these elements through bonding at room temperature.

It should be noted that bonding at room temperature (also called surface-activated bonding at room temperature) is a bonding method using a phenomenon in which strong chemical bonding is achieved even at room temperature by the following: performing radiation of ion beams, etc. in vacuum so that inactive surface layers having a weak reactivity, such as oxides and impurities on the surfaces of the material, can be removed, i.e. ensuring the visibility of atomic planes, which are clean and have significant reactive activity, from the surfaces of the material; and then by pressure welding the atomic planes of the surfaces of the material with each other. By bonding at room temperature, a bond strength equivalent to that of dry materials can be achieved without the need for any binder. Binding at room temperature also leads to such an advantage that thermal stress does not remain in the materials bonded to each other. It should be noted that in the case of direct bonding technology, such as anodic bonding or diffuse bonding, it is difficult to achieve reliable bonding strength, since bonding with an insulating material or between metals is difficult.

Each component is described in more detail below .

IGBT 2 is an element obtained by pre-forming at least one transistor structure on a semiconductor substrate. The IGBT 2 is additionally formed by forming a collector electrode surface 2c, which is to act as a transistor electrode, on the entire IGBT 2 surface on one side, and also forming an emitter electrode surface 2e and a gate electrode surface 2g, which should act as transistor electrodes, on the surface of IGBT 2 on the other side so that its total surface area reaches preferably almost the total surface area for the entire surface on the other side. Similarly, diode 3 is an element obtained by pre-forming at least one diode structure on a semiconductor substrate. The diode 3 is further formed by forming an electrode surface 3c, which should act as a diode electrode, on the entire surface of the diode 3 on one side, and also forming an electrode surface 3e, which should act as a diode electrode, on the entire surface on the other side.

The surfaces from the collector electrode surface 2c, the emitter electrode surface 2e and the gate electrode surface 2g located on the IGBT surfaces 2, as well as the surfaces from the electrode surface 3c and the electrode surface 3e located on the surfaces of the diode 3, are polished and aligned for bonding with ceramic substrates 7 and 8 by binding at room temperature.

On the inner surface of the ceramic substrate 7, interconnect layers 4 and 5 are formed having patterns corresponding to the emitter electrode surface 2e and the IGBT 2 gate electrode surface 2e and the diode 3 electrode surface 3e at locations corresponding to the emitter electrode surface 2e, the gate electrode surface 2g and the surface 3e electrode. Layers 4 and 5 of the interconnect scheme are connected, respectively, with through interconnects 9 and 10 (second through interconnects) provided so as to penetrate the ceramic substrate 7 in the direction of its thickness. These end-to-end interconnects 9 and 10 act as electrode terminals for external interconnects. Meanwhile, on the inner surface of the ceramic substrate 8, an interconnect layer 6 is formed having a pattern corresponding to the surface of the IGBT 2 collector electrode 2 and the surface 3c of the diode 3 electrode at a location corresponding to the collector electrode surface 2c and the electrode surface 3c. The interconnect layer 6 is connected to the through interconnects 12 (first and third through electrodes) provided so as to penetrate the sealing member 11 and the ceramic substrate 7 in the direction of their thickness. These end-to-end interconnects 12 act as an electrode terminal for external interconnects.

The surfaces of layers 4, 5, and 6 of the interconnect pattern located on the inner surfaces of the ceramic substrates 7 and 8 are also polished and smoothed to bond with IGBT 2 and diode 3 by bonding at room temperature. Meanwhile, each of the layers 4, 5 and 6 of the interconnect circuit is formed so as to have a thickness of 10-100 μm, and has an electrical function as an interconnect, as well as a function of thermal radiation as a heat transfer element. In particular, heat generated by IGBT 2 and diode 3 is transferred to ceramic substrates 7 and 8 having high thermal conductivity through layers 4, 5 and 6 of the interconnect circuit made of metal, which have excellent thermal conductivity, and then released to the outside .

Thus, although polysilicon, etc. can be used for layers 4, 5 and 6 of the interconnect circuit and the through electrodes 9, 10 and 12, for the above reason, it is desirable to metal, in particular copper and the like, having a low electrical resistance and excellent thermal conductivity. In addition, for ceramic substrates 7 and 8, an insulating material that has high thermal conductivity and has a similar coefficient of thermal expansion with a semiconductor material such as silicon (Si) used for the semiconductor element substrates is suitable. For example, aluminum nitride (AlN) and the like. is preferred. For example, the coefficient of thermal expansion of AlN (approximately 5 × 10 ^-6 / K) is similar to the coefficient of thermal expansion of Si (3.5 × 10 ^-6 / K), and therefore, the problem of thermal stress can be mitigated even when operating at high temperature semiconductor element module.

Meanwhile, the through electrodes 9, 10 and 12 are provided so as to penetrate the ceramic substrates 7 and 8 and the sealing element 11 and connect to the respective layers 4, 5 and 6 of the interconnect circuit. Consequently, the interconnect distance may be reduced. This allows you to reduce the inductance in the module and thereby reduce the number of capacitors in the control circuit of semiconductor elements.

The collector electrode surface 2c, the emitter electrode surface 2e and the IGBT 2 gate electrode surface 2g and the electrode surface 3c and the electrode surface 3e located on the surfaces of the diode 3 are directly connected to the interconnect layers 4, 5 and 6 corresponding to these electrode surfaces by using binding at room temperature. Therefore, IGBT 2 and diode 3 are mounted and mechanically, electrically and thermally connected to ceramic substrates 7 and 8.

Meanwhile, end-to-end interconnects 9, 10, and 12 are provided on the ceramic substrate 7 as external electrode contact terminals, as shown in FIG. 1, which means that all the outer electrode contact terminals are located on the surface on one side. Thus, connection to external interconnects can be simplified.

In this case, a cooling means, such as a cooling fin, can be bonded to a ceramic substrate 8, in which there are no through-wiring 9, 10, and 12, as described in Embodiment 3 described below. This simplifies the application of the entire module to the structure to improve cooling efficiency. In this regard, if this does not have to be taken into account, end-to-end interconnects 12 can be provided so as to penetrate the ceramic substrate 8 and connect to the layer 6 of the interconnect circuit.

In addition, the sealing element 11 is associated with the outer edge parts of the ceramic substrates 7 and 8 and has the function of sealing the inside of the module. The sealing element 11 is bonded to ceramic substrates 7 and 8 by bonding at room temperature. When bonding is performed in such a way that IGBT 2 and diode 3 are placed between the ceramic substrates 7 and 8, voids (parts indicated by reference numerals 13) created between IGBT 2 and diode 3 and between each of IGBT 2 and diode 3 and the sealing element 11, become rarefied or sealed with an inert gas such as argon (Ar). Otherwise, voids are filled with polymer aggregate 13, such as silicone grease and the like, to hold IGBT 2 and diode 3. Filling aggregate 13 is desirable in terms of cooling efficiency (thermal radiation efficiency).

As described above, the semiconductor element module 1 of this embodiment is obtained by bonding, by bonding at room temperature, the surfaces of electrodes formed on almost all surfaces of IGBT 2 and diode 3 with ceramic substrates 7 and 8 having high thermal conductivity, with layers 4, 5 and 6, interconnect circuits having high thermal conductivity are located between them. Thus, the IGBT 2 and the diode 3 are mounted in such a flat manner as to be placed between the ceramic substrates 7 and 8.

Accordingly, additional intermediate layers should not be provided between the binding surfaces. In addition, since the covalent bond makes the bond strong, the bonded interface can have low heat resistance. Thus, the thermal conductivity between the elements increases, which allows to achieve high thermal radiation. Large parts of the surfaces of the IGBT 2 and diode 3 are in close contact with conductive ceramic substrates 7 and 8 having high thermal conductivity, while the conductive layers 4, 5 and 6 of the interconnect circuit having high thermal conductivity are placed between them. Therefore, a two-sided cooling module structure is obtained in which large parts of both surfaces of the IGBT 2 and diode 3 are used as surfaces through which heat is transferred. This allows you to achieve additionally higher thermal radiation.

In addition, the surfaces of the IGBT 2 electrodes and diode 3 are directly bonded to layers 4, 5 and 6 of the interconnect pattern of ceramic substrates 7 and 8 by bonding at room temperature without the use of solder or wires. Therefore, the bond strength between them can be set as high as the bond strength of dry materials, which can significantly increase the vibration resistance of the parts in which IGBT 2 and diode 3 (parts of interconnects) are mounted. In addition, the interconnects can withstand high temperatures and therefore the heat resistance can be increased. In addition, the number of processes can be reduced and the reduction in production costs, therefore, can be achieved.

As a result, a higher operating temperature of the semiconductor element can be achieved, as well as a uniform temperature in the plane. In particular, it is possible to increase the wear resistance and reliability of parts of the interconnects against cyclic high-temperature exposure. In addition, since heating is not required during bonding, thermal deformation is not caused, and thus thermal stress is not generated. Accordingly, the reliability of the semiconductor element module itself can also be improved.

It should be noted that ceramic substrates 7 and 8 have small thicknesses and IGBT 2 and diode 3 are mounted between ceramic substrates 7 and 8 in a flat manner. Therefore, when the module is formed, its thickness can be significantly reduced, which makes the module compact. For example, provided that the thickness of each ceramic substrate is 2 mm and the thickness of each semiconductor element is 1 mm, the thickness of the entire module is approximately 5 mm (= 2 × 2 mm +1 mm), indicating that the thickness may decrease to approximately one tenth of the thickness of traditional modules.

It should be noted that although the configuration in this embodiment is such that each semiconductor element has electrode surfaces on both of its surfaces, elements each of which has electrode surfaces only on its surface on one side can be used instead. In this case, the surfaces of the interconnects corresponding to the surfaces of the electrodes of the semiconductor elements, as well as the end-to-end interconnects as electrode contact leads to the outside, can be formed on one of the ceramic substrates. The other ceramic substrate and the semiconductor elements can communicate with each other by bonding at room temperature without forming a layer of interconnects in this ceramic substrate.

Furthermore, although bonding is performed after the surfaces of the electrodes are polished and smoothed in this embodiment, they need not be flat. For example, a method may be used in which, when the aligned ceramic substrate is to be bonded to the semiconductor element by bonding at room temperature, a portion of the electrode protruding slightly from the bonding surface is compressed so that conductivity can be provided.

Furthermore, the configuration in this embodiment is such that electrode surfaces are formed on all or substantially all of the surfaces of the semiconductor elements. However, instead of using all surfaces for the electrodes, the configuration may be such that part of the surface is used for electrodes or several electrodes are formed on part or all of the surface (see Fig. 9 (b) and 9 (c), which should be described below). An example of this is an example in which several gate electrodes and emitter electrodes are formed on a surface on one side and several collector electrodes are formed on a surface on the other side or an electrode surface as a common collector electrode is formed on the entire or substantially all surface on the other side. Even in this case, the semiconductor elements are directly bonded to ceramic substrates by bonding at room temperature in parts other than those where the electrodes are. Therefore, strong bonding and high thermal radiation can be achieved. In addition, in the above case, the configuration may be such that the interconnect surfaces corresponding to the electrode patterns of the semiconductor elements are formed on ceramic substrates or that only the through electrodes are formed at positions corresponding to the electrodes. In addition, you can use a method in which the conductivity is established by squeezing, by welding, the surfaces of the electrodes and the surfaces of the interconnects formed from softer materials than semiconductor elements and their insulating substrates.

Furthermore, the configuration in this embodiment is such that through-through interconnects 9, 10 and 12 as external electrode terminals are provided in a penetrating manner in the thickness direction of the ceramic substrates 7 and 8. However, the following interconnects may be formed in place of these through-through interconnects. In particular, as wire interconnects that connect to layers 4, 5 and 6 of the interconnect circuitry and act as external electrode contact terminals, interconnects can be formed so as to extend from the surface of at least one of the ceramic substrates 7 and 8 in the lateral direction and penetrate through the sealing element 11 in the lateral direction, which should act as the outer peripheral part between the ceramic substrates 7 and 8. Alternatively, the grooves can be formed so Braz, to move away from the surface, at least one of the ceramic substrates 7 and 8 in a lateral direction, and wirings may be formed in the grooves so as to penetrate at least through one of the ceramic substrates 7 and 8 in a lateral direction.

Second Embodiment

FIG. 2 shows block diagrams illustrating another exemplary embodiment of a semiconductor cell module according to the present invention. It should be noted that identical reference numbers are assigned to components identical to the components in the semiconductor element module illustrated in Embodiment 1 (FIG. 1), and a duplicate description is omitted.

As shown in FIG. 2 (a), the semiconductor element module 21 of this embodiment has a configuration substantially identical to that of the module in Embodiment 1, but differs in layers 22, 23 and 24 of the interconnect pattern of the ceramic substrates 7 and 8 formed respectively for the collector electrode surface 2c , the emitter electrode surface 2e and the gate electrode surface 2g located on the IGBT surfaces 2, and the electrode surface 3c and the electrode surface 3e located on the surfaces of the diode 3.

Similarly to layers 4 and 5 of the interconnect circuit in Embodiment 1, interconnect layers 22 and 23 (second interconnect surface) having patterns corresponding to the emitter electrode surface 2e and the IGBT gate electrode surface 2g and the electrode surface 3e are formed on the inner surface of the ceramic substrate 7. diode 3 at locations corresponding to the emitter electrode surface 2e, the gate electrode surface 2g, and the electrode surface 3e. Additionally, the interconnect layers 22 and 23 are connected, respectively, with the through interconnects 9 and 10 provided to penetrate the ceramic substrate 7. Like the interconnect layer 6 in the embodiment 1, an interconnect layer 24 is formed on the inner surface of the ceramic substrate 8. (first interconnect surface) having a pattern corresponding to the surface 2c of the collector electrode IGBT 2 and the surface 3c of the electrode of the diode 3 at a location corresponding to the surface 2c of the collector electrode Ora and electrode surfaces 3c. Additionally, the interconnect layer 24 is connected to the sealing member 11 and through-through interconnects 12 provided so as to penetrate the ceramic substrate 7.

The configuration in this embodiment, however, is such that several parts of the high aspect ratio grooves 22a (23a, 24a) are vertically formed in each flat layer of the interconnect network as shown in FIG. 2 (b) in order to reduce the load on the bonded interface, inherent in connection with the differences between the expansion coefficients of IGBT 2 and diode 3 and the expansion coefficients of ceramic substrates 7 and 8. Thus, several thin columnar electrodes 22b (23b, 24b), which are rectangular, polygonal or circular, are formed on the surface side of the layer 22 (23, 24) of the interconnect circuit. The bonding surfaces of the columnar electrodes 22b (23b, 24b) are in the form of rectangular, polygonal or circular points and are bonded to the surfaces of the IGBT 2 electrodes and diode 3 (the illustration of the surfaces of the IGBT 2 electrodes and diode 3 is omitted). The front end of each columnar electrode 22b (23b, 24b) is flat and has a predetermined cross-sectional area, and its length is set equal to a predetermined length. Thus, a structure is provided that enables columnar electrodes 22b (23b, 24b) to provide electrical connection and thermal connection in their longitudinal direction, as well as elastically deform in the orthogonal direction (horizontal direction in Fig. 2 (b)) for the longitudinal direction. The structure thereby leads to the fact that the column electrodes 22b (23b, 24b) act as interconnects for IGBT 2 and diode 3, as well as a heat transfer element for thermal radiation. Additionally, the structure causes the convex portions 22b (23b, 24b) to elastically deform when biasing of the IGBT 2 and the diode 3 occurs due to thermal expansion, whereby the load formed in this way is weakened without deterioration of the electrical connection and thermal connection.

In this regard, the structure of the interconnect layer 22 (23, 24) may be the structure of a square truncated pyramid, a polygonal truncated pyramid, or a truncated cone (rotated trapezoid), similarly to the interconnect layer 31 shown in FIG. 3 (a). In particular, the configuration is such that several tapered wedge portions 31a with high aspect ratios are formed in a flat layer of the interconnect pattern, so that several columnar electrodes 31b, each of which are in the form of a square truncated pyramid, a polygonal truncated pyramid or a truncated cone, are formed on the surface layer 31 of the interconnect circuit. The bonding surfaces of the columnar electrodes 31b are square, polygonal or circular in shape and are bonded to the surfaces of the IGBT 2 and diode 3 electrodes (illustration of the surfaces of the IGBT 2 electrodes and diode 3 is omitted). The front end of each columnar electrode 31b is also flat and has a predetermined cross-sectional area, and its length is set equal to a predetermined length. Thus, a structure is provided that enables columnar electrodes 31b to provide electrical connection and thermal connection in their longitudinal direction, as well as elastically deform in the orthogonal direction (horizontal direction in Fig. 3 (a)) for the longitudinal direction. The structure thereby causes the column electrodes 31b to act as interconnects for IGBT 2 and diode 3, as well as a heat transfer element for thermal radiation. Additionally, the structure causes the convex portions 31b to elastically deform when biasing of the IGBT 2 and the diode 3 occurs due to thermal expansion, whereby the load formed in this way is weakened without deterioration of the electrical connection and thermal connection.

The following describes the elastically deformed state of the layer 31 of the interconnect having the above structure.

IGBT 2 and diode 3 generate heat when used. Through this heat generation, the substrates are thermally expanded and displaced. The bias due to thermal expansion is large, in particular when it comes to IGBT 2 and diode 3, whose output powers are large. In traditional modular structures, displacement cannot be allowed, so that the electrical connection and thermal connection are degraded. This seriously affects the reliability and life of the module. For example, the maximum displacement value can be calculated under the assumption that: the size of each semiconductor element is 10 mm ² ; temperature increase due to heat generation is 500 ° C; the coefficient of thermal expansion of Si forming the substrate of the semiconductor element is approximately 3.5 × 10 ^-6 / K; the coefficient of thermal expansion of Cu, forming the surface of the electrodes and the layers of the interconnect scheme, is 17 × 10 ^-6 / K and the coefficient of thermal expansion of AlN, forming ceramic substrates, is 5 × 10 ^-6 / K. Then, it is expected that the displacement is approximately 7.5 μm at the Si-AlN interface and approximately 65 μm at the Si-Cu interface, and it is assumed that a large displacement should occur at the Si-Cu interface.

In contrast, in this embodiment, even when the IGBT substrates 2 and the diode 3 thermally expand and the thermal expansion causes them to shift, the column electrodes 22b, 23b and 24b or the column electrodes 31b are elastically deformed by the wiring layers 22, 23 and 24 of the interconnect or layers 31 wiring diagrams having the above structure. Offset can therefore be allowed. As a result, reliability and service life can be ensured without deterioration of the electrical connection and thermal connection.

It should be noted that the interconnect layers are not limited to the interconnect layer 31 shown in FIG. 3 (a). An interconnect layer 32 may be used, which is formed from several columnar / cone-shaped column electrodes 32b separated from each other by groove portions 32a, as shown in FIG. 3 (b). You can also use the interconnect layer 33, which is formed of several columnar / cone-shaped column electrodes 33b and 33c, separated by groove parts 33a, and in which the upper sides of each pair of adjacent column electrodes 33b and 33c are facing in mutually different directions as shown in FIG. 3 (c). In addition, the columnar electrodes 32b in the form of a pyramid / cone layer 32 of the interconnect circuit shown in FIG. 3 (b) may be located with inverted vertices. Additionally, the structure of the column electrodes may be such that the column electrodes 22b, 23b and 24b of the layers 22, 23 and 24 of the interconnect circuit shown in FIG. 2 (b) are separated from each other by means of the groove portions 22a, 23a and 24a.

In the columnar electrode structures shown in FIG. 2 (b) and 3 (a) -3 (c), the bead on the edge of the bonding portion of each of the column electrodes is at a right angle or a predetermined angle of inclination with the surface of the bonding target. For example, in FIG. 2 (b), the flange on the edge of the bonding portion of each columnar electrode 22b (23b, 24b) on the side closer to the IGBT 2 or diode 3 is substantially at right angles to the surface of the IGBT 2 or diode 3 on which the bonding takes place. Stress relaxation is sufficient even with this configuration. However, additional stress relaxation should be possible if the collar on the edge of the binding portion of each column electrode 22b (23b, 24b) is formed in a circular shape with a predetermined curvature (i.e., a shape defined as R), as shown in FIG. . 2 (c). In this case, R can be defined for the shoulder on the edge of the binding part of the column electrode 22b (23b, 24b) on the side closer to the surface of the IGBT 2 or diode 3 or for the shoulder on the edge of the binding part of the column electrode 22b (23b, 24b) on the side closer to the surface of the interconnects corresponding to one of the ceramic substrates 7 and 8.

As explained in Embodiment 4 below, columnar electrodes are formed using microprocessing technology, such as laser or electron beam etching or stamping through compression molding. When R is formed in a collar at the edge of the binding part of the column electrode, R can be formed in the collar at the edge of the binding part of the column electrode by using laser heat or electron beams during or after the formation of the column electrode. Alternatively, R may be formed in a flange at the edge of the binding part of the columnar electrode by imprinting with a mold on which R is formed during formation of the columnar electrode.

In addition, in this embodiment, similarly to the parts indicated by reference numerals 13 in Embodiment 1, the groove parts 22a, 23a and 24a or the groove parts 31a may become rarefied, sealed with an inert gas, or alternatively filled with a filler from a polymer, such as silicone grease, etc., taking into account the increase in thermal conductivity.

Third Embodiment

FIG. 4 shows a block diagram illustrating another exemplary embodiment of a semiconductor cell module according to the present invention. It should be noted that identical reference numbers are assigned to components identical to the components in the semiconductor element modules illustrated in embodiments 1 and 2 (FIGS. 1 and 2), and a duplicate description is omitted.

The semiconductor element module of this embodiment is obtained by directly bonding, by binding at room temperature, thermal radiation ribs 41 (cooling means) made of metal that has excellent thermal radiation, with a ceramic substrate 8 of module 1 or 21 of the semiconductor element shown in embodiment 1 or 2 (FIG. 1 or 2).

In particular, the bonding surface of the ceramic substrate 8 of the module 1 or 21 of the semiconductor element and the surface of the fin 41 for thermal radiation are activated by physical sputtering through the emission of ion beams and the like. and then by welding to each other under pressure at room temperature, whereby the bonding surfaces are directly bonded to each other. In this regard, the cooling means can be a fin for thermal radiation, for example, and it can be, for example, a cooling unit containing a passage through which a refrigerant, such as water, is forced to flow, or a similar means or, alternatively, structure, which such a cooling module is pre-integrated into the substrate itself by forming a passage, etc. in the backing itself.

As described in embodiments 1 and 2, in the present invention, interconnects for IGBT 2 and diode 3 located internally can be formed from through interconnects 9, 10 and 12 provided for one of the ceramic substrates, i.e. ceramic substrate 7. A cooling agent, such as thermal radiation rib 41, can therefore be bonded to another ceramic substrate 8. Furthermore, bonding at room temperature allows direct bonding between ceramic substrate 8 and thermal radiation rib 41 without the need for an intermediate element. This leads to a higher strength of the physical bond, which, in turn, leads to a stronger thermal connection. Thus, high thermal conductivity can be achieved between the ceramic substrate 8 and the rib 41 for thermal radiation.

In addition, the binding process by binding at room temperature is performed at room temperature, as mentioned previously. Thus, the influence associated with heating is not caused in the module, so that thermal stress is not generated. Strong bonding can also be achieved even when bonding various materials. Meanwhile, an intermediate element, in order to maintain binding, may be necessary in some cases, depending on the type of material. However, in this case, the strength of the physical bond is also high, and therefore, the thermal bond is strong. Therefore, high thermal conductivity can be achieved between the ceramic substrate 8 and the rib 41 for thermal radiation.

It should be noted that the configuration in this embodiment is such that a thermal radiation rib 41 is provided for the outer surface of the ceramic substrate 8 having no through wiring penetrating therethrough in the thickness direction; instead, if the through wiring is located only on the side of the ceramic substrate 8, a thermal radiation rib 41 may be provided for the outer surface of the ceramic substrate 7 having no through wiring penetrating therethrough in the thickness direction. Meanwhile, if wire interconnects protruding laterally from the ceramic substrates 7 and 8 are provided instead of end-to-end interconnects, there are no end-to-end interconnects on the ceramic substrates 7 and 8, and thus the thermal radiation rib 41 can be attached to the outer surface of each of the ceramic substrates 7 and 8.

Fourth Embodiment

The following describes a method for manufacturing modules 1 and 21 of the semiconductor elements illustrated in embodiments 1 and 2 (FIGS. 1, 2, etc.) using FIG. 5-8. Here, FIG. 5 shows a diagram illustrating elements in an unassembled state constituting a semiconductor element module 1 or 21, illustrated in embodiment 1 or 2, and is used to explain the structure of the method for manufacturing the module. FIG. 6-8 are diagrams for explaining the details of manufacturing steps in a manufacturing method. Thus, each manufacturing step is described with reference to FIG. 5. It should be noted that identical reference numbers are assigned to components identical to the components in modules 1 and 21 of the semiconductor elements illustrated in embodiments 1 and 2.

(1) Preparation of items

IGBT 2, diode 3, ceramic substrate 7, ceramic substrate 8 and sealing element 11 are prepared in advance.

Regarding IGBT 2 and diode 3, at least one transistor structure and a diode structure are formed on semiconductor substrates by using common semiconductor processes. On both surfaces of the semiconductor substrates, formed electrode surfaces are provided (collector electrode surface 2c, emitter electrode surface 2e, gate electrode surface 2g, electrode surface 3c and electrode surface 3e), which must be connected to the transistor structure and the diode structure. These electrode surfaces are formed so as to have the largest possible area. For example, the collector electrode surface 2c and the electrode surface 3c are formed on the entire surface of the corresponding one of the IGBT 2 and the diode 3 on one side. The surface 3e of the electrode is formed on the entire surface of the diode 3 on the other side. The emitter electrode surface 2e and the gate electrode surface 2g are formed on the IGBT 2 surface on the other side so as to have the largest possible areas while providing isolation from each other. These electrode surfaces are used not only to provide an electrical connection, but also to provide a thermal connection, therefore, they have the function of transferring heat generated by IGBT 2 and diode 3.

In this regard, the configuration may be such that a part of the surface is used for the electrodes or a plurality of electrodes are formed on all or part of the surface (see Figs. 9 (b) and 9 (c), which should be described below). Then, interconnect surfaces corresponding to patterns of electrodes of the semiconductor element or only through electrodes at positions corresponding to the electrodes can be formed on the ceramic substrate. Even in this case, the semiconductor element is directly bonded to the ceramic substrate by bonding at room temperature in parts other than those where the electrodes are. Therefore, strong bonding and high thermal radiation can be achieved.

Ceramic substrates 7 and 8 are formed in flat plate forms by using the general ceramic manufacturing process. Then, on the surface of each of the ceramic substrates 7 and 8 on one side (a surface located on the inner side after the module is formed), interconnect layers 4, 5 and 6 (or interconnect layers 22, 23 and 24) are formed at locations corresponding to the surfaces of the IGBT 2 electrodes and diode 3. Additionally, the through wiring 9, 10 and 12, which should be connected, respectively, with layers 4, 5 and 6 of the interconnect (or layers 22, 23 and 24 of the interconnect) are formed penetrating through ceramic substrate 7. Other and in words, layers 4, 5 and 6 of the interconnect (or layers 22, 23 and 24 of the interconnect) form a pattern such that the conductivity is established between the surfaces of the IGBT 2 electrodes and the diode 3 and the corresponding end-to-end interconnects 9, 10 and 12. The sealing element 11, in order to seal the inside of the module, is formed in a hollow flat plate form by using the general ceramic manufacturing process. End-to-end interconnects 12, which are to be connected to the interconnect layer 6 (24), are also formed in the sealing element 11 so as to penetrate the sealing element 11 itself.

Regarding the interconnect layers 4 and 5, the interconnect layers 4a and 5a are formed directly on the ceramic substrate 7 through a film forming process, as shown, for example, in FIG. 6 (a). As the film-forming process, a general film-forming process is used, for example, such as CVD (chemical vapor deposition), metallization, spraying, and the like. More specifically, the interconnect layers 4a and 5a corresponding to the surfaces of the IGBT 2 electrodes and the diode 3 can be formed by forming a film on the entire surface of the ceramic substrate 7 and removing a part thereof and thereby forming a pattern on the film by etching or the like. Alternatively, the interconnect layers 4a and 5a corresponding to the surfaces of the IGBT 2 electrodes and the diode 3 can form a pattern by forming them selectively by masking.

As another alternative for interconnect layers 4 and 5, as shown in FIG. 6 (b), the interconnect layers 4b and 5b corresponding to the surfaces of the IGBT 2 electrodes and the diode 3 can be formed by patterning on the metal foil in a separate process, and then the metal foil interconnect layers 4b and 5b can bond to the surface of the ceramic substrate 7 by binding at room temperature. Interconnect layers 4b and 5b corresponding to the surfaces of the IGBT 2 electrodes and diode 3 can also be formed by bonding the metal foil to the entire surface of the ceramic substrate 7 by bonding at room temperature and then removing part of it and thereby forming a pattern on the metal foil by etching and etc. When the metal foil is to be bonded to the ceramic substrate 7, an intermediate layer 7a may be formed between the metal foil and the ceramic substrate 7 if the bond strength between them is to be increased. Examples of the material of the intermediate layer include metals, for example gold (Au), platinum (Pt), titanium (Ti) and aluminum (Al).

The layer 6 of the interconnect pattern of the ceramic substrate 8 can be prepared similarly to the layers 4 and 5 of the interconnect pattern. However, the interconnect layer 6 should not form a pattern, respectively, for the surfaces of the IGBT 2 electrodes and the diode 3, as in the case of the interconnect layers 4 and 5. Therefore, the interconnect layer 6 can be formed on almost the entire surface of the ceramic substrate 8 through a film-forming process. The interconnect layer 6 can also be formed by separately preparing the metal foil as the interconnect layer 6 and then bonding the metal foil over the entire surface of the ceramic substrate 8 by bonding at room temperature.

It should be noted that according to the information on the interconnect layers 22, 23 and 24 or the interconnect layers 31 illustrated in Embodiment 2, several vertical grooves, each of which has a high aspect ratio in the thickness direction, can be formed in flat layers of the interconnect, formed on ceramic substrates 7 and 8. In this way, interconnect layers 22, 23 and 24 or interconnect layers 31 having a structure with several thin columnar electrodes are formed. For example, in processing the interconnect layers 4a, 5a, and 9a, several thin vertical grooves with a high aspect ratio can be formed in the flat layers of the interconnect having a thickness of 10-100 μm by using microprocessing technology such as laser or electron beam etching 51 as shown in FIG. 6 (c), or stamping through extrusion in molds. Thus, interconnect layers 4a, 5a and 9a are formed having a structure with several thin columnar electrodes.

Meanwhile, when a metal foil is used, as in the case of interconnect layers 4b, 5b and 9b, several thin vertical grooves with a high aspect ratio can be formed in the metal foil in advance and the metal foil can then be bonded to the ceramic substrates 7 and 8 by bonding at room temperature. In this manner, interconnect layers 4b, 5b and 9b are formed having a structure with several thin columnar electrodes. Additionally, a structure with several thin columnar electrodes can be formed by extrusion pressing or growing a metal film in specific areas. In addition, a structure with several thin columnar electrodes can be formed through a multilayer structure by binding at room temperature.

It should be noted that the interconnect layers 22, 23 and 24 or the interconnect layers 31 having a columnar electrode structure are preferably formed in a deformable, and more preferably in an elastic deformable form and with a size suitable based on the operating environment (e.g., operating temperature electrode material, etc.). In addition, the aspect ratio of the columnar electrode structure is preferably 5: 1 and higher, and more preferably 10: 1 and higher.

The use of layers 22, 23 and 24 of the interconnect circuit or layers 31 of the interconnect circuit having a columnar electrode structure makes it possible to reduce loads due to heat generation, and also reliably provide electrical connection and thermal connection of the layers 22, 23 and 24 of the interconnect circuit or layers 31 of the interconnect circuit.

When bonding, by bonding at room temperature, the thus prepared IGBT 2, diode 3, ceramic substrate 7, ceramic substrate 8 and sealing element 11, their bonding surfaces are polished and leveled for more reliable and stronger bonding than otherwise. In particular, CMP (chemical mechanical polishing) device 52, for example, is used to polish and smooth: surfaces of elements including a collector electrode surface 2c, an emitter electrode surface 2e and a gate electrode surface 2g for IGBT 2; element surfaces including an electrode surface 3c and an electrode surface 3e for a diode 3; the surfaces of layers 4 and 5 of the interconnect pattern for the ceramic substrate 7; the surface of layer 6 of the interconnect pattern for the ceramic substrate 8 and the like. (see Fig. 6 (d)). Polishing and surface leveling are carried out by means of a chemical-mechanical process, such as CMP, or a mechanical grinding process using a reverse grinding machine, etc. It should be noted that bond strength through bonding at room temperature is influenced by surface roughness for bonding surfaces. Thus, it is desirable to level the surfaces to maximum smoothness, preferably by means of CMP and the like. Thus, the presence of voids on the bonded interface is not allowed, which, in turn, allows to achieve a higher bond strength than in other cases.

(2) Linking elements

The following steps are performed in order to bond the prepared IGBT 2, the diode 3, the ceramic substrate 7, the ceramic substrate 8 and the sealing element 11, the bonding surfaces of which are polished and aligned.

(2I) Binding of IGBT 2 and Diode 3 to Ceramic Substrate 8

The prepared IGBT 2, diode 3, and ceramic substrate 8, the binding surfaces of which are polished and aligned, are bonded together as follows. When these elements are placed in the vacuum chamber of the processing equipment used to perform binding at room temperature, the activation treatment to clean and activate the binding surfaces of these elements is first performed through physical sputtering using ion beams and argon 53, etc. P. or through a similar process as shown in FIG. 7 (a).

In particular, under high vacuum conditions, inactive layers formed on the bonding surfaces (for example, impurities adhering to surfaces, products of materials processing, extreme outer surface layers of materials having weak reactivity due to rupture of their bonds by oxygen, etc.) are removed by physical spraying, etc. Thus, the binding surfaces are cleaned and also transferred to a state in which unsaturated bonds are present on the binding surface, i.e. an activated state in which active surfaces are visible from binding surfaces. Ion beams of inert atoms (e.g. argon, etc.), beams of fast atoms (FAB), plasma, etc., are used as a means for physical deposition. In this regard, activation processing can be performed by pre-positioning the IGBT 2, the diode 3, and the ceramic substrate 8 at such locations that the IGBT 2 and the diode 3 are located opposite the ceramic substrate 8, and then physically spraying them simultaneously on their surfaces.

Then, the activated binding surfaces are set so as to be located opposite each other, after which their positions are adjusted. After this, the bonding surfaces are brought into contact with each other and pressure welded to each other by applying loads F to them, as shown in step S1 in FIG. 5 and FIG. 7 (b). Since unsaturated bonds are formed on the bonding surfaces by surface activation, pressure welding causes unsaturated bonds to form bonding. Therefore, the surface 2c of the IGBT electrode 2 and the surface 3c of the electrode of the diode 3 are firmly bonded to the interconnect layer 6 of the ceramic substrate 8 by bonding at room temperature, so that electrical continuity and thermal continuity are established. When bonding at room temperature in this manner, bonding occurs between the unsaturated bonds of each binding surface and the unsaturated bonds of the corresponding binding surface. Thus, high bond strength can be achieved. In addition, since the binding is carried out at room temperature, thermal deformation is not caused.

(2II) Bonding of the sealing member 11 to the ceramic substrate 8

Then, the ceramic substrate 8 to which the IGBT 2 and the diode 3 are connected, and the sealing element 11 are connected to each other as follows. Similarly to (2I) described above, in a vacuum chamber, activation processing is performed on the binding surfaces of these elements. Then, the activated binding surfaces are set so as to be located opposite each other, after which their positions are adjusted. After that, the bonding surfaces are brought into contact with each other and pressure welded to each other when a load is applied to them (step 2 in Fig. 5 and Fig. 8 (a)). Accordingly, the ceramic substrate 8 and the sealing element 11 are firmly bonded to each other by bonding at room temperature. In this case, the through wiring 12 provided for the sealing element 11 is also firmly bonded to the layer 6 of the wiring diagram of the ceramic substrate 8, so that electrical continuity and thermal continuity are established. After bonding to the ceramic substrate 7, which should be described below, the sealing element 11 seals the inside of the module, acting as a means to seal and also protect the IGBT 2 and diode 3. It should be noted that on the outer edge part of the ceramic substrate 8 an external peripheral wall is formed in advance, which is configured to seal the inside of the module in the same way as the sealing element 11. IGBT 2 and the diode 3 can communicate with areas inside the external peripheral wall .

(2III) Bonding of IGBT 2, Diode 3, and Sealing Element 11 to Ceramic Substrate 7

Finally, the IGBT 2, the diode 3, and the sealing element 11, after bonding to the ceramic substrate 8, bind to the ceramic substrate 7 as follows. Similarly to (2I) described above, in a vacuum chamber, activation processing is performed on the binding surfaces of these elements. Then, the activated binding surfaces are set so as to be located opposite each other, after which their positions are adjusted. After this, the bonding surfaces are brought into contact with each other and pressure welded to each other when a load is applied to them (step 3 in Fig. 5 and Fig. 8 (b)). Accordingly, the ceramic substrate 7 and the sealing element 11 (or the outer peripheral wall) are firmly bonded to each other by bonding at room temperature. In addition, the emitter electrode surface 2e and the IGBT 2 gate electrode surface 2g and the diode 3 electrode surface 3e are firmly bonded to layers 4 and 5 of the interconnect pattern of the ceramic substrate 7, which form a pattern, respectively, for these electrode surfaces. Thus, electrical continuity and thermal continuity are established.

In the case of vacuum sealing of the inside of the module, the inside of the module is naturally vacuum sealed after the bonding in (2III) described above, since the bonding of the sealing element 11 by bonding at room temperature is carried out in a vacuum atmosphere and thereby the sealing element 11 ( or external peripheral wall) acts as an air sealant. Meanwhile, in the case of sealing the inside of the module with a polymer, predetermined inlets are provided in advance in the ceramic substrates 7 and 8. Then, after bonding, a fluid insulating polymer is injected or vacuum sucked to be introduced from the inlets into the gaps within the module, whereby the inside of the module is sealed with polymer.

Through the above manufacturing steps, IGBT 2 and diode 3 are mounted on the inside between the ceramic substrates 7 and 8, and a semiconductor element module 1 or 21 according to the present invention is manufactured.

In this embodiment, as one example, manufacturing steps that are performed in sequence as described above, i.e. with the beginning in (2I) for bonding IGBT 2 and diode 3 with a ceramic substrate 8 (bonding and mounting a collector electrode, etc.), then (2II) is performed for bonding the sealing element 11 with the ceramic substrate 8 (forming the sealing part) and then (2III) for bonding the IGBT 2, the diode 3, and the sealing element 11 to the ceramic substrate 7 (bonding and mounting the emitter electrode, gate electrode, and the like). However, note that the present invention does not always have to follow this sequence. For example, the sequence may be such that (2I) and (2III) are interchanged. Similarly, after the module is formed, the thermal radiation rib 41 can also bind to the ceramic substrate 8 by bonding at room temperature, as shown in FIG. four.

As described above, using the method for manufacturing the semiconductor element module according to the present invention, the interconnect formation process and the mounting process are performed only by bonding the flat surfaces of the IGBT 2 electrodes and the diode 3 to the flat layers 4, 5 and 6 of the interconnect circuit (or layers 22, 23 and 24 interconnect patterns) of ceramic substrates 7 and 8 in a planar manner. Thus, compared with traditional cases, module manufacturing processes can be greatly simplified, and the number of required components can be reduced. This makes it possible to significantly reduce production costs.

It should be noted that examples of electrode layouts of semiconductor elements such as IGBT 2 and diode 3 include configurations as shown in FIG. 9 (a) -9 (d) (in FIG. 9, a description is given with IGBT 2 as an example). In particular, all electrode surfaces (emitter electrode surface 2e, gate electrode surface 2g and collector electrode surface 2c) can be located on the entire IGBT 2 surface on one side such that each electrode surface has the largest possible area (see FIG. 9 (a)). On the IGBT surface 2 on one side, as described above, each of the electrode surfaces (emitter electrode surface 2e, gate electrode surface 2g and collector electrode surface 2c) can also be arranged in a row (see Fig. 9 (b)). On the IGBT 2 surface on one side, as described above, each of the electrode surfaces (emitter electrode surface 2e, gate electrode surface 2g and collector electrode surface 2c) can be positioned so as to occupy part of the total surface area of IGBT 2 (see FIG. . 9 (c)). In addition, electrode surfaces with patterns identical to those of any of the above arrangement examples may be formed on both surfaces of the IGBT 2. In addition, some of the electrode surfaces (emitter electrode surface 2e and gate electrode surface 2g) may be arranged in a row on the IGBT surface 2 on one side with the remaining electrode surface (collector electrode surface 2c) in a row on the IGBT 2 surface on the other side (see FIG. 9 (d)). In these cases, the interconnect surfaces corresponding to the patterns of the electrodes of the semiconductor element can be formed on the ceramic substrate (s), or only through electrodes can be formed penetrating through the ceramic substrate at a location corresponding to the surfaces of the electrodes.

Industrial applicability

The present invention is suitable for a semiconductor element module in which several semiconductor elements, such as power transistors with high output power and heat generation, are integrated into one set, as well as for a method for manufacturing the module. Such a semiconductor element module is also applicable to electric motor modules for electric cars and the like.

Claims (12)

1. A semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate using a sealing element, while:
- the semiconductor element includes metal and flat surfaces of the electrodes formed on all or almost all surfaces of the semiconductor element on both sides,
- the first insulating substrate includes a metal and a flat first surface of the interconnects formed on the surface of the first insulating substrate on one side so as to correspond to the surfaces of the electrodes of the semiconductor element on one side,
- the sealing element includes a metal first end-to-end interconnects connected to the first surface of the interconnects and provided so as to penetrate through the sealing element,
- the second insulating substrate includes:
a metallic and flat second interconnect surface formed on the surface of the second insulating substrate on one side so as to correspond to the electrode surfaces of the semiconductor element on the other side,
- metal second through wiring connected to the second surface of the wiring and provided so as to penetrate the second insulating substrate, and
- metal third through interconnects connected to the first through interconnects and provided so as to penetrate the second insulating substrate, and
- the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the first insulating substrate with the sealing element by bonding at room temperature, thereby thereby bonding the first surface of the interconnects to the first through interconnects, and bonding the surfaces of the electrodes of the semiconductor element to the first surface of the interconnects and a second interconnect surface by binding at room temperature. 2. The semiconductor element module according to claim 1, in which:
- many deformable and thin columnar electrodes are provided on surfaces from either the first and second surfaces of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and at least one of the first surface of the interconnects and the second surface of the interconnects is connected to the surfaces of the electrodes a semiconductor element with a plurality of columnar electrodes between them by bonding at room temperature. 3. The module of the semiconductor element according to claim 2, in which the shoulders on the edges of the binding parts of the columnar electrodes are rounded, and the shoulders are either on the sides closer to the first and second surfaces of the interconnects, or on the sides closer to the surfaces of the electrodes of the semiconductor element, or on both sides. 4. The module of the semiconductor element according to claim 2, in which cooling means for cooling the module of the semiconductor element is provided for the outer surface of at least one of the first insulating substrate and the second insulating substrate by bonding at room temperature, in case the first insulating the substrate and the second insulating substrate or either the first insulating substrate or the second insulating substrate do not have interconnects penetrating through them in the thickness direction. 5. A method for manufacturing a semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having a high thermal conductivity and a second insulating substrate having a high thermal conductivity, and an outer peripheral part between a first insulating substrate and a second the insulating substrate is sealed with a sealing element, the method comprising the steps of:
- form metal and flat surfaces of the electrodes on all or almost all surfaces of the semiconductor element on both sides;
- form a metal and flat first surface of the interconnects on the surface of the first insulating substrate on one side so that the first surface of the interconnects corresponds to the surfaces of the electrodes of the semiconductor element on one side;
- form the first metal end-to-end interconnects penetrating through the sealing element and connected to the first surface of the interconnects;
- form a metal and flat second surface of the interconnects on the surface of the second insulating substrate on one side so that the second surface of the interconnects corresponds to the electrode surfaces of the semiconductor element on the other side;
- form a metal second through wiring, penetrating through the sealing element and connected to the second surface of the wiring;
- form metal third through wiring, penetrating through the sealing element and connected to the first through wiring; and
- mount the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the first insulating substrate with a sealing element by bonding at room temperature, thereby thereby bonding the first surface of the interconnects to the first through interconnects, and bonding the surfaces of the electrodes of the semiconductor element to the first surface of the interconnects and a second interconnect surface by binding at room temperature. 6. A method for manufacturing a module of a semiconductor element according to claim 5, in which:
- a plurality of deformable and thin columnar electrodes is formed on surfaces from either the first and second surfaces of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and
- at least one of the first surface of the interconnects and the second surface of the interconnects is connected to the surfaces of the electrodes of the semiconductor element with a plurality of columnar electrodes between them by bonding at room temperature. 7. The method for manufacturing the semiconductor element module according to claim 6, wherein the shoulders are rounded at the edges of the column bonding parts of the column electrodes, the shoulders being either on the sides closer to the first and second surfaces of the interconnects, or on the sides closer to the surfaces of the electrodes of the semiconductor element, or both sides. 8. The method for manufacturing a semiconductor element module according to claim 6, wherein the cooling means for cooling the semiconductor element module is bonded to the outer surface of at least one of the first insulating substrate and the second insulating substrate by bonding at room temperature, if both the first insulating substrate and the second insulating substrate or either the first insulating substrate or the second insulating substrate do not have interconnects penetrating through them in the thickness direction. 9. A semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and the outer peripheral part between the first insulating substrate and the second insulating substrate , wherein:
- the semiconductor element includes a plurality of electrode surfaces formed over the entire surface of the semiconductor element on one side,
the first insulating substrate includes a plurality of first interconnect surfaces formed on the surface of the first insulating substrate on one side so as to correspond to each of the electrode surfaces of the semiconductor element,
- a lot of deformable and thin columnar electrodes are provided on surfaces from either the first surface of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and
- the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element to the first interconnect surfaces with a plurality of column electrodes between them by bonding at room temperature and bonding the surface of the semiconductor element on the other side to the second insulating substrate by bonding with room temperature. 10. A semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second insulating substrate , wherein:
- the semiconductor element includes a plurality of electrode surfaces formed on all surfaces of the semiconductor element on both sides,
- the first insulating substrate includes a first interconnect surface formed on the surface of the first insulating substrate on one side so as to correspond to the electrode surfaces of the semiconductor element on one side,
- the second insulating substrate includes a second interconnect surface formed on the surface of the second insulating substrate on one side so as to correspond to the electrode surfaces of the semiconductor element on the other side,
- a lot of deformable and thin columnar electrodes are provided on surfaces from either the first and second surfaces of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and
- the semiconductor element is mounted on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element on one side to the first interconnect surface by bonding at room temperature and bonding the electrode surfaces of the semiconductor element on the other side to the second interconnect surface by bonding at room temperature,
- and at least one of the first interconnect surface and the second interconnect surface is bonded to the electrode surfaces of the semiconductor element with a plurality of column electrodes between them by bonding at room temperature. 11. A method for manufacturing a semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second the insulating substrate is sealed, while the method comprises the steps of:
- form a plurality of electrode surfaces over the entire surface of the semiconductor element on one side,
- form a plurality of first interconnect surfaces on the surface of the first insulating substrate on one side such that the first interconnect surfaces corresponds to each of the electrode surfaces of the semiconductor element on one side;
- a plurality of deformable and thin columnar electrodes are formed on surfaces from either the first surface of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and
- mount the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element to the first interconnect surfaces with a plurality of column electrodes between them by bonding at room temperature and bonding the surface of the semiconductor element on the other side to the second insulating substrate by bonding with room temperature. 12. A method for manufacturing a semiconductor element module in which at least one semiconductor element is sandwiched between a first insulating substrate having high thermal conductivity and a second insulating substrate having high thermal conductivity, and an outer peripheral part between the first insulating substrate and the second the insulating substrate is sealed, while the method comprises the steps of:
- form a plurality of electrode surfaces on all surfaces of the semiconductor element on both sides,
- form the first surface of the interconnects on the surface of the first insulating substrate on one side so that the first surface of the interconnects corresponds to the surfaces of the electrodes of the semiconductor element on one side;
- form a second surface of the interconnects on the surface of the second insulating substrate on one side so that the second surface of the interconnects corresponds to the surfaces of the electrodes of the semiconductor element on the other side;
- a plurality of deformable and thin columnar electrodes are formed on surfaces from either the first and second surfaces of the interconnects, or the surfaces of the electrodes of the semiconductor element, or both, and
- mount the semiconductor element on the first insulating substrate and the second insulating substrate by bonding the electrode surfaces of the semiconductor element on one side to the first interconnect surface by bonding at room temperature and bonding the electrode surfaces of the semiconductor element on the other side to the second interconnect surface by bonding at room temperature,
- at least one of the first surface of the interconnects and the second surface of the interconnects is connected to the surfaces of the electrodes of the semiconductor element with a plurality of columnar electrodes between them by bonding at room temperature.

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