RU2428787C1 - Conversion method of binary signal to five-level signal - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: conversion method of binary signal to five-level signal consists in the fact that zero in input data is transmitted bit by bit to the line as zero, and when combination 10 or 11 is supplied in input data, the first unit bit is retained in delay trigger and zeroised; delayed bit is supplied to input of toggle trigger, and being addressed with value of output signal of toggle trigger and with the value of the second bit of combination, the delayed bit is supplied to one of four inputs of five-level shaper of output signal which supplies pulses to the line when the unit bit appears at inputs.

EFFECT: increasing carrying capacity of communication channel.

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Description

The invention relates to techniques for field geophysical research of wells, in particular to seismic acoustic methods.

The creation of modern equipment modifications for seismic-acoustic methods for researching wells is constrained by the inadequate speed of digital data transmission via wireline cable. Part of the problem is solved by the use of multilevel coding digital modems in downhole tools used in HDSL technologies for transmitting data over telephone lines. But this limits the thermal stability of the downhole equipment. As the depths of research increase, the need for high bit rate is supplemented by the requirement of heat resistance, which raises the question of efficient and simple digital signal conditioners for wireline logging.

A known method of forming a balanced five-level signal in a line, implemented in a converter, in which, based on an analysis of eight bits of input data and the magnitude of the current unbalance in the output signal, according to certain rules, the input data is replaced by balancing combinations (V.A. Shuvalov, ed. St. No. 651491, publ. 08.03.79, bull. No. 9). Replacement is made so that the current amount of imbalance of the output data does not go beyond certain boundaries, and the balancing combination in the receiver is again correctly converted to the original data.

As you can see, a large number of bits are involved in the formation of the output pulse of the converter, which is a drawback, since it can lead to the propagation of errors in the inverse data conversion.

In addition, in the spectrum of the output signal of the converter there is an explicit component at the clock frequency FТ, which is generated by code combinations in the communication channel, consisting of two or three pulses of the same polarity located at adjacent clock intervals. It follows that for the correct selection of such code combinations at the receiving side, an unreasonably wide band of the communication channel will be required.

There is also known a method of converting a binary signal into a three-level balanced signal (AMI code) and a device for its implementation, described in the digital data transmission method, in which the input zero bits are transmitted to the line as zero, and the single bits are transmitted alternately as pulses of positive and negative polarity ( RHBarker, Jan. 25, 1955, U.S. Patent No. 2,700,696). The practical converter circuit for implementing this method contains a counting trigger, which is connected with two outputs to the coincidence circuit (multiplexer), the outputs of which are connected to the inputs of the output signal shaper, which consists of two output circuits that form positive and negative pulses at the common load (Catermole K. B. Principles of pulse-code modulation. Translation from English under the editorship of VV Markov. M., “Communication”, 1974, pp. 344, 345).

The advantages of the AMI code include the simplicity of the encoder and the advantageous shape of the spectrum of its linear signal, where the main energy is concentrated near the half-cycle frequency Ft / 2. Due to this, the AMI code is widely used in backbone digital data transmission systems. The insufficient synchronizing ability of the code with a long zero signal is quite simply increased by adding additional pulses to the linear signal (HDBn codes). Another more important drawback of the AMI code is its low bit rate, close to 2 bits / Hz.

The purpose of the proposed conversion method is to increase the throughput of the communication channel.

This goal is achieved by the fact that in the method of converting a binary signal into a five-level signal, including alternating the polarity of the pulses in the line, the input data is delayed by one bit interval in the delay trigger and, depending on the value of the current bit and the predetermined polarity, are sent to one of the four inputs of the five-level of the output signal conditioner, conventionally designated as +1, +2, -1, -2, which, when a single pulse appears at its inputs, gives the same pulse to the line, and the value zero of the current bit corresponds to a single value of the pulse amplitude in the line, and a value of one is doubled or vice versa, the remaining input zero bits are transmitted to the line as zero, while the delay trigger is brought to a single state on the current clock cycle causes it to go to zero no later than the end time next measure.

Figure 1 shows a functional diagram of the device, figure 2 - timing diagrams of operation, figure 3 - modified timing diagrams.

Conversion of a binary signal into a five-level signal is performed according to the following rules:

1. The polarity of the first pulse in the line is set arbitrarily, and the polarity of subsequent pulses in the line is alternately reversed. This rule is considered known.

2. The data bits must be transmitted with values of 10, 11, and the detection of the first single bit in the specified bits initiates the sending of a pulse to the line.

3. The amplitude of the pulse in the line, depending on the value of the 2nd bit, takes two values, which are correlated as 1: 2. The zero value of the second bit in the indicated bits can correspond to a small value of the pulse amplitude in the line, and to a larger one, a large one. The remaining input zero bits are transmitted to the line as zero

The voltage at the converter output, taking into account rule 1, can take 5 values: +1, +2, 0, -1, -2.

In one embodiment, the binary signal to five-level signal converter comprises an AND 1 circuit, a delay trigger 2, a counting trigger 3, a multiplexer 4, an output signal shaper 5.

The inputs of the Converter receive clock pulses (Fig.2A) and a bit sequence (Fig.2B).

Input data with the value “one” can go to the D-input of the delay trigger 2 only at a positive (allowing for the circuit AND 1) voltage level at the inverse output of the delay trigger 2, that is, when its state is zero. This state of the trigger can be called the source. Delay trigger 2 is in standby mode until a combination of 10 or 11 appears in the input data stream. At the moment of fixing the first (from a bit) unit bit, the trigger state changes to the opposite.

Transferring the trigger of delay 2 to a single state (current beat) closes the AND 1 circuit at the beginning of the current beat, as a result, the trigger level will be kept at the zero level (D-input), but its state will remain unchanged until the end of the current beat (unit). At the beginning of the next clock cycle, the input of the delay trigger 2 remains in the zero state, therefore, at the next clock cycle, the delay trigger 2 will be set to the "zero" state. From this moment, the And 1 circuit reopens.

As a result of the joint operation of the circuit I 1 and the delay trigger 2, the appearance of the desired combination (10, 11) in the input data stream (Fig.2b) is accompanied by the formation of a single pulse at the output of the delay trigger 2 (Fig.2c).

From the output of the delay trigger 2 pulses (Fig.2c) are fed to the C-input (input) of the counting trigger 3 and to the data input (input) of the multiplexer 4. The output signal of the counting trigger 3 (Fig.2d) is supplied to the senior (second) address input multiplexer 4. The youngest (first) address input of the multiplexer 4 is under the control of input data (figb). Under the influence of these address signals, the data from the input of the multiplexer 4 is fed to one of its four outputs. For definiteness, we assume that the single state of the counting trigger 3 assumes the formation of a negative pulse in the line at the output of the converter, and a zero - positive. Based on the foregoing, and taking into account rule No. 3, we denote the outputs of multiplexer 4 by the values: +1, +2, -1, -2, bearing in mind the fact that the appearance of a single value at one of the outputs of multiplexer 4 involves sending the same voltage to the line . In this case, the driver of the output signal 5 can be performed on four keys with normally open contacts. In the presence of a positive pulse at one of the inputs of the shaper 5, the key corresponding to this input is closed and the supply voltage corresponding to this key is sent to the line. As a result, a pulse signal is generated in the line, shown in Fig.2d, containing five voltage levels: + 1V, + 2V, 0, -1V, -2V.

In known five-level converters, the interval (T) between adjacent pulses in a line (clock interval) is usually a multiple of twice the bit interval of the input data. In the proposed converter, the interval between adjacent pulses will be a multiple of a single bit interval, and the minimum clock interval (Tmin) is equal to twice the bit interval. On the diagram (fig.2d) the interval Tmin is observed between the third and fourth pulses. Given these features, the gating of the signal on the receiving side must be performed at a frequency of F = 2 / Tmin, that is, twice as often as usual.

On the receiving side, from the signal (FIG. 2e), the frequency F can be extracted and a signal (delay not shown) generated, similar to the signal shown in FIG. 2e. To decode the indicated signal (Fig. 2e), a pulse with a small amplitude should be matched with a bit of 0 0, and a pulse with a large amplitude should be assigned a bit of 11, as shown in Fig. A comparison between the original signal (fig.2b) and the decoded signal (fig.2zh) shows their identity.

In other embodiments of the converter, the multiplexer 4 can be performed on separate logic elements or can be replaced with a corresponding decoder. The output signal shaper 5, in turn, can be performed on controlled current sources in the form of an analog subtraction circuit or on four single-vibrators that respond to the pulse front of the delay trigger and issue a pulse with the desired parameters to the line. In this case, the duration of the output pulse of the one-shot, regardless of the duration of the pulse of the delay trigger 2, can be a fraction of the doubled value of the bit interval. The duration of the delay trigger pulse 2 can be selected within the bit interval.

Such solutions allow you to build a variety of, for example analog, circuit reset reset trigger delay 2 to zero.

For the normal operation of the proposed converter, it is important to prevent the appearance of a false edge in the output signal of the delay trigger 2 at the boundary between the current and next bit intervals. At the same time, it is necessary to create conditions (to limit the duration of the “reset” pulse) for the delay edge 2 to appear in the output signal of the trigger trigger at the end of the next bit interval. In the given converter, the “pulse reset” as such is absent and the correct operation of the delay trigger 2 is ensured by switching the input signal of the delay trigger 2 using circuit I 1. This is only the preferred option that does not deserve special mention in the formula.

In the considered converter (Fig. 1) at the address inputs of the multiplexer, a frequent change of signal levels at the boundaries of bit intervals is permissible. For this reason, the single state of the delay trigger should not be kept outside the current clock cycle, so as not to cause a false appearance of a single signal at another output of the multiplexer. Therefore, for the correct operation of this converter (Fig. 1), the translation of the delay trigger from a single state to a zero state must be performed no later than the start of the next clock cycle.

We show that this restriction is too strict and there are simple circuit solutions that allow a wider interpretation of the conditions for the implementation of the proposed method.

Let the previous data arrive at the inputs of such a converter: clock pulses (figa) and a bit sequence (fig.3b). The delay trigger signal (FIG. 3c) is obtained in any manner previously indicated from the input data (FIG. 3b). The signal depicted in FIG. 3g is obtained from the signal (FIG. 3c) by delaying it by a 0.5 bit interval. The value of the current bit in the input data displays the signal (fig.3d). It is obtained by reading the input bits (Fig.3b) at time points corresponding to the edges of the signal (Fig.3g). Alternately changing the polarity of the output signal of the Converter is performed using the signal (Fig.3E). The signal (Fig.3e) is, as before, the result of dividing into two signals (Fig.3g) using a counting trigger. If the signal (Fig. 3d) and the signal (Fig. 3f) are fed to the address inputs of the multiplexer 4, and the signal shown in (Fig. 3d) is input to the multiplexer data input, the previously known linear signal will be generated at the output of the shaper 5 (Fig. 3g) )

This example (Fig. 3) shows that a small change in the converter circuit (Fig. 1) - it boiled down to adding two D-flip-flops - does not change the essence of its operation, but it allows almost double the duration of a single state of the delay trigger (Fig. 3c). On the example of one pulse, a similar situation is shown by a dashed line in the diagrams (Fig.3c), (Fig.3d), (Fig.3g).

This implies a broader interpretation of the conditions for the implementation of the proposed method: "the translation of the delay trigger from a single state to a zero state must be performed no later than the end of the next clock cycle."

In its appearance, the output signal of the converter is close to the signal in the AMI code and in many respects preserves its positive qualities: high synchronizing ability, compact spectrum, which implies moderate demand for channel correction quality, simplicity of circuit implementation. The polarity of the pulses in the line changes alternately, which is an important advantage compared to the known five-level converters, where pulses with the same polarity are allowed at adjacent positions of the signal in the line. Such unwanted pulse combinations expand the spectrum of the signal in the low and high frequencies. This makes it difficult to correct it in the receiver. As practice shows, reliable data reception in such conditions, in addition to difficulties with correction, is ensured by the price of expanding the channel band by 25% towards higher frequencies.

The signal at the output of the proposed converter is almost balanced. The maximum level of unbalance occurs when repeating the input combination 1110. This does not cause reception failures, but can reduce the length of the communication line. With seismic-acoustic methods for exploring wells, the signals from the sensors are similar to a zero-mean speech signal. Under these conditions, the signal imbalance in the line is minimal, the reception quality does not decrease, and scrambling of the input data is not required.

Alternate change in the polarity of the pulses in a linear signal suggests its good synchronizing ability with a high density of units at the input of the converter. But a long zero at the input leads to a synchronization failure. As in the AMI code, this drawback is eliminated by adding additional pulses to the converter output signal that violate the rule of alternating pulse polarity at the output, similar to what is usually done in codes with a “high unit density”.

When testing the converter on a three-wire log cable with a length of 5.3 km, the data transfer rate was 800K baud. That is approximately two times higher than in the HDB3 code. In both cases, an analog corrector was used to restore the signal.

The five-level converter circuit is quite simple. Therefore, its thermal stability in comparison with the HDB3 encoder has remained unchanged. It exceeds 150 ° C and, as before, is limited by the heat resistance of the output shaper.

Claims (1)

A method of converting a binary signal into a five-level signal, in which zero in the input data is bit-wise transmitted to the line as zero, which alternately changes the polarity of the pulses in the line using the output signal of the counting trigger, addressing the bits to one or another input of the output signal shaper, characterized in that when entering the input data, combinations 10 or 11 delay the first single bit in the delay trigger and reset it no later than the end of the next clock cycle, the delayed bit is fed to the input of the counting three and addressing the value of the output signal of the counting trigger and the value of the second bit of the combination, send the delayed bit to one of the four inputs of the five-level output driver, which, when a single bit appears at the inputs, sends pulses to the line, and a value of zero of the second bit of the combination corresponds to a single amplitude value pulse in the line, and the value of one is doubled, or vice versa.

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