JP2012023638A - Digital communication system and receiving device used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital communication system with high transmission efficiency and a receiving device used therefor making it possible to perform stable clock reproduction with a conventional simple clock reproduction circuit and be constructed by a low speed semiconductor device having high reliability and excellence in terms of cost.SOLUTION: A digital communication system performs clock reproduction from a data signal 50. The data signal 50 is a multiple value data signal having a plurality of signal (voltage) levels corresponding to codes and one reference (voltage) level set outside the range of a plurality of the signal levels, has voltage values of the signal voltage levels corresponding to the codes and the reference level during a period T, and has a reference recovery signal waveform of which transition (edge) is at the middle point of the period T. A clock reproduction circuit 10 in a receiving device 50R has one determination (voltage) level set for detecting the edge between the reference level and an signal level adjacent to the reference level.

Description

  The present invention relates to a digital communication system that extracts timing information from a received data signal and regenerates a clock, and a receiving apparatus used therefor.

  In order to transmit / receive a digital signal, it is necessary to determine each data bit at a correct timing on the receiving side. Therefore, a clock signal line for transmitting timing information (clock) is provided in parallel with the data signal line for transmitting data. There are many cases. On the other hand, in a signal from a read head such as an optical disk or recent high-speed serial transmission, timing information is superimposed on a data signal and transmitted without providing a clock signal line. In such a digital communication system without a clock signal line, an edge (signal transition) is detected from the waveform of the received data signal, and the phase of the internal reference clock is adjusted by the edge, thereby obtaining timing information (clock). Reproduce. As described above, in a digital communication system without a clock signal line, a clock recovery technique is important in order to recover a clock from a waveform of a data signal to obtain accurate received data.

  Further, in recent in-vehicle digital communication systems, not only the clock signal line is eliminated, but the digital communication system having a high bit transmission rate and high transmission efficiency as the function of the system mounted on the vehicle increases. Is becoming necessary. On the other hand, in a vehicle-mounted digital communication system, it is preferable not to use a high-speed semiconductor device in terms of reliability and cost as a semiconductor device constituting the system, and a digital communication system with the above high transmission efficiency is constructed with a low-speed semiconductor device. It is requested to do.

  As means for realizing high-efficiency digital communication with a low-speed semiconductor device, for example, Japanese Patent Application Laid-Open No. 5-236043 (Patent Document 1), Japanese Patent Application Laid-Open No. 8-237239 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2008-17413. A digital communication system using a multi-level transmission code as disclosed in the publication (Patent Document 3) is conceivable.

JP-A-5-236043 JP-A-8-237239 JP 2008-17413 A

  In a digital communication system without a clock signal line, in order to correctly perform clock recovery (CDR), edges need to appear frequently in a data signal. Otherwise, due to the drift of the internal reference clock on the receiving side, jitter increases in the recovered clock or synchronization is lost.

  11A and 11B are diagrams for explaining the above problem. FIG. 11A is a diagram showing a waveform of a general binary data signal 91 and an example of encoding, and FIG. 11B is a diagram showing binary phase displacement modulation (BPSK). It is the figure which showed the waveform and encoding example of the data signal 90 of.

In the general binary data signal 91 shown in FIG. 11A, 1-bit data can be transmitted with one code of the period T ₀ , and the baud rate is B ₀ = 1 / T _0, which is the same as the baud rate 1B. Data can be transmitted at a bit transmission rate of _zero . However, in the data signal 91 that takes a binary value of “1” and “0”, for example, when “1” of the same sign continues, an edge does not appear in the waveform between them, so synchronization is lost and clock reproduction cannot be performed. . Therefore, when transmitting the data signal 91 of FIG. 11A, it is necessary to separately provide a clock signal line and transmit the clock signal.

On the other hand, in the BPSK data signal 90 shown in FIG. 11B, data is encoded as shown in the table in the figure so that an edge always appears in one code. That is, in the BPSK data signal 90, binary data “1” and “0” are encoded so that a transition (edge) of the signal (voltage) level always occurs at the midpoint of one code period T _1. Has been. As described above, in the BPSK data signal 90, for example, even when “1” of the same sign continues, an edge is steadily included in the waveform between them and synchronization is not lost. Stable clock recovery is possible. In the BPSK data signal 90 shown in FIG. 11B, 1-bit data can be transmitted with one code of the cycle T ₁ = 2T ₀ . Thus, the baud rate is _B 1 = at 1 / _{T 1,} it is possible to transmit data at 11 1/2 bit of the data signal waveform shown in (a) transmission speed _1B 1 _{= B} 0/2.

  12A and 12B are diagrams for explaining clock recovery using the BPSK in FIG. 11B as an example. FIG. 12A is a block diagram showing a front end of the receiving device 90R, and FIG. 2 is a block diagram showing a configuration example of a clock recovery circuit 10 in FIG. FIG. 6C is a time chart illustrating the correspondence between the BPSK data signal 90 and the reproduction clock 20.

  In the receiving device 90R of FIG. 12A, the data signal 90 input from the terminal (RX) is branched at the node N1 and transmitted to the clock recovery circuit 10 and the latch circuit 30, respectively. In the clock recovery circuit 10, the recovery clock 20 is generated from the data signal 90. In the latch circuit 30, the data signal 90 is latched by the recovered clock 20 generated by the clock recovery circuit 10, and the received data is read at the correct timing.

The clock recovery circuit 10 in FIG. 12B includes a phase comparison circuit 1, a loop filter 2 and a voltage controlled oscillator 3. A data signal 90 that is an input signal of the clock recovery circuit 10 is input to the phase comparison circuit 1. The phase comparison circuit 1 utilizes the crossing of the determination level indicated by the alternate long and short dash line when the voltage level from the first half to the second half in one symbol of the data signal 90 shown in FIG. And a phase comparison signal 6 corresponding to the phase difference between the reproduction clock 20 and the loop clock 2. Here, the phase comparison signal 6 is band-limited by the loop filter 2 and input to the voltage controlled transmitter 3. In accordance with this input signal, the voltage control oscillator 3 controls the phase and frequency (f ₀ = 1 / T ₀ ) of the reproduced clock 20 to be output, and synchronizes the data signal 90 and the reproduced clock 20. As described above, as indicated by the long downward broken arrow in FIG. 12C, the accurate reproduction clock 20 having the frequency f ₀ synchronized with the data signal 90 is generated from the data signal 90.

Next, in the latch circuit 30 of FIG. 12A, the data signal 90 is latched by the recovered clock 20 of FIG. 12C generated by the clock recovery circuit 10. Then, as indicated by a short upward broken arrow in FIG. 12C, the voltage levels of the first half and the second half in one code of the data signal 90 are sampled at the rising edge of the reproduction clock 20 of the frequency f ₀ , and the voltage level The received data is read out by decoding the data into the codes in the table in FIG.

  On the other hand, a digital communication system using a multi-level transmission code is considered to be a means that can realize high-speed communication with a low-speed semiconductor device as described above. There are the following problems.

  FIG. 13 is a diagram for explaining the problem of clock recovery in a digital communication system using a multilevel transmission code. FIG. 13A shows a waveform of a general multilevel (four-level) data signal 92 and an example of encoding. (B) is a diagram in the case where a plurality of edge detection determination levels are provided for the same waveform of the data signal 92 as in (a).

In the general quaternary data signal 92 shown in FIG. 13A, 2-bit data can be transmitted with one code of the period T ₀ . Therefore, the baud rate is B ₀ = 1 / T ₀ which is the same as the binary data signal 91 shown in FIG. 11A, and data can be transmitted at a bit transmission rate of 2B _{0 which} is double. However, if, for example, the conventional clock recovery circuit 10 shown in FIG. 12 (b) is used to recover the clock from the data signal 92 of FIG. 13 (a), the waveform of the data signal 92 has a signal level above the determination level. When (1.25 V or more) continues, no edge appears, and clock regeneration cannot be performed during that time.

  In order to solve the above problem, in the digital communication system using the conventional multilevel transmission code as disclosed in Patent Documents 1 to 3, a plurality of edge detection determination levels are provided as shown in FIG. The edge detection frequency is increased by dynamically changing the determination level. However, when a plurality of edge detection determination levels are used as described above, the conventional clock recovery circuit 10 illustrated in FIG. 12B cannot be used, and a more complicated and large-scale clock recovery circuit is required. I need it.

Incidentally, as a means for increasing the bit transmission rate without using a multi-level transmission code, the two-phase displacement modulation (BPSK) shown in FIGS. 11B and 12C has been developed, and the four-phase displacement modulation (QPSK). As described above, there is a method of further dividing the phase displacement and increasing the number of bits allocated to one code of the same period T ₁ . However, in this method, it is necessary to sample data from the received waveform for each divided phase, and the frequency of the recovered clock also increases in proportion to the number of divided phases. For this reason, it is not possible to use a low-speed semiconductor device that is excellent in reliability and cost in a sampling circuit for a received data signal.

  Therefore, the present invention provides a digital communication system that extracts timing information from a received data signal and regenerates a clock, and a receiving apparatus used therefor, which can stably reproduce a clock with a conventional simple clock recovery circuit, and is reliable. Another object of the present invention is to provide a high-efficiency digital communication system that can be constructed with a low-speed semiconductor device that is excellent in cost and a receiver used therefor.

According to the first aspect of the present invention, the transmission device and the reception device are connected by a data signal line having no clock signal line, and timing information is obtained from a data signal received by the reception device via the data signal line. extracting and a digital communication system for clock recovery, the data signal, with a period of one code is T _1, would have a baud rate of 1 / T _1, a plurality of signal voltage level corresponding to the code And a multi-value data signal having one reference voltage level set outside the range of the plurality of signal voltage levels, and the signal voltage level corresponding to the code during the code period T ₁ the take voltage value of the reference voltage level, the transition of the signal voltage level and a reference voltage level (edge) is a reference return signal waveform that is present at the midpoint of the period T _1, clock of the receiving device In the reproduction circuit, a determination voltage level for detecting the edge is provided between the reference voltage level and the signal voltage level adjacent to the reference voltage level. It is characterized by detecting an edge and performing clock recovery.

  The digital communication system is a digital communication system without a clock signal line that transmits timing information superimposed on a data signal, extracts timing information from the received data signal, and regenerates a clock. The data signal used in the digital communication system is a multi-value data signal having a plurality of signal voltage levels corresponding to codes. That is, the above digital communication system is a digital communication system using a multi-level transmission code, is a digital communication system having a high bit transmission rate and high transmission efficiency, and is a low-speed semiconductor device excellent in reliability and cost. It is also a digital communication system that can be built with.

  On the other hand, in the conventional digital communication system using the multilevel transmission code, there is the following problem when the clock signal line is eliminated and the clock is reproduced. That is, when clock recovery is performed from a data signal having a conventional multilevel transmission code, in a clock recovery circuit having a single determination (voltage) level, transition (edge) occurs in a region where a signal (voltage) level above the determination level continues. ) Does not appear, so the clock cannot be played back. In addition, in order to solve the above problem, when the edge detection frequency is increased by using a plurality of edge detection determination levels or by dynamically changing the determination level, a simple simple clock reproduction with a single determination level is performed. Circuits cannot be used, requiring more complex and large scale clock recovery circuits.

The digital communication system employs a new waveform of a data signal called “reference return signal waveform” in order to solve the problem of clock recovery in a digital communication system using a conventional multilevel transmission code. That is, the data signal in the digital communication system has a baud rate of 1 / T ₁ with a period of one code T ₁ and a plurality of signal voltage levels corresponding to the code and a range of the plurality of signal voltage levels. A multi-value data signal having one reference voltage level set outside, and taking the signal voltage level corresponding to the code and the voltage value of the reference voltage level during the code period T ₁ , The transition (edge) between the voltage level and the reference voltage level has a “reference return signal waveform” present at the midpoint of the cycle T ₁ . In other words, the data signal having a "reference return signal waveform" is one takes each signal voltage level and the reference voltage level half or the second half of the period T ₁ of the code, the signal voltage at the midpoint of the period T ₁ of the code A transition (edge) between the level and the reference voltage level occurs. For this reason, in the digital communication system described above, a multilevel signal voltage level can be obtained by setting only one determination voltage level between a reference voltage level and a signal voltage level adjacent to the reference voltage level in the clock recovery circuit of the receiver. An edge can always be detected from the data signal having the following values every period T ₁ of one code. Therefore, the above digital communication system is a digital communication system having a high transmission efficiency using a multi-level transmission code, and a conventional simple clock recovery circuit having a single determination level, which increases jitter from the waveform of the data signal. Accurate clock recovery without being lost or out of sync is possible.

  As described above, the digital communication system is a digital communication system that extracts the timing information from the received data signal and regenerates the clock, and stable clock recovery is possible with a conventional simple clock recovery circuit. A digital communication system with high transmission efficiency that can be constructed with a low-speed semiconductor device excellent in reliability and cost can be obtained.

  The reference voltage level in the digital communication system is preferably a ground potential having a stable potential as described in claim 2. However, the present invention is not limited to this, and the reference voltage level may be, for example, a power supply potential of the receiving device as described in claim 3.

The digital communication system, for example as described in claim 4, the signal voltage level corresponding to the code is comprised half or set to one of the second half than the midpoint of the period T _1, the reference voltage The level may be set to the other half of the first half or the second half opposite to the signal voltage level.

Further, as described in claim 5, wherein the signal by combining the voltage level with the reference voltage level, the signal voltage level and said set in either the first half or the second half than the midpoint of the cycle T ₁ The sign may be configured by the reference voltage level set in the other half of the first half or the second half opposite to the signal voltage level.

  In the configuration described in claim 4, the reference voltage level set outside the range of the plurality of signal voltage levels is used only for generating an edge, and each of the plurality of signal voltage levels corresponds to each code. It has a configuration. On the other hand, in the configuration described in claim 5, each code is configured by combining a plurality of signal voltage levels and a reference voltage level. For this reason, the structure of Claim 5 can be made to respond | correspond to more codes | symbols even if it is the number of the same signal voltage level compared with the structure of Claim 4. For example, when the number of signal voltage levels is 4, in the configuration according to claim 4, 2-bit information can be assigned to one code, whereas in the configuration according to claim 5, one code is assigned to one code. 3-bit information can be assigned. For this reason, the configuration according to claim 5 has twice the transmission efficiency as compared with the configuration according to claim 4.

For example, the digital communication system may be configured to regenerate a clock having a frequency f ₀ = 2 / T ₁ from the multi-value data signal.

According to a seventh aspect of the present invention, a clock having a frequency f ₁ = 1 / T ₁ can be reproduced from the multilevel data signal.

In the configuration described in claim 6, for example, the signal voltage level and the reference voltage level set in the first half or the second half of the data signal can be sampled at the rising edge of the reproduction clock having the frequency f ₀ = 2 / T _1. it can. On the other hand, in the configuration according to claim 7, by setting a predetermined phase delay to the reproduction clock generated at the frequency f ₁ = 1 / T ₁ , for example, the first half or the second half of the data signal is set at the rising edge of the reproduction clock. It is possible to sample the signal voltage level and the reference voltage level. According to the configuration described in claim 7, the frequency of the recovered clock can be reduced to ½ that of the configuration described in claim 6, and the circuit configuration of the low-speed semiconductor device excellent in reliability and cost can be easily achieved. Become.

  As described above, the digital communication system is a digital communication system that extracts the timing information from the received data signal and regenerates the clock, and stable clock recovery is possible with a conventional simple clock recovery circuit. A digital communication system with high transmission efficiency that can be constructed with a low-speed semiconductor device excellent in reliability and cost can be obtained.

  Therefore, as described in claim 8, the digital communication system not only eliminates the clock signal line but also requires a high transmission efficiency with a high bit transmission rate as the function of the system mounted on the vehicle increases. In addition, it is suitable for a vehicle-mounted digital communication system that requires the use of a low-speed semiconductor device that is excellent in reliability and cost as a semiconductor device constituting the system.

  The invention described in claims 9 to 16 is an invention of a receiving apparatus used in the digital communication system described above.

The invention according to claim 9 is a receiving device having a clock recovery circuit that extracts timing information from a data signal received via a data signal line and recovers the clock, wherein the data signal is a single signal. The cycle of the code is T ₁ and has a baud rate of 1 / T ₁ , and a plurality of signal voltage levels corresponding to the code and one reference voltage level set outside the range of the plurality of signal voltage levels A multi-value data signal having a voltage value of the signal voltage level and the reference voltage level corresponding to the code during a period T ₁ of the code, and a transition between the signal voltage level and the reference voltage level; It becomes a reference return signal waveform (edge) exists in the middle of the period T _1, in the clock recovery circuit, the signal voltage level adjacent to the reference voltage level and the reference voltage level In the meantime, one determination voltage level for detecting the edge is provided, and the edge is detected from the multi-value data signal, and the clock is reproduced.

  The effect obtained by the receiving apparatus is the same as that of the digital communication system described in claim 1, and the description thereof is omitted.

  The effects obtained by the receiving apparatus according to claims 10 to 16 are the same as the effects of the digital communication system described in claims 2 to 8 respectively corresponding thereto.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the outline | summary of the digital communication system which concerns on this invention, and the receiver used for it, (a) is the figure which showed an example of the transmitter 50T used for the digital communication system 50S, (b) is digital communication. It is the figure which showed an example of the receiver 50R used for the system 50S. FIG. 2 is a diagram for explaining details of a data signal 50 used in the digital communication system 50S of FIG. 1, and (a) shows a waveform of the data signal 50 and an example of encoding. Further, (b) is a diagram showing a waveform and an example of encoding of the reference data signal 93, although it is not a data signal used in the digital communication system of the present invention. FIG. 3 is a diagram for explaining clock recovery from the data signal 50 shown in FIG. 1 and FIG. 2 (a), (a) is a block diagram showing a front end of the receiving device 50R, and (b) is a data signal. 5 is a time chart illustrating the correspondence between 50 and the reproduction clock 20; FIG. 10 is a diagram showing another multi-value reference return data signal having a different number of signal voltage levels from the multi-value reference return data signal 50, and (a) shows the waveform of the multi-value reference return data signal 50 a having 16 signal voltage levels. It is the figure which showed the example of encoding, (b) is the figure which showed the waveform and encoding example of the multi-level reference return data signal 50b which has two signal voltage levels. It is a figure which shows another multi-value reference return data signal in which a reference voltage level differs from the multi-value reference return data signal 50, and is the figure which showed the waveform and encoding example of the multi-value reference return data signal 50c. 2A is a diagram illustrating another receiving device that receives the multilevel reference return data signal 50 of FIG. 2A, FIG. 2A is a block diagram illustrating a front end of the receiving device 51R, and FIG. 3 is a time chart illustrating the correspondence between a reproduction clock 21a and a clock 21b reproduced from a data signal 50. It is a figure which shows another multi-value reference return data signal different from the multi-value reference return data signal 50, and is a figure which shows the waveform and encoding example of the multi-value reference return data signal 60. FIG. 8A is a block diagram showing a front end of the receiving device 60R, and FIG. 8B is a block diagram showing a multilevel reference return data signal 60 shown in FIG. 6 is a time chart illustrating the correspondence between 60 and the reproduction clock 20; FIG. 8 is a diagram illustrating another receiving device that receives the multilevel reference return data signal 60 of FIG. 7, (a) is a block diagram illustrating a front end of the receiving device 61 </ b> R, and (b) is a data signal 60. 6 is a time chart illustrating the correspondence between the reproduction clock 21a and the clocks 21b and 21c. FIG. 9 is a diagram illustrating another receiving device that receives the multilevel reference return data signal 60 of FIG. 7, in which FIG. 7A is a block diagram illustrating a front end of the receiving device 62 </ b> R, and FIG. 6 is a time chart illustrating the correspondence between the reproduction clock 21a and the clock 21b. (A) is the figure which showed the waveform and encoding example of the binary general data signal 91, (b) showed the waveform and encoding example of the data signal 90 of 2 phase displacement modulation (BPSK). FIG. FIGS. 11A and 11B are diagrams illustrating clock regeneration using the BPSK in FIG. 11B as an example, where FIG. 11A is a block diagram showing a front end of the receiving device 90R, and FIG. 11B is a clock regeneration in FIG. 2 is a block diagram illustrating a configuration example of a circuit 10. FIG. FIG. 6C is a time chart illustrating the correspondence between the BPSK data signal 90 and the reproduction clock 20. It is a figure explaining the problem of the clock reproduction | regeneration in a digital communication system using a multi-value transmission code, (a) is the figure which showed the waveform and encoding example of the general data signal 92 of multi-value (four values). (B) is a figure at the time of making the determination level of edge detection into multiple about the waveform of the same data signal 92 as (a).

  The present invention relates to a digital communication system that extracts timing information from a received data signal and regenerates a clock, and a receiving apparatus used therefor. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram for explaining the outline of a digital communication system according to the present invention and a receiving device used therefor. FIG. 1A is a diagram showing an example of a transmitting device 50T used in a digital communication system 50S. These are figures which showed an example of the receiver 50R used for the digital communication system 50S.

  FIG. 2 is a diagram for explaining details of the data signal 50 used in the digital communication system 50S of FIG. 1, and (a) shows a waveform of the data signal 50 and an example of encoding. FIG. 2B is a diagram showing a waveform and an example of encoding of the reference data signal 93, which is not a data signal used in the digital communication system of the present invention.

  3 is a diagram for explaining clock recovery from the data signal 50 shown in FIGS. 1 and 2A. FIG. 3A is a block diagram showing a front end of the receiving device 50R. b) is a time chart illustrating the correspondence between the data signal 50 and the reproduction clock 20;

  In the receiving device 50R shown in FIGS. 1B and 3A, the same reference numerals are given to the same parts as those of the receiving device 90R shown in FIG.

  In a digital communication system 50S shown in FIG. 1, a transmission device 50T and a reception device 50R are connected by a data signal line DL without a clock signal line, and a data signal 50 received by the reception device 50R via the data signal line DL. It is a digital communication system that extracts timing information from a clock and reproduces the clock. The data signal 50 used in the digital communication system 50S is a data signal having a new signal waveform named “multilevel reference return data signal” as will be described in detail later with reference to FIG.

  In the transmission device 50T in the digital communication system 50S of FIG. 1, binary code data that takes a binary value of “1” and “0” with a predetermined number of bits is converted into multi-level code data by the multi-level encoder 42, A clock component generated by the clock generator 41 is inserted into the multi-level encoded data signal and transmitted as a multi-level reference return data signal 50. In the receiving device 50R, the clock recovery circuit 10 generates the recovered clock 20 from the received multilevel reference return data signal 50. In the latch circuit 30, the received data signal 50 is latched by the reproduction clock 20, and the binary decoder 31 converts multi-level code data into binary code data.

As shown in FIG. 2A, the multilevel reference return data signal 50 has a code period of T ₁ and a baud rate of 1 / T ₁ , and has a plurality of signal voltage levels (( In FIG. 2A, four signal levels of 1V, 2V, 3V, and 4V) and one reference voltage level set outside the range of the plurality of signal voltage levels (in FIG. 2A, the ground potential is set). (GND) is a multilevel data signal (a quaternary data signal in FIG. 2A) having a reference level of 0V. In the multilevel reference return data signal 50 illustrated in FIG. 2A, 2-bit binary code data is encoded into quaternary code data, as shown in the table of FIG. Further, the multi-level reference return data signal 50, as shown by the signal waveform of FIG. 2 (a), between the period of the code T _1, takes a voltage value of the signal voltage level and a reference voltage level corresponding to said code A transition (edge) between the signal voltage level and the reference voltage level has a “reference return signal waveform” in which the transition (edge) exists at the midpoint of the period T ₁ . In other words, in the example of the multi-level reference return data signal 50 shown in FIG. 2 (a), corresponding to the binary code of 2 bits in one T ₀ of the first half of the period T ₁ of the code ₍₌ T _1/2) signal level has been granted, and is returned to the reference voltage level in the second half of the T _0. Conversely, as the multilevel reference return data signal, the first half T ₀ in one code period T ₁ is set as a reference voltage level, and a signal level corresponding to a 2-bit binary code is given at the second half T _0. May be.

On the other hand, the data signal 93 shown in FIG. 2B is not a data signal used in the digital communication system 50S of FIG. Data signal 93 in FIG. 2 (b), similarly to the multi-valued reference return data signal 50 in FIG. 2 (a), _T 1/2 = _{T 0} of the first half of the period _{T 1} of the one code, two bits A signal level corresponding to the binary code is given. However, the data signal 93 in FIG. 2B does not have a reference voltage level set outside the range of the four signal voltage levels corresponding to the code, and the latter half T in the cycle T ₁ of one code. in _1/2 = _{T 0,} it is configured to return the signal level 1. Therefore, the data signal 93 in FIG. 2B has no transition (edge) between the signal voltage level and the reference voltage level at the midpoint of the period T ₁ , and the multilevel reference return data signal 50 in FIG. It does not have a “reference return signal waveform”.

  The configuration of the front end of the receiving device 50R shown in FIG. 3A is the same as the configuration of the front end of the conventional receiving device 90R shown in FIG. Therefore, the configuration of the clock recovery circuit 10 in FIG. 3A may be the same as the configuration of the clock recovery circuit 10 illustrated in FIG. In FIG. 3A and FIG. 12A, only the received data signal 50 and data signal 90 are different.

In the clock recovery circuit 10 of the receiving device 50R shown in FIG. 3A, as shown in FIGS. 2A and 3B, the reference voltage level (0V in the figure) and the reference voltage level are adjacent to each other. In order to detect a transition (edge) existing at the midpoint of the above-described code period T ₁ , one determination voltage level indicated by a one-dot chain line is provided between the signal voltage levels (1V in the figure). It has been. As a result, the clock recovery circuit 10 of the receiving device 50R detects the edge from the multilevel reference return data signal 50, which is a multilevel data signal, and has a frequency f ₀ = 1 as indicated by a long downward dashed arrow. A clock 20 with / T ₀ = 2 / T ₁ is generated. Then, as indicated by an upward short broken line arrow, the signal level given to the first half of the multilevel reference return data signal 50 is sampled at every other rising edge of the recovered clock 20 of the frequency f ₀ , The received data is read after being decoded into the codes in the table in the figure corresponding to the signal level.

  As described above, the digital communication system 50 </ b> S illustrated in FIGS. 1 to 3 transmits the clock information superimposed on the data signal 50, extracts the timing information from the received data signal 50, and regenerates the clock signal. A digital communication system without lines. The data signal 50 used in the digital communication system 50S is a multi-value data signal having a plurality of signal voltage levels corresponding to codes. That is, the digital communication system 50S is a digital communication system using a multi-level transmission code, is a digital communication system having a high bit transmission rate and high transmission efficiency, and is a low-speed semiconductor excellent in reliability and cost. It is also a digital communication system that can be built with devices.

  On the other hand, in the conventional digital communication system using the multilevel transmission code, there is the following problem when the clock signal line is eliminated and the clock is reproduced. That is, as described with reference to FIG. 13A, when the clock recovery is performed from the data signal 92 having the conventional multilevel transmission code, the determination (voltage) level is higher than the determination level in one clock recovery circuit 10. Since no transition (edge) appears in the region where the signal (voltage) level continues, the clock cannot be recovered. In order to solve the above problem, as described with reference to FIG. 13B, when the edge detection frequency is increased by using a plurality of edge detection determination levels or dynamically changing the determination levels, The conventional simple clock recovery circuit 10 having a single determination level cannot be used, and a more complicated and large-scale clock recovery circuit is required.

The digital communication system 50S illustrated in FIGS. 1 to 3 is a new data signal 50 called a “reference return signal waveform” in order to solve the above-described clock recovery problem in a digital communication system using a conventional multilevel transmission code. The waveform is adopted. That is, the data signal 50 in the digital communication system 50S has a code period of T ₁ and a baud rate of 1 / T ₁ , and a plurality of signal voltage levels corresponding to the code and the plurality of signal voltage levels. a multi-level data signal having a one reference voltage level set outside the range of, among the period of the code T _1, takes a voltage value of the signal voltage level and a reference voltage level corresponding to said code, The transition (edge) between the signal voltage level and the reference voltage level has a “reference return signal waveform” that exists at the midpoint of the period T ₁ . In other words, the data signal 50 with a "reference return signal waveform" is one takes each signal voltage level and the reference voltage level half or the second half of the period T ₁ of the code, the signal at the midpoint of the period of the code T ₁ A transition (edge) between the voltage level and the reference voltage level occurs. For this reason, in the digital communication system 50S, a multi-value can be obtained simply by setting one determination voltage level between the reference voltage level and the signal voltage level adjacent to the reference voltage level in the clock recovery circuit 10 of the receiving device 50R. An edge can always be detected from the data signal 50 taking the signal voltage level every period T ₁ of one code. Therefore, the digital communication system 50S is a digital communication system having high transmission efficiency using a multi-level transmission code, and is a conventional simple clock recovery circuit 10 having a single determination level. From the waveform of the data signal 50, Accurate clock recovery without increasing jitter or loss of synchronization is possible.

  As described above, the digital communication system 50S is a digital communication system that extracts the timing information from the received data signal and regenerates the clock, and can stably reproduce the clock with a conventional simple clock recovery circuit. Thus, a high-efficiency digital communication system that can be constructed with a low-speed semiconductor device excellent in reliability and cost can be obtained.

  Next, a modified example of the digital communication system 50S and the receiving device 50R used therefor will be described.

  FIG. 4 is a diagram showing another multilevel reference return data signal having a different number of signal voltage levels from the multilevel reference return data signal 50 described above, and FIG. 4A is a multilevel reference return data signal having 16 signal voltage levels. It is the figure which showed the waveform and encoding example of the data signal 50a, (b) is the figure which showed the waveform and encoding example of the multi-level reference return data signal 50b which has two signal voltage levels.

The multilevel reference return data signal 50 shown in FIG. 2A is a data signal having four signal voltage levels and one reference voltage level. Multivalued reference return data signal 50 may be imparted a 2-bit data in one code period T _1. Therefore, the baud rate is B ₁ = 1 / T ₁ (= 1 / 2T ₀ ), and the bit transmission rate (bps) is 2B ₁ . This bit transmission rate is twice the bit transmission rate of BPSK shown in FIG.

On the other hand, multi-valued reference return data signal 50a shown in FIG. 4 (a) is a data signal having a 16 signal voltage level and one reference voltage level, the 4-bit data in one code period T ₁ Can be granted. Therefore, the bit transmission rate (bps) is 4B _1, which is twice the bit transmission rate of the multilevel reference return data signal 50 shown in FIG. 2A, and four times the bit rate of BPSK shown in FIG. Transmission speed. In this way, in a digital communication system using a multilevel reference return data signal, by setting a large number of signal voltage levels, the bit transmission rate can be increased at the same baud rate (and hence the same reproduction clock frequency), A digital communication system having high transmission efficiency can be obtained.

Note that the multilevel reference return data signal may be a data signal having two signal voltage levels and one reference voltage level, like the multilevel reference return data signal 50b shown in FIG. 4B. Multilevel reference return data signal 50b in FIG. 4 (b), the same as the BPSK data signal 90 in FIG. 11 (b), can be imparted to one bit of data in one code period _{T 1.} Therefore, the bit transmission rate is also 1B ₁ which is the same as the data signal 90 of BPSK.

  It should be noted that the multilevel reference return data signals 50a and 50b shown in FIG. 4A and FIG. 4B can be stably regenerated in the same manner as the multilevel reference return data signal 50 shown in FIG. Needless to say.

  FIG. 5 is a diagram showing another multilevel reference return data signal having a reference voltage level different from that of the multilevel reference return data signal 50 described above, and is a diagram showing a waveform and an example of encoding of the multilevel reference return data signal 50c. .

  The multi-level reference return data signal 50 shown in FIG. 2A has one reference voltage level set outside the range of a plurality of signal voltage levels (1V, 2V, 3V, 4V), and the ground potential (GND = GND). 0V). On the other hand, the multi-level reference return data signal 50c shown in FIG. 5 applies one reference voltage level set outside the range of the plurality of signal voltage levels (1V, 2V, 3V, 4V) to the power supply of the receiving device. The potential is set to VDD (5 V).

  Since the ground potential is stable, the ground potential is suitable as the reference voltage level of the multilevel reference return data signal. However, the present invention is not limited to this, and the reference voltage level set outside the range of the plurality of signal voltage levels in the multi-level reference return data signal is the power supply potential of the receiving device as in the multi-level reference return data signal 50c of FIG. It may be.

  FIG. 6 is a diagram illustrating another receiving device that receives the multilevel reference return data signal 50 of FIG. 2A, and FIG. 6A is a block diagram illustrating a front end of the receiving device 51R. b) is a time chart illustrating the correspondence between the reproduction clock 21a and the clock 21b reproduced from the data signal 50; In the receiving device 51R shown in FIG. 6A, the same reference numerals are given to the same parts as those of the receiving device 50R shown in FIG.

The receiving device 50R shown in FIG. 3A has a configuration in which the clock recovery circuit 10 generates the recovered clock 20 having the frequency f ₀ = 1 / T ₀ = 2 / T ₁ from the multilevel data signal 50. Then, the signal voltage level set in the first half of the data signal 50 is sampled at every other rise of the reproduction clock 20 of the frequency f ₀ = 2 / T ₁ . On the other hand, the receiving device 51R shown in FIG. 6A uses the same multi-value data signal 50 as shown by the long dashed arrow pointing downward in FIG. 6B, so that the frequency f ₁ = 1 / T _1. = it is obtained by configured to play the _f 0/2 of the clock 21a.

In the receiving apparatus 51R of FIG. 6 (a), the data signal 50 is transmitted to the clock recovery circuit 11, wherein the frequency _{f 1 = 1 / T 1 =} f 0/2 of the reproduction clock 21a is generated. Thereafter, the phase delay circuit 12a converts the phase into a clock 21b delayed by 90 °. The latch circuit 30a of FIG. 6 (a), the data signal 50 by the clock 21b is latched, as indicated by an upward short dashed arrows in FIG. 6 (b), the rising edge of the clock 21b of the frequency _{f 1,} the data The signal level of the first half in one code of the signal 50 is sampled, decoded into the code of the table in the figure corresponding to the signal level, and the received data is read out.

  FIG. 7 is a diagram showing another multilevel reference return data signal different from the multilevel reference return data signal 50 described above, and is a diagram showing a waveform of the multilevel reference return data signal 60 and an example of encoding.

  FIG. 8 is a diagram showing the receiving device 60R for the multilevel reference return data signal 60 shown in FIG. 7, wherein (a) is a block diagram showing the front end of the receiving device 60R, and (b) 3 is a time chart illustrating the correspondence relationship between a multilevel reference return data signal 60 and a reproduction clock 20; In addition, in the receiving device 60R illustrated in FIG. 8A, the same reference numerals are given to the same portions as those of the receiving device 50R illustrated in FIG.

In the example of the multilevel reference return data signal 50 in FIG. 2A, a signal level corresponding to a 2-bit binary code is given in the first half T ₀ in one code period T ₁ , and the second half T ₀ returned to the reference voltage level.

Similarly to the multilevel reference return data signal 50 shown in FIG. 2A, the multilevel reference return data signal 60 shown in FIG. 7 has four signal voltage levels of 1V, 2V, 3V, and 4V and a ground potential of 0V. It has one reference voltage level. However, the multilevel reference return data signal 60 in FIG. 7 is different from the multilevel reference return data signal 50 in FIG. 2A, as shown in the encoding table in FIG. and by combining the reference voltage level, the reference voltage is set to the other half, or second half half or either one set the signal voltage level and the signal voltage level and reverse late than the midpoint of the period T ₁ Each code is configured with a level.

  As described above, in the configuration of the multilevel reference return data signal 50 shown in FIG. 2A, the reference voltage level set outside the range of the four signal voltage levels is used only for generating an edge. Each of the two signal voltage levels corresponds to each code. On the other hand, in the configuration of the multi-level reference return data signal 60 in FIG. 7, each code is configured by combining four signal voltage levels and the reference voltage level. For this reason, the configuration of the multilevel reference return data signal 60 in FIG. 7 is more than the configuration of the multilevel reference return data signal 50 in FIG. It can correspond to a large number of codes. In other words, even when the number of signal voltage levels is the same four, in the configuration of the multilevel reference return data signal 50 in FIG. 2A, 2-bit information can be assigned to one code. In the configuration of the multilevel reference return data signal 60 of FIG. 7, 3-bit information can be assigned to one code. For this reason, the configuration of the multilevel reference return data signal 60 in FIG. 7 is twice as efficient as the configuration of the multilevel reference return data signal 50 in FIG.

  The configuration of the front end of the receiving device 60R shown in FIG. 8A is the same as that of the receiving device 50R shown in FIG. 3A, and the configuration of the front end of the conventional receiving device 90R shown in FIG. Is the same. Therefore, the configuration of the clock recovery circuit 10 in FIG. 8A may be the same as the configuration of the clock recovery circuit 10 illustrated in FIG. 8 (a), FIG. 3 (a), and FIG. 12 (a) differ only in the received data signal 60 and the data signals 50 and 90, respectively.

In the clock recovery circuit 10 of the receiving device 60R shown in FIG. 8A, as shown in FIGS. 7 and 8B, the reference voltage level (0 V in the figure) and the signal voltage adjacent to the reference voltage level are shown. between level (1V in the figure), in the drawing for detecting a transition present in the middle of the period T ₁ of the code (edge) one determination voltage levels indicated by the one-dot chain line is provided. As a result, the clock recovery circuit 10 of the receiving device 60R detects the edge from the multilevel reference return data signal 60, which is a multilevel data signal, and has a frequency f ₀ = 1 as indicated by a downward long dashed arrow. A clock 20 with / T ₀ = 2 / T ₁ is generated. Then, as indicated by the upward short dashed arrow, the first half voltage level and the second half voltage level of the cycle T ₁ of the multilevel reference return data signal 60 are sampled at each rising edge of the recovered clock 20 having the frequency f _0. The received data is read out by decoding the decoded data into the codes in the table in the figure corresponding to the first half voltage level and the second half voltage level.

  FIG. 9 is a diagram illustrating another receiving device that receives the multilevel reference return data signal 60 of FIG. 7. FIG. 9A is a block diagram illustrating a front end of the receiving device 61R, and FIG. 4 is a time chart illustrating the correspondence between a data signal 60 and a reproduction clock 21a and clocks 21b and 21c. In addition, in the receiving device 61R shown in FIG. 9A, the same reference numerals are given to the same parts as those of the receiving device 51R shown in FIG.

The receiving device 60R shown in FIG. 8A has a configuration in which the clock recovery circuit 10 generates the recovered clock 20 having the frequency f ₀ = 1 / T ₀ = 2 / T ₁ from the multilevel data signal 60. The voltage level and the latter half voltage level of the data signal 60 are sampled at each rising edge of the reproduction clock 20 having the frequency f ₀ = 2 / T ₁ . On the other hand, the receiving device 61R shown in FIG. 9A starts from the same multi-value data signal 60 as shown by a long dashed arrow pointing downward in FIG. 9B, with the frequency f ₁ = 1 / T _1. = it is obtained by configured to play the _f 0/2 of the clock 21a.

In the receiving apparatus 61R in FIG. 9 (a), the data signal 60 is transmitted to the clock recovery circuit 11, wherein the frequency _{f 1 = 1 / T 1 =} f 0/2 of the reproduction clock 21a is generated. The recovered clock 21a is branched at the node N2, and one is converted into a clock 21b whose phase is delayed by 90 ° by the phase delay circuit 12a, and the other is converted into a clock 21c whose phase is delayed by 270 ° by the phase delay circuit 12b. Is done. The latch circuit 30a in FIG. 9 (a), the data signal 60 is latched by the clock 21b, as indicated by an upward short dashed arrows in FIG. 9 (b), the rising edge of the clock 21b of the frequency _{f 1,} the data signal The first half voltage level at one sign of 60 is sampled. Further, the latch circuit 30b of FIG. 9 (a), as indicated by an upward short dashed arrows in FIG. 9 (b), the data signal 60 is latched by a clock 21c, the rising edge of the clock 21c of the frequency _{f 1,} The second half voltage level in one sign of the data signal 60 is sampled. In the combinational circuit 32 of FIG. 9A, the first half voltage level and the second half voltage level in one code sampled as described above are combined and read out as received data at an accurate timing by the latch circuit 30c.

  FIG. 10 is also a diagram showing another receiving device that receives the multi-level reference return data signal 60 of FIG. 7, wherein (a) is a block diagram showing the front end of the receiving device 62R, and (b) 4 is a time chart illustrating the correspondence between a data signal 60 and a reproduction clock 21a and a clock 21b. In addition, in the receiving device 62R shown in FIG. 10A, the same reference numerals are given to the same parts as those of the receiving device 61R shown in FIG.

Similarly to the receiving device 61R shown in FIG. 9A, the receiving device 62R shown in FIG.
As indicated by a downward long dashed arrows in FIG. 10 (b), the one in which the configuration from the multi-level data signal 60 to reproduce the frequency _{f 1 = 1 / T 1 =} f 0/2 of the clock 21a.

In the receiving apparatus 62R in FIG. 10 (a), the data signal 60 is transmitted to the clock recovery circuit 11, wherein the frequency _{f 1 = 1 / T 1 =} f 0/2 of the reproduction clock 21a is generated. The reproduced clock 21a is converted into a clock 21b whose phase is delayed by 90 ° by the phase delay circuit 12a. The latch circuit 30a of FIG. 10 (a), is the data signal 60 by the clock 21b is latched, as indicated by an upward short dashed arrows in FIG. 10 (b), the rising of the clock 21b of the frequency _{f 1,} the data signal The first half voltage level at one sign of 60 is sampled. Further, as shown in FIG. 10A, the clock 21b branched at the node N3 is inverted and inputted to the latch circuit 30d, and the frequency f as shown by the upward short dashed arrow in FIG. 10B. _{At the} falling edge of _one clock 21b, the second half voltage level in one sign of the data signal 60 is sampled. In the combinational circuit 32 of FIG. 10A, the first half voltage level and the second half voltage level in one code sampled as described above are combined and read out as received data at an accurate timing by the latch circuit 30c.

As can be seen from the receiving device 50R in FIG. 3 (a) that receives the multilevel reference return data signal 50 and the receiving device 60R in FIG. 8 (a) that receives the multilevel reference return data signal 60, the digital communication system described above is The clock having the frequency f ₀ = 2 / T ₁ can be reproduced from the multilevel data signals 50 and 60. Also, from the receiving device 51R in FIG. 6A that receives the multilevel reference return data signal 50 and the receiving devices 61R and 62R in FIG. 9A and FIG. 10A that receive the multilevel reference return data signal 60. As can be seen, the digital communication system described above can also be configured to regenerate a clock of frequency f ₁ = 1 / T ₁ from the same multilevel data signals 50, 60.

In the configuration of the receiving device 50R in FIG. 3A and the receiving device 60R in FIG. 8A, for example, the first half or the second half of the data signal is set at the rising edge of the reproduction clock having the frequency f ₀ = 2 / T _1. The current signal voltage level and the reference voltage level can be sampled. On the other hand, in the configuration of the receiving device 51R shown in FIG. 6A and the receiving devices 61R and 62R shown in FIGS. 9A and 10A, the regenerated clock generated at the frequency f ₁ = 1 / T ₁ is predetermined. By applying this phase delay, for example, the signal voltage level and the reference voltage level set in the first half or the second half of the data signal can be sampled at the rising edge of the reproduction clock. According to the later configuration, the frequency of the recovered clock can be halved compared to the previous configuration, and the circuit configuration with a low-speed semiconductor device that is excellent in reliability and cost is facilitated.

  As described above, the digital communication system and the receiving apparatus used therefor are a digital communication system that extracts timing information from a received data signal and recovers the clock, and a receiving apparatus used therefor, which is a conventional simple clock recovery circuit. It is possible to provide a digital communication system with high transmission efficiency that can be constructed with a low-speed semiconductor device that is capable of stable clock recovery and is excellent in reliability and cost, and a receiving apparatus used therefor.

  Therefore, the digital communication system and the receiving apparatus used therefor not only eliminate the clock signal line, but also require high transmission efficiency with a high bit transmission rate as the system mounted on the vehicle becomes more functional. It is suitable as a vehicle-mounted digital communication system and a receiving apparatus used therefor, which require use of a low-speed semiconductor device that is excellent in reliability and cost as a semiconductor device to be configured.

50S digital communication system 50T transmitter 50R, 51R, 60R, 61R, 62R receiver 50, 50a to 50c, 60 (multi-level reference return) data signal 10, 11 clock recovery circuit 20, 21a (regeneration) clock

Claims (16)

The transmission device and the reception device are connected by a data signal line without a clock signal line,
A digital communication system that extracts timing information from a data signal received by the receiving device via the data signal line and regenerates a clock,
The data signal is
A cycle of one code is T ₁ and has a baud rate of 1 / T ₁ , and a plurality of signal voltage levels corresponding to the code and one reference voltage set outside the range of the plurality of signal voltage levels A multi-level data signal having a level,
During the period T ₁ of the code, the signal voltage level corresponding to the code and the voltage value of the reference voltage level are taken, and the transition (edge) between the signal voltage level and the reference voltage level is the midpoint of the period T ₁ A reference return signal waveform existing in
In the clock recovery circuit of the receiver,
A determination voltage level for detecting the edge is provided between the reference voltage level and the signal voltage level adjacent to the reference voltage level.
A digital communication system, wherein the edge is detected from the multi-value data signal and clock recovery is performed.   The digital communication system according to claim 1, wherein the reference voltage level is a ground potential.   The digital communication system according to claim 1, wherein the reference voltage level is a power supply potential of the receiving device. Signal voltage level corresponding to the code, becomes half or set to one of the second half than the midpoint of the period T _1,
The digital communication system according to any one of claims 1 to 3, wherein the reference voltage level is set to the other half of the first half or the second half opposite to the signal voltage level. The signal voltage level and the reference voltage level are combined,
In the reference voltage level set to the other half or the signal voltage level and the signal voltage level and reverse any is set to one of the late first half or the second half than the midpoint of the period T _1,
The digital communication system according to any one of claims 1 to 3, wherein the code is configured. 6. The digital communication system according to claim _{1, wherein} a clock having a frequency of f ₀ = 2 / T ₁ is reproduced from the multilevel data signal. 6. The digital communication system according to claim _{1, wherein} a clock having a frequency of f ₁ = 1 / T ₁ is regenerated from the multilevel data signal.   The digital communication system according to any one of claims 1 to 7, wherein the digital communication system is for in-vehicle use. A receiver having a clock recovery circuit that extracts timing information from a data signal received via a data signal line and recovers the clock,
The data signal is
A cycle of one code is T ₁ and has a baud rate of 1 / T ₁ , and a plurality of signal voltage levels corresponding to the code and one reference voltage set outside the range of the plurality of signal voltage levels A multi-level data signal having a level,
During the period T ₁ of the code, the signal voltage level corresponding to the code and the voltage value of the reference voltage level are taken, and the transition (edge) between the signal voltage level and the reference voltage level is the midpoint of the period T ₁ A reference return signal waveform existing in
In the clock recovery circuit,
A determination voltage level for detecting the edge is provided between the reference voltage level and the signal voltage level adjacent to the reference voltage level.
A receiving apparatus, wherein the edge is detected from the multilevel data signal and clock recovery is performed.   The receiving apparatus according to claim 9, wherein the reference voltage level is a ground potential.   The receiving apparatus according to claim 9, wherein the reference voltage level is a power supply potential. Signal voltage level corresponding to the code, becomes half or set to one of the second half than the midpoint of the period T _1,
12. The receiving apparatus according to claim 9, wherein the reference voltage level is set to the other one of the first half and the second half opposite to the signal voltage level. The signal voltage level and the reference voltage level are combined,
In the reference voltage level set to the other half or the signal voltage level and the signal voltage level and reverse any is set to one of the late first half or the second half than the midpoint of the period T _1,
The receiving apparatus according to claim 9, wherein the code is configured. 14. The receiving apparatus according to claim 9, wherein a clock having a frequency f ₀ = 2 / T ₁ is reproduced from the multilevel data signal. 14. The receiving apparatus according to claim 9, wherein a clock having a frequency f ₁ = 1 / T ₁ is reproduced from the multilevel data signal.   The receiving device according to any one of claims 9 to 15, wherein the receiving device is for vehicle use.

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