RU2427886C2 - Generator of pseudorandom binary sequences - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: device includes shift register consisting of n in-series connected quaternary memory cells, where n - odd number; each of the above cells consists of two binary memory cells, initial setup unit, half adder, square wave generator, which forms the sequences of "zero" and "one" signals, feedback unit performing locic operation of multiplication and summing above the contents of memory cells for formation of feedback signal according to characteristic polynomial, bit synchronisation device, devices providing the storage of coefficients of characteristic polynomial and serving as multipliers when performing multiplying operations in feedback unit.

EFFECT: larger volume of group of pseudorandom binary sequences with the same correlation characteristics as in the prototype.

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Description

The invention relates to the field of radio engineering and can be used in the formation of ensembles of pseudo-random binary sequences used as signatures in the code division of broadband signals in satellite navigation systems, as well as in the code division of channels in broadband telecommunication systems and multi-channel communication systems.

The code separation of signals used in satellite navigation systems consists in the fact that the signals emitted by navigation spacecraft (NSC) are modulated by individual pseudorandom binary periodic sequences (code sequences), allowing the receiver to identify and separate the broadband signals of different NSCs transmitted to single carrier frequency. This allows navigational measurements based on measurements of pseudorange to the corresponding satellite, which consists in determining the delay that occurs during the propagation of broadband signals from the satellite to the receiver. In this case, the methods of correlation processing are used, based on a comparison of code sequences related to the received signals with their local, time-shifted copies formed in the receiver.

Based on the tasks of the receiver to measure the delay and temporal resolution of the received broadband signals, the requirements for the autocorrelation functions (ACF) of the signals and, accordingly, the code sequences modulating them, namely, the ACF should have a fairly sharp central peak and, as low as possible, side lobes . At the same time, the ensemble of code sequences used for code separation of signals should be large enough to satisfy the ever-increasing requirements for the number of shared signals, and the equipment performing encoding and decoding should be as simple as possible based on the requirements of practical implementation.

The simplest known pseudorandom binary sequence generator is a binary m-sequence generator, the implementation of which is described, for example, in the books: [1] - M.D. Venediktov, S.A. Danielyan, V.V. Markov, G.S. Eidus . Multiple access in satellite communication systems. M., Communications, 1973, pp. 81-83, Fig. 6.3, [2] - GLONASS Global Satellite Radio Navigation System. Ed. V.N.Kharisova, A.I. Perov, V.A.Boldin. M., IPRZh, 1998, pp. 64-66, Fig. 5.1, and also in the patents: [3] - SU 375769 A1, G06F 7/58, 01/01/1973, [4] - RU 2223593 C1, H03B 29 / 00, G06F 7/58, 02/10/2004. The considered generator of binary m-sequences is constructed according to the principle of a shift register with linear feedback. The shift register consists of n series-connected binary memory cells (bits), each of which has two possible states. The state of the discharges is transmitted (shifted) to subsequent discharges under the action of clock pulses generated by means of clock synchronization. The initial setting of the bits (register loading) is carried out using the appropriate means of initial loading. Feedback is implemented using the feedback block, which performs logical operations on the contents of the bits of the shift register and transfers the result to the input of the first bit. Logical operations consist in multiplying the output signals of the registers by coefficients (constants) determined by the characteristic polynomial, and their subsequent addition modulo two. In this case, multiplication by one is practically realized as a simple connection of the output of the corresponding register bit to the input of the adder, and multiplication by zero as the absence of a connection. The output signal of the binary m-sequence generator is a binary {0,1} sequence of pulses taken from the output of the last bit of the shift register. This sequence is a linear recurrence sequence of length L = 2 ⁿ -1, which is called the sequence of maximum length or m-sequence.

The characteristic polynomials used in the formation of binary m-sequences are selected from ensembles of primitive polynomials that make up a subclass of irreducible polynomials. Primitive polynomials are known, described in detail and tabulated, see, for example, the book [5] - W. Peterson, E. Weldon. Error correction codes. M., Mir, 1976. For each value of n, there is a certain set of primitive polynomials and, accordingly, an ensemble of binary m-sequences.

Discrete wideband signals based on binary m-sequences, due to the simplicity of formation and processing, are widely used in information systems for measuring time, as training signals, etc. For example, in the 2G mobile communication standard cdmaOne (IS-95) binary m-sequences of various lengths are used as pilot signals for initial synchronization and sounding of channels, as well as codes for multiplexing signals of base stations and scrambling data.

In the case of asynchronous code separation, pseudorandom binary sequences that are more complex in structure and have better cross-correlation characteristics, such as Gold and Kasami sequences, are used.

The general principles for constructing the Gold sequence generator are described, in particular, in the book [6] - V.P. Ipatov. Broadband systems and code division signals. Principles and applications. M., Technosphere, 2007, p. 304-307, Fig. 7.18, and an example of a specific implementation of the Gold sequence generator, designed to generate the C / A code used to separate the satellite signals in the global GPS satellite navigation system, is presented in the book [7 ] - On-board devices of satellite radio navigation. I.V. Kudryavtsev, I.N. Mishchenko, A.I. Volynkin and others. Ed. B.C. Shebshaevich. M., Transport, 1988, pp. 15-16, Fig. 5.

The generalized block diagram of the Gold sequence generator contains the first and second n-bit binary shift registers with linear feedback, a delay unit that implements a delay of k clocks, and an output adder modulo two, the output of which forms the output of the generator. The output of the first shift register with linear feedback is connected to the first input of the output adder modulo two, and the output of the second shift register with linear feedback is connected to its second input through the delay unit.

Each of the shift registers due to the action of the feedback block forms a binary m-sequence corresponding to its characteristic polynomial. The work of shift registers is synchronized by clock pulses generated by clock synchronization. As a result of addition in the output adder modulo two of the first binary m-sequence and shifted by a certain number of clock cycles (k) of the second binary m-sequence, a pseudo-random binary sequence called the Gold sequence is formed. Changing the value of the clock delay k in the delay block, a signature ensemble of Gold sequences is obtained.

(n нечетное) и

(n четное).The ensemble of Gold sequences is characterized, as indicated in [6, p. 312, table 7.1], by the length of the sequences L = 2 ⁿ -1, the volume K = L + 2 = 2 ⁿ +1, and the squares of the maximum correlation

(n odd) and

(n is even).

Gold sequence ensembles are widely used. In addition to the indicated global satellite navigation system GPS, where Gold sequences are used to separate the NKA signals, these sequences are also used in the WCDMA 3G mobile communication system as scrambling CDMA codes (code division multiple access).

According to the construction principle, the Kasami sequence generator adjacent to the Gold sequence generator is described, in particular, in [6, p.307-310, Fig. 7.19, p.215-221], adopted as a prototype.

The block diagram of a sequence generator Kasami contains the first and second shift registers with linear feedback, a delay unit and an output adder modulo two, the output of which forms the output of the generator.

The first linear feedback shift register contains n, where n is an even number of binary memory cells connected in series, each of which has p = 2 possible states, and a feedback block performing logical operations of multiplication and addition modulo two over the contents of the memory cells in according to the first characteristic polynomial and transmitting the result in the form of a binary feedback signal to the input of the first memory cell. This register forms a “long” binary m-sequence. Its output is connected to the first input of the output adder modulo two.

The second linear feedback shift register contains n / 2 sequentially connected binary memory cells, each of which has p = 2 possible states, and a feedback block performing logical operations of multiplication and addition modulo two over the contents of the memory cells in accordance with the second characteristic polynomial and transmitting the result in the form of a binary feedback signal to the input of the first memory cell. This register forms a “short” binary m-sequence. Its output is connected to the second input of the output adder modulo two through a delay block that delays the “short” binary m-sequence by k clocks.

The Kasami sequence generator also contains means for bootstrap memory cells, clock synchronization tools that synchronize the shift operations of the state of the memory cells in each shift register with operations carried out in the feedback blocks and the output adder modulo two, as well as tools for storing characteristic coefficients polynomials serving as factors in the implementation of multiplication operations in feedback blocks.

The principle of constructing feedback blocks in the Kasami sequence generator is the same as in the Gold sequence and binary m-sequence generators discussed above. In accordance with the functions performed, the feedback blocks contain multiplication and addition elements modulo two. In this case, as before, multiplication by one is realized by connecting the adder modulo two with the output of the corresponding shift register cell, and multiplying by zero - by the absence of such. The modulo two addition elements form an addition circuit in each of the feedback blocks, which modulo adds two output signals of the multiplication elements with the formation of the output signal of the feedback block.

The output adder modulo two sums the “long” binary m-sequence coming from the output of the first shift register with linear feedback, with the “short” binary m-sequence coming from the output of the second shift register with linear feedback through the delay block for k measures. As a result of this summation, a pseudo-random binary sequence called the Kasami sequence is formed. By changing the delay delay value k in the delay block, a signature ensemble of Kasami sequences is obtained.

и квадратом максимума корреляции

The Kasami sequence ensemble is characterized, as indicated in [6, p. 312, table 7.1], by the length of the sequences L = 2 ⁿ -1, where n is even, by the volume

and squared correlation maximum

раз) числа сигнатур К.A comparison of the characteristics of the Kasami sequence ensemble with the Gold sequence ensemble of the same length shows a significant gain in the correlation peak ensemble of the Kasami sequence ensemble compared to the ensemble of Gold sequences, which, however, is achieved due to a significantly smaller (approximately

times) the number of signatures K.

The technical problem to which the invention is directed is the development of a pseudo-random binary sequence generator capable of forming a signature ensemble of pseudo-random binary sequences with approximately the same correlation characteristics as in the prototype, but substantially larger.

The invention consists in the following. The pseudo-random binary sequence generator contains a shift register, consisting of n series-connected memory cells, each of which has p possible states, an adder modulo two, connected to the nth memory cell, a feedback unit that performs logical operations of multiplication and addition over the contents of the cells memory for generating, according to the characteristic polynomial, a feedback signal transmitted to the signal input of the first memory cell, means for initial setting of the shift register, means so synchronization operations, which ensure synchronization of the state shift operations of the memory cells with the operations carried out in the feedback block and the adder modulo two, as well as the means for storing the coefficients of the characteristic polynomial, which serve as factors in the implementation of the multiplication operations in the feedback block. Unlike the prototype, each of the n cells in the shift register memory, where n is odd, is made in the form of a quadruple memory cell with p = 4 possible states and consisting of two binary memory cells, the signal inputs and outputs of which form a signal input and output, respectively a quadruple memory cell, and the feedback block is made using multiplication and addition elements modulo four, providing logical operations of multiplication and addition modulo four over the contents of the quadruple memory cells, respectively with a quaternary characteristic polynomial and transmitting the result in the form of a quaternary feedback signal to the input of the first quaternary memory cell, while the output of the oldest of the binary memory cells included in the nth quaternary memory cell forms the first output of the pseudorandom binary sequence generator connected with the first adder input modulo two, the output of which forms the second output of the pseudo-random binary sequence generator, while the second adder input modulo two with it is single with the output of the meander generator, forming a sequence of signals of "zeros" and "units" ... 01010 ..., alternating with the shift register operation cycle.

The invention and the possibility of its implementation are illustrated by illustrative materials presented in figures 1 and 2, where:

figure 1 presents a generalized structural diagram of the inventive generator of pseudo-random binary sequences;

figure 2 is a table of quadruple characteristic polynomials.

The pseudo-random binary sequence generator contains, see FIG. 1, shift register 1, consisting of n series-connected memory cells 2 (2 ₁ , 2 ₂ ÷ 2 _n-1 , 2 _n ), where n is odd. Each memory cell 2 is a quadruple memory cell with p = 4 possible states, and consists of two binary memory cells 3 (older 3 ₁ and younger 3 ₂ ), the signal inputs and outputs of which form the signal input and output of memory cell 2, respectively. The inputs of the installation of binary memory cells 3, forming the inputs of the installation of memory cells 2, are connected with the outputs of the corresponding memory cells of block 4 of the initial setting of shift register 1.

The output of the highest memory cell 3 ₁ , which is part of the nth memory cell 2 _n , forms the first output of the pseudorandom binary sequence generator. This output is connected to the first input of the adder 5 modulo two, the output of which forms the second output of the generator of pseudorandom binary sequences.

The second input of the adder 5 modulo two is connected to the output of the meander 6 generator, forming a sequence of signals of "zeros" and "units" ... 01010 ..., alternating with the clock register 1. In the simplest case, the meander 6 generator can be implemented as a counting trigger, changing its state synchronously with the state change of memory cells 2 in the shift register 1 under the action of clock pulses generated by the clock generator (not shown in Fig. 1).

The structure of the pseudo-random binary sequence generator includes a feedback unit 7, which performs logical multiplication and addition modulo four over the contents of memory cells 2 in accordance with the quadruple characteristic polynomial with the formation of a quadruple feedback signal transmitted to the signal input of the first memory cell 2 ₁ .

In accordance with the functions performed, the feedback unit 7 comprises modulo four multiplication elements 8 and modulo four addition elements 9. The modulo four multiplication elements 8 form a multiplication circuit 10, modulo four multiplying the contents of the memory cells 2 by the coefficients of the quadruple characteristic polynomial stored in the corresponding memory cells of the block 11 of the coefficients of the characteristic polynomial. Modulo four addition elements 9 form an addition circuit 12, modulo adding four output signals generated by modulo four multiplying elements 8, to obtain an output four-way signal of the feedback unit 7. The operations carried out in the feedback unit 7 are synchronized with the operations performed in the shift register 1 to shift the state of the memory cells 2. Synchronization is carried out using conventional clock synchronization tools based on the use of a clock generator (not shown in FIG. 1).

The quadruple characteristic polynomials used in the inventive pseudo-random binary sequence generator are selected from ensembles of polynomials, the mathematical apparatus of which is presented in [8] - A. A. Nechaev. Kerdock's code in cyclic form // Discrete Mathematics, 1989, vol. 1, issue 4, pp. 123-139. To find the quaternary characteristic polynomial, it is necessary to take the primitive binary polynomial f (x) = x ⁿ + f _n-1 x ^n-1 + f ₁ x + 1 of the same degree n, where f _i = 0,1 for all i = 1, 2, ..., n-1. As already indicated, such polynomials are tabulated in detail and presented, in particular, in [5]. Separating the even degrees of the variable x in f (x) from the odd, the binary polynomial can be represented as f (x) = F ₁ (x ² ) + xF ₂ (x ² ). If we now construct the polynomial G (x) as G (x) = x [F ₂ (x)] ² - [F ₁ (x)] ² , where all operations are carried out modulo four, the polynomial F (x ) = G (3x). Since for each value of n there are a series of binary primitive polynomials, all of them lead to different quaternary characteristic polynomials. Any of these polynomials is suitable for the inventive pseudo-random binary sequence generator, however, those in which a large number of coefficients are zero are most convenient. The fact is that multiplication by zero corresponds to the absence of a connection between the corresponding memory cell 2 of shift register 1 and the feedback unit 7, and therefore a large number of zero coefficients of the characteristic polynomial simplifies the implementation of the inventive pseudorandom binary sequence generator. For example, the table in FIG. 2 shows one quadruple characteristic polynomial for each value of n from seven to seventeen, corresponding to the length range L of binary sequences from 254 to 262142, covering the needs of any navigation or many other applications. Polynomials are represented by a set of quadruple coefficients starting with the oldest.

Basically, the principle of operation of the inventive pseudo-random binary sequence generator is similar to the m-sequence generator considered above. After the initial setting of the shift register 1 (setting the initial state of the memory cells 2), the state of the memory cells 2 is shifted in cycles along the shift register 1. The state of the first memory cell 2 ₁ (the state of its binary memory elements 3 ₁ and 3 ₂ ) is determined by the signal coming from the output of the feedback block 7. As a result of the joint operation of shift register 1 and feedback block 7, a quadruple linear sequence is formed in shift register 1, the individual code of which (individual structure) is determined by the initial setting of shift register 1 and the characteristic polynomial.

Reading the state of the highest binary element of memory 3 ₁ , which is part of the nth cell of memory 2 _n , we get a pseudo-random binary sequence with the alphabet {0,1}, which, if necessary, can be changed to the alphabet {± 1} by standard conversion: 0 → 1, 1 → -1. Another pseudo-random binary sequence is removed from the output of adder 5 modulo two, adding up the above sequence with a meander (i.e., with a sequence of zeros and ones ... 010110 ..., alternating with the shift register 1 cycle time) generated by the meander 6 generator.

и квадратом максимума корреляции

Для рассматриваемых применений имеют смысл «длинные» последовательности, характеризующиеся значениями n, равными или большими семи.Changing the initial state of shift register 1, one obtains a signature ensemble of pseudorandom binary sequences, which are characterized by the length of the sequences L = 2 (2 ⁿ -1), where n is odd, volume

and squared correlation maximum

For the applications under consideration, “long” sequences with n values equal to or greater than seven make sense.

, который можно получить с помощью заявляемого генератора, многократно превышает объем ансамбля псевдослучайных бинарных последовательностей

, который можно получить с помощью прототипа. Так, например, объем ансамбля псевдослучайных бинарных последовательностей длины L=4094, получаемых с помощью заявляемого генератора при n=11, составляет величину К=2048, что более чем на порядок превосходит аналогичный показатель (К=64) для ансамбля псевдослучайных бинарных последовательностей примерно той же длины L=4095, получаемых с помощью прототипа.From a comparison of the characteristics of the ensemble of pseudorandom binary sequences obtained using the inventive generator with the characteristics of the ensemble of pseudorandom binary sequences obtained using the prototype Kasami sequence generator, it can be seen that for comparable lengths of sequences and with close correlation properties, the volume of the ensemble of pseudorandom binary sequences

, which can be obtained using the inventive generator, many times exceeds the volume of the ensemble of pseudo-random binary sequences

which can be obtained using the prototype. So, for example, the volume of an ensemble of pseudorandom binary sequences of length L = 4094, obtained using the inventive generator at n = 11, is K = 2048, which is more than an order of magnitude greater than the similar indicator (K = 64) for an ensemble of pseudorandom binary sequences the same length L = 4095 obtained using the prototype.

Thus, the above shows that the claimed invention is feasible and ensures the achievement of a technical result consisting in the development of a pseudorandom binary sequence generator capable of forming a signature ensemble of pseudorandom binary sequences with approximately the same correlation characteristics as in the prototype Kasami sequence generator, but much larger volume. Given the relatively simple implementation, this feature of the inventive pseudo-random binary sequence generator makes it promising for solving urgent problems in the field of broadband transmission and code separation of signals associated with an increase in the number of channels and the expansion of the range of signals, including in satellite navigation systems.

Information sources

1. M.D. Venediktov, S.A. Danielyan, V.V. Markov, G.S. Eidus. Multiple access in satellite communication systems. M., Communication, 1973, pp. 81-83, Fig. 6.3.

2. The global satellite radio navigation system GLONASS. Ed. V.N.Kharisova, A.I. Perov, V.A.Boldin. M., IPRZh, 1998, p. 64-66, Fig. 5.1.

3. SU 375769 A1, G06F 7/58, publ. 01/01/1973.

4. RU 2223593 C1, H03B 29/00, G06F 7/58, publ. 02/10/2004.

5. W. Peterson, E. Weldon. Error correction codes. M., World, 1976.

6. V.P. Ipatov. Broadband systems and code division signals. Principles and applications. M., Technosphere, 2007, p. 215-221, 304-310, fig. 7.18, 7.19, p. 312, table 7.1.

7. On-board devices of satellite radio navigation. / I.V. Kudryavtsev, I.N. Mishchenko, A.I. Volynkin and others. Ed. B.C. Shebshaevich. M., Transport, 1988, pp. 15-16, Fig. 5.

8. A.A. Nechaev. Kerdock's code in cyclic form // Discrete Mathematics, 1989.Vol.1, issue 4, p.123-139.

Claims (1)

A pseudorandom binary sequence generator containing a shift register consisting of n series-connected memory cells, each of which has p possible states, an adder modulo two, connected to the nth memory cell, a feedback unit that performs logical operations of multiplication and addition over the contents memory cells for generating, according to the characteristic polynomial, a feedback signal transmitted to the signal input of the first memory cell, means for initial setting of the shift register, means t synchronization, providing synchronization of the state shift operations of the memory cells with the operations carried out in the feedback unit and the adder modulo two, as well as means for storing the coefficients of the characteristic polynomial, serving as factors in the implementation of the multiplication operations in the feedback unit, characterized in that each of n memory cells of the shift register, where n is odd, made in the form of a quadruple memory cell with p = 4 possible states and consisting of two binary memory cells, the input and output of which form the signal input and output of the quadruple memory cell, respectively, and the feedback block is made using multiplication and addition elements modulo four, ensuring logical operations of multiplication and addition modulo four over the contents of the quadruple memory cells in accordance with the quadruple characteristic polynomial and the transmission of the result in the form of a quadruple feedback signal to the input of the first quadruple memory cell, while the eldest binary x memory cells, which is part of the nth quadruple memory cell, forms the first output of the pseudo-random binary sequence generator connected to the first input of the adder modulo two, the output of which forms the second output of the pseudo-random binary sequence generator, while the second adder input modulo two with the output of the meander generator, forming a sequence of signals of "zeros" and "units" ... 01010 ..., alternating with the clock register shift.

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