RU2762209C1 - DEVICE FOR PARALLEL FORMATION OF q-VALUED PSEUDO-RANDOM SEQUENCES ON ARITHMETIC POLYNOMS - Google Patents

Abstract

FIELD: pseudo-random sequences generation.

SUBSTANCE: invention relates to a device for parallel generation of q-digit pseudo-random sequences on arithmetic polynomials. The device contains a memory unit for storing the coefficients of polynomials, to the input of which the bus for feeding the coefficients is connected; multipliers, the outputs of which are connected to the inputs of multi-place adders; a masking operator block, the outputs of which are the outputs of the device, a memory register, the inputs of which are the inputs of the device, to which the feed bus of r variables of multivalued functions of logic algebra is connected; multipliers, to the inputs of which the bus for supplying r variable multivalued functions of logic algebra is connected, the outputs of which are connected to the first inputs of the factors, to the second inputs of which the output of the memory unit of the coefficients of the arithmetic polynomial is connected; a multiplier by weight coefficients qj-1, to the first inputs of which the outputs of multi-place adders are connected, to the second inputs of which a memory unit of weight coefficients is connected, to the output of which a bus for supplying weight coefficients is connected; a multi-place adder modulo qr, the output of which is connected to the masking operator, the outputs of which are outputs of the device for issuing r values ​​of multivalued functions of logic algebra.

EFFECT: providing parallel computation of multivalued pseudo-random sequences.

1 cl, 6 dwg, 3 tbl

Description

The technical field to which the invention relates

The invention relates to computer technology and can be used for parallel implementation of systems of multivalued functions of logic algebra (MFAL) in means of cryptographic information protection.

State of the art

a) Description of analogs

A device for obtaining pseudo-random sequences (pseudo-noise, register sequences of maximum length, M-sequences) is known, the elements of which belong to an alphabet of q symbols (q is a prime number or a power of a prime number), based on the use of switching circuits of a special type, called linear recurrent shift registers with feedback (LRRS) [MacWilliams F., Sloane N. Pseudo-random sequences and arrays, Proc. IEEE, 64, pp. 1715-1729, 1976; Lidl R., Niederreiter H. Introduction to finite fields and their applications, Cambridge: Cambridge Univ. Press, 1987]. The construction of an LRRS over GF (q) (hereinafter q-LRRS) is carried out according to a given primitive, irreducible (characteristic) polynomial:

where p _i ∈ GF (q), r is the degree of the polynomial P (z), r GN, GF (q) is the Galois field of q elements and the homogeneous recurrent equation constructed in accordance with it:

or

where n = 0, 1, 2, ...; p _j ∈ GF (q), 0 ≤ j ≤ r - 1; ⊕ is the mod q addition symbol.

In the general case, q-LRRS consists of structural elements: cells D _j (j = 0, 1, ..., r-1), adders mod q, amplifiers mod q and has an initial filling (elements of the GF (q) field): s ₀ , s ₁ , ..., s _r-1 . By "cell" is meant a parallel [log ₂ q] - bit register (⎡х⎤ - the smallest integer equal to or greater than x). After the first cycle of work, q-LRRS contains filling: s ₁ , s ₂ ,…, s _r . In general, q-LRRS (Fig. 1) generates an infinite output q-valued sequence s ₀ , s ₁ , s ₂ , ..., s _r-1 , ... with a period q ^r - 1 (for a nonzero initial state), and each nonzero the state appears once per period. The generated segment of the output sequence of length q ^r - 1 is a pseudo-random sequence (PRS) over GF (q).

In terms of linear algebra, the next element of the PSP s _{n + r} obtained using (1) is calculated in accordance with the expression:

- символ транспонирования.Where

- transposition symbol.

The disadvantage of the device is the sequential organization of computations, in which the output bandwidth segment is formed. b) Description of the closest analogue (prototype)

The closest in technical essence to the claimed technical solution and adopted as a prototype is the device described in [RF Patent No. 2579991 C1 publ. 04/10/2016].

The considered device contains a bus for supplying t Boolean variables, a memory unit designed to store the coefficients of a linear numerical polynomial (LPP), to the input of which the bus for supplying LPF coefficients is connected; in addition, a memory register is introduced, the inputs of which are the inputs of the device, to which the bus for supplying τ of Boolean variables is connected; a memory block designed to store the bases of the system, to the input of which the feed bus of the bases of the system is connected, the outputs of which, together with the outputs of the memory block for storing the LPI coefficients, are connected to the inputs of the blocks for calculating the least non-negative residues of the number (LPR coefficients) based on the bases of the system, the outputs of which are together with the outputs the memory register is connected to the inputs of the multipliers, the outputs of which are connected to the inputs of multiplace adders, the outputs of which are connected to the inputs of the solution block of the comparison system with one unknown, the output of which is connected to the inputs of the comparison block and the masking operator block, the output of the comparison block is connected to the second input of the masking operator block , the outputs of which are the outputs of the device for issuing values of τ of Boolean functions.

The block diagram of the prototype device is shown in Fig. 2.

The device considered as a prototype is intended for calculating binary memory bandwidth, identical to the bandwidth obtained by means of classical generators on the LRRS, with the function of controlling computational errors. The operation of the device is based on the representation of systems of recursive characteristic equations of the LPP.

The disadvantage of the known device is the lack of functionality for obtaining multi-valued PSP.

Disclosure of invention

a) Technical result, the achievement of which is aimed at the invention The aim of the proposed technical solution is to provide parallel computation of multivalued PSP, identical to PSP over GF (q) (q> 2), obtained by means of classical generators on q-LRRS.

b) A set of essential features The technical result of the invention is achieved by:

This goal is achieved by the fact that in the device for the parallel formation of q-valued pseudo-random sequences on arithmetic polynomials, containing a memory unit designed to store the coefficients of the polynomials, to the input of which the bus for feeding the coefficients is connected; multipliers, the outputs of which are connected to the inputs of multi-place adders; a masking operator block, the outputs of which are the outputs of the device, a memory register is additionally introduced, the inputs of which are the inputs of the device, to which the bus for supplying r variables of multivalued functions of logic algebra is connected; multipliers, to the inputs of which the bus for supplying r variable multivalued functions of logic algebra is connected, the outputs of which are connected to the first inputs of the factors, to the second inputs of which the output of the memory unit of the coefficients of the arithmetic polynomial is connected; a multiplier by weight coefficients q ^i-1 , to the first inputs of which the outputs of multi-place adders are connected, to the second inputs of which a memory unit of weight coefficients is connected, to the output of which a bus for supplying weight coefficients is connected; a multi-place adder modulo q ^r , the output of which is connected to the masking operator, the outputs of which are the outputs of the device for issuing r values of multivalued functions of logic algebra.

c) Causal relationship between features and technical result

Owing to the introduction of a set of essential distinctive features into a known object, the device for parallel formation of q-valued PSPs on arithmetic polynomials makes it possible to implement an algorithm for the parallel formation of q-valued PSPs for the implementation of promising high-performance means of cryptographic information protection.

Evidence of compliance of the claimed invention with the conditions of patentability "novelty" and "inventive step"

The analysis of the state of the art made it possible to establish that there are no analogues characterizing the set of features identical to all the features of the claimed technical solution, which indicates that the claimed method corresponds to the "novelty" condition of patentability.

The search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the prototype features of the claimed object have shown that they do not follow explicitly from the prior art. The prior art also did not reveal the knowledge of the distinctive essential features that determine the same technical result that is achieved in the claimed method. Therefore, the claimed invention corresponds to the level of patentability "inventive step".

Brief Description of Drawings

The claimed device is illustrated by drawings, which show:

- in Fig. 1 is a block diagram of a q-LRRS operating in accordance with the homogeneous recurrent equation (1);

- in Fig. 2 is a diagram of a prototype device;

- in Fig. 3 is a block diagram of a parallel q-LRRS operating in accordance with expression (4);

- in Fig. 4 is a diagram of parallel computations of the generator corresponding to expression (7);

- in Fig. 5 is a diagram explaining the principle of operation of the multipliers 3.r;

- in Fig. 6 - device for parallel formation of q-digit pseudo-random sequences on arithmetic polynomials.

Implementation of the invention

Let's consider the algorithm of the device.

Let s ₀ , s ₁ , s ₂ ,…, s _r-1 ,… be the elements of the PRS that satisfy the multivalued recurrent equation (1). Since an arbitrary element s _n (n ≥ r) of the sequence s ₀ , s ₁ , s ₂ , ..., s _r-1 , ... is determined by the preceding r elements, we represent the elements of the PRS section of length rs _{n + r} , s _{n + r + 1} ,…, s _{n + 2r-1} in the form of a system of recurrent equations:

where [s _{n + r} s _{n + r + 1} … s _{n + 2r-1} ] is the vector of the r-th state of the PSP (or the internal state of the q-LRRS at the r-th cycle of work).

Let us express the right-hand sides of system (2) in terms of the given initial conditions:

Simplifying expression (3), we write the resulting system of recurrent equations as a system of r multivalued functions of logic algebra (MFAL) in r variables:

формируются после сокращения выражения (3). На фигуре 3 в соответствии с выражением (4) представлена структурная схема параллельных вычислений генератора.Odds

are formed after the reduction of expression (3). In figure 3, in accordance with expression (4), a block diagram of parallel computations of the generator is presented.

We represent an arbitrary MFAL in the form of an arithmetic polynomial:

where a _i - i-th coefficient of the arithmetic polynomial; s = s _n , s _{n + 1} ,…, s _{n + r-1} are the arguments of the IPAL s _u ∈ {0, 1,…, q - 1} (u = 0, 1,…, r - 1); (i ₀ i ₁ … i _r-1 ) q is the representation of the parameter i in the q-ary number system:

For MFAL known algebraic and matrix methods for constructing an arithmetic polynomial [Kukharev GA, Shmerko VP, Zaitseva EN. Algorithms and systolic processors for processing multivalued data. - Minsk: Science and technology, 1990. - 296 p.]. Direct and inverse matrix transformation is defined by expressions

и

- матрицы прямого и инверсного арифметического преобразования размерности q^r × q^r (базис преобразования); S - вектор истинности МФАЛ:where N _k - normalizing factor;

and

- matrices of direct and inverse arithmetic transformation of dimension q ^r × q ^r (transformation basis); S is the MFAL truth vector:

where s ⁽ⁱ⁾ is the numerical value accepted by the MFAL on the i-th set of variables; vector of coefficients (spectrum) of arithmetic polynomial (5):

и

определяется кронекеровским возведением в степень:Matrices

and

is determined by Kronecker's exponentiation:

и

- базовые матрицы прямого и обратного преобразования (таблица 1 - для q=2, 3, …, 6).Where

and

- basic matrices of direct and inverse transformations (table 1 - for q = 2, 3,…, 6).

.For the MFAL f (S) = 2s ₀ ⊕ 2s ₁ (mod 3) the vector of the received values of the MFAL has the form S = [0 2 1 2 1 0 1 0 2]

...

Accordingly, the direct transformation (6) can be represented as follows:

Then, in accordance with expression (5), the algebraic form of the MFAL takes the form

For example, when s ₀ = 2 and s ₁ = 2 MFAL corresponds to the value:

For a 3-valued Boolean function depending on 2 variables, Table 2 shows the corresponding arithmetic polynomials. Table 3 shows as an example the calculated arithmetic polynomials for a 3-valued Boolean function depending on 3 variables.

We implement the MFAL system (4) by calculating some arithmetic polynomial. For this, we put in correspondence to the IPAL system (4) a system of arithmetic polynomials of the form (5). We get:

We multiply the polynomials of system (7) by the weights q ^l-1 (l = 1, 2,…, r):

where

Then, we get:

or using the provisions of the generalization of modular forms to MFAL [Finko O.A. Modular arithmetic of parallel logical computing. - Krasnodar: Krasnodar Military Institute, 2003. - 224 p.]:

where

Let us calculate the values of the required MFAL. To do this, we represent the result of calculating M (S) in the q-ary number system and apply the masking operator Ξ ^t {M (S)}:

where t is the desired q-ary bit of the representation M (S). Figure 3 is a diagram explaining the essence of parallel computations of the generator in accordance with expression (8).

The proposed device contains a bus 10 for supplying r values of the MFAL variables s _{n + r-1} , s _{n + r-2} , ..., s _n , a bus 11 for supplying coefficients a _{r, i of} arithmetic polynomials, a bus 12 for supplying weight coefficients q ^l-1 , memory register 1, block 2 for memory of coefficients a _{r, i of} arithmetic polynomials, block 6 for memory of weight coefficients q ^l-1 , blocks 3.1, 3.2,…., 3.r of multipliers, factors 4.1.0, 4.1.1,…, 4.1 .q ^r - 1, 4.2.0, 4.2.1,…, 4.2.q ^r - 1, 4.r.0, 4.r.1,…, 4.rq ^r - 1, multiplace adders 5.1, 5.2, ..., 5.r, factors 7.1, 7.2, ..., 7.r, multiplace adder modulo q ^r 8, block 9 of the masking operator, outputs 13.1, 13.2, ..., 13.r values r of multivalued functions of the algebra of logic f ₁ (s _{n + r-1} , s _{n + r-2} ,…, s _n ), f ₂ (s _{n + r-1} , s _{n + r-2} ,…, s _n )…, f _r (s _{n + r -1} , s _{n + r-2} , ..., s _n ).

Bus 10 for supplying r values of MFAL variables s _{n + r-1} , s _{n + r-2} , ..., s _n , is the input of memory register 1, the output of which is connected to the inputs of multipliers 3.1, 3.2, ..., 3.r, whose outputs connected to the first inputs of multipliers 4.1.0, 4.1.1,…, 4.1.q ^r - 1, 4.2.0, 4.2.1,…, 4.2.q ^r - 1, 4.r.0,4.r.1 ,…, 4.rq ^r - 1, to the second inputs of which the output of the memory unit 2 is connected, to the input of which the bus 11 for supplying the coefficients a _{r, i of the} arithmetic polynomials is connected; outputs of factors 4.1.0, 4.1.1,…, 4.1.q ^r - 1, 4.2.0, 4.2.1,…, 4.2.q ^r - 1, 4.r.0, 4.r.1,…, 4.rq ^r - 1 are connected to the inputs of multiplace adders 5.1, 5.2, ..., 5.r, the corresponding outputs of which are connected to the first inputs of multipliers 7.1, 7.2, ..., 7.r for weight coefficients q ^l-1 , to the second inputs of which connected to the memory unit 6, to the input of which the bus 12 is connected to the supply of weight coefficients q ^l-1 ; the outputs of the factors 7.1, 7.2, ..., 7.r are connected to the input of the multiplace adder 8 modulo q ^r , the output of which is connected to the input of block 9 of the masking operator, the outputs of which are the outputs of the device for issuing r values of multivalued functions of the algebra of logic f ₁ (s _{n + r-1} , s _{n + r-2} ,…, s _n ), f ₂ (s _{n + r-1} , s _{n + r-2} ,…, s _n ),…, f _r (s _{n + -1} , s _{n + r-2} , ..., s _n ).

The proposed device works as follows.

поступают на входы множителей 4.1.0, 4.1.1, …, 4.1.q^r - 1, 4.2.0, 4.2.1, …, 4.2.q^r - 1, 4.r.0, 4.r.1, …, 4.r.q^r - 1. С выходов множителей 4.1.0, 4.1.1, …, 4.1.q^r - 1, 4.2.0, 4.2.1, …, 4.2.q^r - 1, 4.r.0, 4.r.1, …, 4.r.q^г - 1. на входы многоместных сумматоров 5.1,5.2, …, 5.r поступают произведения

С выходов многоместных сумматоров 5.1,5.2, …, 5.r на соответствующие входы множителей 7.1, 7.2, …, 7.r поступают результаты вычисления арифметических полиномов A±(S), A₂(S), …, A_r(S), также на вход множителей 7.1, 7.2, …, 7.r из блока памяти 6 поступают весовые коэффициенты q^l-1. Далее с выходов множителей 7.1, 7.2, …, 7.r результаты вычислений q⁰A₁(S), q¹ A₂(S), …, q^r-lA_r(S) поступают на вход многоместного сумматора 8 по модулю q^r. С выхода многоместного сумматора 8 по модулю q^r на вход блока 9 оператора маскирования поступает числовой результат вычисления (8). Далее выхода блока 9 оператора маскирования получим значения МФАЛ f₁(s_n+r-1, s_n+r-2, …, s_n), f₂(s_n+r-1, s_n+r-2, …, s_n), …, f_r(s_n+r-1, s_n+r-2, …, s_n), которые соответствуют элементам r-го блока ПСП s_n+2r-1, s_n+2r-2, …,s_n+r.In the initial state, the memory blocks 2 and 6 are entered on the buses 11 and 12 with the coefficients a _{r, i of the} arithmetic polynomials and the weight coefficients q ^l-1, respectively. From the output of the memory block 2 to the input of the factors 4.1.0, 4.1.1,…, 4.1.q ^r - 1, 4.2.0, 4.2.1,…, 4.2. q ^r - 1, 4.r.0,4.r.1,…, 4.rq ^r - 1 the coefficients a _{r, i of the} arithmetic polynomials are received. At the moment of time corresponding to the beginning of the transformations, the values of r variables of the MFAL s _{n + r-1} , s _{n + r-2} , ..., s _n arrive at the inputs of the memory register 1 from the bus 10. From the output of memory register 1, the values of r variables of the MFAL s _{n + r-1} , s _{n + r-2} ,…, s _n arrive at the inputs of blocks 3.1, 3.2,…, 3.r multipliers, from the output of which the arguments

come to the inputs of factors 4.1.0, 4.1.1, ..., 4.1.q ^r - 1, 4.2.0, 4.2.1, ..., 4.2.q ^r - 1, 4.r.0, 4.r.1, …, 4.rq ^r - 1. From the outputs of the factors 4.1.0, 4.1.1,…, 4.1.q ^r - 1, 4.2.0, 4.2.1,…, 4.2.q ^r - 1, 4.r. 0, 4.r.1, ..., 4.rq ^г - 1.the inputs of multiplace adders 5.1,5.2, ..., 5.r arrive at the products

The results of calculating arithmetic polynomials A ± (S), A ₂ (S),…, A _r (S) , also the input of factors 7.1, 7.2,…, 7.r from the memory block 6 receives the weight coefficients q ^l-1 . Further, from the outputs of the factors 7.1, 7.2,…, 7.r, the results of calculations q ⁰ A ₁ (S), q ¹ A ₂ (S),…, q ^rl A _r (S) are fed to the input of the multiplace adder 8 modulo q ^r ... From the output of the multiplace adder 8 modulo q ^{r, the} numerical result of the calculation (8) is sent to the input of the masking operator block 9. Further, the output of block 9 of the masking operator, we obtain the values of the MFAL f ₁ (s _{n + r-1} , s _{n + r-2} ,…, s _n ), f ₂ (s _{n + r-1} , s _{n + r-2} ,… , s _n ),…, f _r (s _{n + r-1} , s _{n + r-2} ,…, s _n ), which correspond to the elements of the rth block of the PRS s _{n + 2r-1} , s _{n + 2r- 2} ,…, s _n + r.

The claimed invention can be carried out using the means and methods described in the available sources of information. This allows us to conclude that the claimed invention is consistent with the features of "industrial applicability".

Example. Consider the construction of q = 3 LRRS generating a 3-digit PSP, given by the recurrent equation: s _{k + 3} = 2s _{k + 2} ⊕ s _k (mod 3) and initial filling: s ₀ = 0, s ₁ = 1, s ₂ = 2. The corresponding characteristic polynomial is: P (z) = z ³ + 2z ² +1.

Then the system of recurrent equations for a three-element PSP section will take the form:

Next, we write the system of recurrent equations as a system of MFAL with the right-hand sides of the equalities expressed in terms of the given initial conditions:

In accordance with (7), we obtain a system of arithmetic polynomials of the following form:

We implement a system of arithmetic expressions in the form of an arithmetic polynomial:

The modular polynomial form becomes:

In accordance with the given initial conditions, the following fragment of the 3-digit PSP can be obtained:

The given example has shown that the inventive device for parallel formation of q-valued PSP on arithmetic polynomials functions correctly, is technically feasible and allows solving the problem.

Claims (1)

A device for parallel formation of q-digit pseudo-random sequences on arithmetic polynomials, comprising a memory unit for storing the coefficients of the polynomials, to the input of which the bus for feeding the coefficients is connected; multipliers, the outputs of which are connected to the inputs of multi-place adders; a masking operator block, the outputs of which are the outputs of the device, characterized in that a memory register is introduced, the inputs of which are the inputs of the device, to which the bus for supplying r variables of multivalued functions of logic algebra is connected; multipliers, to the inputs of which the bus for supplying r variable multivalued functions of logic algebra is connected, the outputs of which are connected to the first inputs of the factors, to the second inputs of which the output of the memory unit of the coefficients of the arithmetic polynomial is connected; a multiplier by weight coefficients q ^j-1 , to the first inputs of which the outputs of multi-place adders are connected, to the second inputs of which a memory unit of weight coefficients is connected, to the output of which a bus for supplying weight coefficients is connected; a multi-place adder modulo q ^r , the output of which is connected to the masking operator, the outputs of which are the outputs of the device for issuing r values of multivalued functions of logic algebra.

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