RU2422984C2 - Pulse shaper - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: pulse shaper includes D-triggers, generator of rectangular pulses, binary counter, decoder, shifting registers, majority elements, AND circuit, as well as transistor switches at the outlet of device and control circuit of transistor switches which are combined into common electronic circuit in certain manner.

EFFECT: enlarging functional capabilities of pulse shaper owing to providing the possibility of its interference immunity, possibility of shaping the output signal of specified voltage, and possibility of shaping output pulses.

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Description

The invention relates to a pulse technique and can be used in telemetry, automated control systems, control, measurement and other devices of various industries.

A known delay line, selected as a prototype, containing a D-trigger controlled by OR, OR-NOT, as well as a rectangular pulse generator, a binary pulse counter and a decoder (RF patent No. 2103813 C1, IPC6 H03K 17/28).

This device allows you to shift in time the output pulse signal relative to the input and change after the shift of its duration. The disadvantage of this device is the limited functionality due to insufficient noise immunity of the input signal when using high-speed circuits (with a short switching time), a fixed output voltage equal to the output voltage of the outputs of the logic circuits, and the lack of the ability to block the transmission of pulses from input to output.

The technical result is expressed in expanding the functionality of the device by ensuring its noise immunity, the possibility of generating an output signal of a given voltage, different from the voltage of the outputs of the logic circuits, and the possibility of blocking the formation of output pulses.

To achieve a technical result, a pulse shaper containing a D-trigger, a rectangular pulse generator, the output of which is connected to a synchronization input of a binary pulse counter, the output bits of which, except the last, are connected to a decoder, is equipped with two shift registers, two majority elements, two D-triggers , the control circuit of the transistor switches, three transistor switches and the circuit And, moreover, the output of the rectangular pulse generator is connected to the synchronization inputs of the first and second th shift registers, the first and third D-flip-flops, as well as with one of the inputs of the transistor switch control circuit, the first information input of the driver is connected to the zero bit of the first shift register, the outputs of which are connected to the corresponding inputs of the first majority element, the output of which is connected to the input of the first D-flip-flop, the output of which is connected to the synchronization input of the second D-flip-flop, on the other input of which the signal “1” is set, the output of the second D-flip-flop is connected to the reset input of the binary counter , the highest bit of the binary counter is connected to the reset input of the second D-trigger, the decoder output is connected to the first input of the And circuit, the second information input of the shaper is connected to the zero bit of the second shift register, the outputs of which are connected to the corresponding inputs of the second majority element, the output of which is connected to the input the third D-flip-flop, the inverted output of which is connected to the second input of the And circuit, the output of which is connected to the second input of the transistor switch control circuit, the first output of which is single with the first terminal of the first resistor, the second terminal of which is connected to the base of the first transistor, the emitter of which is connected to a common wire, and the collector is connected to the first terminal of the second resistor and the base of the second transistor, the second terminal of the second resistor is connected to the emitter of the second transistor and with the plus of the reference voltage , the second output of the transistor switch control circuit is connected to the first terminal of the third resistor, the second terminal of which is connected to the base of the third transistor, the emitter of which is connected to a common wire, ry second and third transistors are connected together and to the output of the.

The drawing shows a structural diagram of a pulse shaper.

The pulse shaper has two information inputs: Imp. and Set. Input Imp. connected to the zero bit of the 5-bit shift register 1. The data in this register is shifted from the zero bit to the fourth along the edge of the rectangular pulses. All five bits of the shift register 1 are connected to the majority element 2. Element 2 transmits to the output a value that corresponds to most of the input data. The output of the majority element 2 is connected to the input of the D-trigger 3. The output of the trigger 3 is connected to the C-input of the D-trigger 4, at the input of which there is a constant single signal. The inverted output of trigger 4 is connected to the reset input of counter 5. All bits of the counter 5, with the exception of the highest level, are connected to the inputs of the decoder 6. The senior bit of the counter 5 is connected to the reset input of the D-trigger 4. The output of decoder 6 is connected to the first input of AND 7 .

Login Set connected to the zero bit of the second 5-bit shift register 8, similar to register 1. All five bits of the shift register 8 are connected to the second majority element 9. The output of the majority element 9 is connected to the input of the D-trigger 10. The inverting output of the D-trigger 10 is connected to the second input of the circuit And 7. The output of the circuit And 7 is connected to the input of the control circuit of the transistor switches 11, connected to the pulse generator 12. Rectangular pulses from the generator 12 are supplied to the C-inputs of register 1, trigger 3, counter 5, register 8, trigger 10.

The transistor switch control circuit 11 has two outputs: Q0 and Q1. The output Q1 is connected to the first terminal of the resistor R1, the second terminal is connected to the base of the transistor VT1. The emitter of transistor VT1 is connected to a common wire, the collector is the first output of resistor R2 and the base of transistor VT2. The second output of the resistor R2 is connected to the emitter VT2 and the plus of the reference voltage source. The output Q0 of the control circuit of the transistor switches 11 is connected to the first output of the resistor R3. The second output of the resistor is connected to the base of the transistor VT3. The emitter of the VT3 transistor is connected to a common wire. The collectors of transistors VT2 and VT3 are interconnected and with the output of the shaper.

The pulse generator operates as follows.

At the initial time, triggers 3, 4, 10 are in a reset state. At the output of trigger 3 - “0”, triggers 4 and 10 - “1”. Counter 5 - reset (“reset”). The outputs Q0 and Q1 of the control circuit of the transistor switches 11 are in the state Q0 = 1, Q1 = 0. Transistors VT1 and VT2 are locked, VT3 is open, connecting the output of the device with a common wire.

Signal value at imp. is continuously recorded in the shift register 1 along the front of the rectangular pulses received at the C-input of this register 1 from the rectangular pulse generator 12. Recording is made in the 0th digit, while the value from the 0th digit is written in the 1st, from the 1st go in the 2nd, etc. (i.e., the shift of the discharge values is performed). So far at the entrance of Imp. signal “0”, all bits of the shift register 1 have the value “0”, and at the output of the majority element 2 also “0”. When changing the signal at the input Imp. to “1”, along the front of a rectangular pulse from generator 12 at input C to the 0th digit, “1” will be written. With the duration of the signal "1" at the input Imp. greater than three periods of pulses of the generator 12, in the shift register 1, at least three digits will have a value equal to "1". While the number of bits in the shift register 1 having the value “1” is less than or equal to two, the state Q = 0 at the output Q of the majority element 2. As soon as the number of digits with the value “1” becomes more than two, the output state changes to Q = 1. The use of shift registers 1 and 8, majority elements 2 and 9 allows the device to ignore short interference pulses at the information input of the device, which can cause false alarms. The use of these schemes significantly increases the noise immunity of the shaper. The signal "1" from the output of the majority element 2 is fed to the data input of trigger 3, and along the edge of the rectangular pulse at the C-input of this trigger 3, signal "1" is set at the output of trigger 1. Since the output of trigger 3 is connected to the C-input of trigger 4 , then when the signal at the output of trigger 3 changes from “0” to “1”, the signal at the output of trigger 4 is set to “0” (when the counter 5 is zero, all bits of which are equal to zero, “0” is sent to the reset input R of trigger 4 from the last digit of the counter 5). The output of trigger 4 is connected to the reset input R of counter 5. After setting “0” at the input R of counter 5, counter 5 starts counting pulses from generator 12 arriving at the C input. All bits of the counter 5, with the exception of the high-order bit, are connected to the decoder 6. After the binary code corresponding to the first specified number of pulses is generated at the inputs of the decoder 6, “1” is set at the output of the decoder 6. After decoding the number of pulses corresponding to the second number, the output of the decoder 6 is set to "0". Further, the counter 5 continues to count until “1” is set on the highest level of the counter. This signal from the high-order bit is fed to the reset input R of trigger 4. Trigger 4 is reset, “1” is set at its output. The signal from the output of trigger 4 resets counter 5: all outputs of the counter are reset, the reset is removed from input R of trigger 4. The system enters a state of waiting for the arrival of the next pulse to the input Imp. The signal from the output of the decoder 6 goes to the first input of the And 7 circuit, to the second input of which “1” comes from the output of the trigger 10. As long as the signal “1” is at the second input of the And 7 circuit, the signal at the output of And corresponds to the signal at its first input. The output of the circuit And 7 is connected to the input of the control circuit of the transistor switches 11. The control circuit of the transistor switches 11 is provided to prevent the simultaneous opening of the transistors VT2 and VT3 and short circuit of the reference voltage source to a common wire. While at the input of circuit 11 the signal is "0", at the outputs of the circuit Q1 = 0, Q0 = 1. After the signal “1” is installed at the input of circuit 11, Q0 = 0 is set at the output Q0, and after a time interval equal to one period of rectangular pulses entering the circuit 11 from the generator 12, Q1 = 1 is set at the output Q1. When setting the input value “0” again, the value “0” at the output Q1 sets Q1 = 0, and after a time interval equal to one period of rectangular pulses, at the output Q0, Q0 = 1 is set. The interval between the installation of signals at the outputs is provided for the output of transistors from saturation mode. The signal "1" from the output Q1 of the circuit 11 through the resistor R1 enters the base of the transistor VT1, the transistor opens, a current begins to flow through the emitter-collector junction. With the transistor VT1 open, current begins to flow through the resistor R2. The voltage across the resistor R2 opens the transistor VT2, through the emitter-collector junction of which + U _reference. arrives at the output of the shaper. If the output Q1 of the circuit 11 is “0”, then the transistors VT1 and VT2 are closed, + U _reference. It doesn’t get to the output. The signal "1" from the output Q0 of the circuit 11 through the resistor R3 enters the base of the transistor VT3, the transistor opens, through the emitter-collector junction the device output is connected to a common wire. If the output Q0 of the circuit 11 «0, then the transistor VT3 is closed, the output of the device is not connected to the common wire. The given control circuit for supplying voltage to the output of the device allows the use of + U _reference. any given value. A limitation on the voltage value is imposed by the type of transistor. Signal value at the input continuously recorded in the shift register 8 along the front of the rectangular pulses arriving at the C-input of this register (by type, shift register 8 is similar to shift register 1). Recording is performed in the 0th digit, while the value from the 0th digit is shifted to the 1st, from the 1st to the 2nd, etc. When installing at the input signal “1” along the edge of the pulse at input C to the 0th digit will be written “1”. When the signal duration is greater than three periods of the pulses of the generator 12, in the shift register 8 at least three digits will have a value equal to "1". While the number of digits in the shift register 8 having a value of "1" is less than or equal to two, the state Q = 0 at the output Q of the majority element 9. As soon as the number of digits with the value “1” becomes more than two, the output state changes to Q = 1. The signal "1" from the output of the majority element 9 is fed to the data input of the trigger 10, and along the front of the rectangular pulse at the C-input of this trigger at the output of the trigger 10 is set to "0". The output of trigger 10 is connected to the second input of circuit And 7, when a signal “0” is applied to this input from trigger 10, “0” is set at the output of circuit 7, blocking a change in the signal at the output of circuit And 7. While at the input Set. held "1", the output of the device is connected to a common wire, pulses at the input Imp. Do not affect the output status of the device. Thus, setting the signal “1” at the input Set. allows you to block the formation of pulses from the input Imp. to the output of the device.

The introduction of shift registers, triggers, majority elements, AND circuitry, as well as transistor switches at the device output and transistor switch control circuits, appropriately connected into a single electronic circuit, increased the noise immunity of the driver, provided the possibility of generating an output signal of a given voltage, which differs from the voltage of the outputs of the logic circuits, the ability to block the formation of output pulses and, as a result, allowed to expand pulse shaper functionality.

In addition, D-flip-flops, binary counter, decoder, shift registers, majority elements, circuit I, transistor switch control circuit can be implemented on a programmable logic integrated circuit FPGA type XC95144 or similar, which will significantly reduce the dimensions of the device.

Claims (1)

A pulse shaper containing a D-trigger, a rectangular pulse generator, the output of which is connected to a synchronization input of a binary pulse counter, the output bits of which, except the last, are connected to a decoder, characterized in that it is equipped with two shift registers, two majority elements, two D-triggers , the control circuit of the transistor switches, three transistor switches and the circuit And, and the output of the rectangular pulse generator is connected to the synchronization inputs of the first and second shear reg Istr, the first and third D-flip-flops, as well as with one of the inputs of the transistor switch control circuit, the first information input of the driver is connected to the zero bit of the first shift register, the outputs of which are connected to the corresponding inputs of the first majority element, the output of which is connected to the input of the first D- the trigger, the output of which is connected to the synchronization input of the second D-trigger, the signal “1” is installed at the other input, the inverted output of the second D-trigger is connected to the binary counter reset input ka, the highest bit of the binary counter is connected to the reset input of the second D-trigger, the decoder output is connected to the first input of circuit I, the second information input of the shaper is connected to the zero bit of the second shift register, the outputs of which are connected to the corresponding inputs of the second majority element, the output of which is connected to the input of the third D-flip-flop, the inverted output of which is connected to the second input of the And circuit, the output of which is connected to the second input of the transistor switch control circuit, the first moment of time at the first output of the transistor switch control circuit sets a logic zero signal, and at the second output - a logic unit signal, after setting a logical unit at the second input of the transistor switch control circuit, a logical zero is established at its second output, and after a time interval equal to one period of rectangular pulses from the rectangular pulse generator to the first input of the transistor switch control circuit, a logical unit is established at its first output tsa, when a logic zero is installed at the second input of the transistor switch control circuit, a logical zero is set at its first output, and after a time interval equal to one period of rectangular pulses, a logical unit is established at its second output, the first output of which is connected to the first output of the first resistor , the second terminal of which is connected to the base of the first transistor, the emitter of which is connected to a common wire, and the collector to the first terminal of the second resistor and the base of the second transistor, the second terminal is the resistor is connected to the emitter of the second transistor and with the plus of the reference voltage, the second output of the transistor switch control circuit is connected to the first terminal of the third resistor, the second terminal of which is connected to the base of the third transistor, the emitter of which is connected to a common wire, the collectors of the second and third transistors are interconnected and with the output of the shaper.