RU2397603C1 - Wide-range annular voltage-controlled producer - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: producer supports constant signal amplitude of symmetrical oscillation, which is equal to power supply voltage and is capable of quick readjustment within the operating range. Producer consists if CMOS inverters with controlled switching current, which are combined in a ring, which provides negative feedback as to direct current. Inverter includes the following: the first, the second and the third P - channel transistors and the first, the second and the third N - channel transistors, gates of the first P - channel transistor and the first N - channel transistor are connected and form the input In of inverter, sinks of the first P - channel transistor and the first N - channel transistor are connected and form output Out of inverter, source of the first P - channel transistor is connected to the sink of the second P - channel transistor the source of which is connected to VDD line of power supply voltage, source of the first N - channel transistor is connected to the sink of the second N - channel transistor the source of which is connected to GND ground line, to the gate of the second P - channel transistor there supplied is control voltage of P - channel transistor, to the gate of the second N - channel transistor there supplied is control voltage of N - channel transistor, the gate of the third P - channel transistor and the gate of the third N - channel transistor are connected to inverter output, the source of the third P - channel transistor is connected to the sink of the second P - channel transistor, the sink of the third P - channel transistor is connected to ground line, the source of the third N - channel transistor is connected to the sink of the second N - channel transistor, the sink of the third N - channel transistor is connected to power supply voltage line.

EFFECT: development of compact annular controlled producer with low constant value and low pulsation level of the consumed current, which has quadruple covering of operating frequency range in which change of inclination of modulation characteristic does not exceed value two.

12 dwg

Description

The present invention relates to integrated electronic technology and can be used as part of micro-consuming high-frequency devices for clock synchronization of digital circuits. Recently, much attention has been paid to the development of CMOS chips with high integration of the functions performed, called a system on a chip (SoC). One of the problems encountered in the design of SoCs is the noise relationship between circuits located close to the chip.

As the source of clock synchronization for SoC microcircuits, the most widely used are devices based on a voltage controlled oscillator (VCO), the frequency of the oscillation signal of which is stabilized using a phase-locked loop (PLL). It is often required that the operating frequency range of the VCO overlap at least twice, and the duty cycle of the oscillation signal be close to 0.5. Due to the fact that the slope of the VCO modulation characteristic is the coefficient of its transmission in the PLL, for stable operation of the circuit it is preferable that within the operating frequency range the change in the slope of the modulation characteristic does not exceed two times. The generator must have guaranteed self-excitation.

To reduce the sensitivity to noise from other circuits and not to be a noise source itself, the VCO must meet the following requirements:

- in the entire operating frequency range, have the same and equal to the supply voltage amplitude of the oscillation signal occurring relative to the level of half of the supply voltage, the duration of the front and fall of the oscillation should be approximately equal;

- work at low supply voltages (for example, 1.8 V) and consume low power (up to 250 μW);

- have a small pulsed current consumption;

- during the restructuring of the VCO should have low inertia. In order to save space on the SNK chip, only CMOS transistors should be used in the VCO circuit.

Known ring CMOS VCO circuits are described in US Pat. 2] and No. 5764110 "Voltage Controlled Ring Oscillator Stabilized Against Supply Voltage Fluctuations", IPC Н03В 5/04 [3]. A common feature with the claimed invention is the presence of an odd number of inverters with controlled switching current connected in a ring that provides negative DC feedback. The frequency of the oscillation signal is determined by the number of inverters in the ring and the switching delay of each of them. The switching delay is determined by the value of the switching current and the value of the equivalent load capacitance. Switching current is controlled in all generator inverters at the same time.

The inverter circuit [1] and [2] is shown in FIG. 1A, the inverter circuit [3] is shown in FIG. 1B. The inverter includes the first and second P-channel transistors and the first and second N-channel transistors, the gates of the first P-channel transistor and the first N-channel transistor are connected and form the inverter input In, the drains of the first P-channel transistor and the first N-channel transistors are connected and form the output of the inverter. The source of the first P-channel transistor is connected to the drain of the second P-channel transistor, the source of which is connected to the supply voltage line VDD. The source of the first N-channel transistor is connected to the drain of the second N-channel transistor, the source of which is connected to the GND ground line. The inverter switching current, and therefore the frequency of the oscillation signal, is limited by the control signals Pcon and Ncon. In the invention [3], the source of the first P-channel transistor is additionally connected to the elements of circuit 1 supporting constant voltage on it.

However, these generator circuits have disadvantages. In [1], when the generating ring is operating in the lower part of the frequency range, the necessary switching delay of each inverter is achieved by stretching the front and decay of the oscillation signal, which leads to a decrease in its amplitude. To avoid this and expand the frequency range in the invention [2], an additional control signal is used that changes the number of inverters in the generating ring, which complicates the VCO control circuit. In the inventions [1] and [2], each inverter forming a generating circuit has a pulsed current consumption, and in the invention [3] to smooth the pulsed consumption and reduce sensitivity to changes in the supply voltage, the oscillation amplitude is maintained less than the supply voltage, which is a disadvantage of this circuit .

The closest technical solution to the claimed invention is a ring CMOS VCO circuit described in US patent No. 6271730 "Voltage-Controlled Oscillator Including Current Control Element", IPC Н03В 1/00 [4]. This scheme is selected as a prototype of the claimed invention and is shown in figure 2. Each inverter contains the first, second and third P-channel transistors and the first, second and third N-channel transistors, the gates of the first P-channel transistor and the first N-channel transistor are connected and form the inverter input In, the drains of the first P-channel transistor and the first N-channel transistors are connected and form the inverter output Out, the source of the first P-channel transistor is connected to the drain of the second P-channel transistor, the source of which is connected to the supply voltage line VDD, the source of the first N-channel transistor dinene with the drain of the second N-channel transistor, the source of which is connected to the GND ground line, the source of the third P-channel transistor is connected to the supply voltage line, and its drain through the first resistor is connected to the inverter output, the gates of the second and third P-channel transistors are connected and they are supplied with the control voltage of the P-channel transistors Pcon, the source of the third N-channel transistor is connected to the ground line, and its drain through the second resistor is connected to the inverter output, the gates of the second and third N-channel transistor The s are connected and the control voltage of the N-channel transistors Ncon is applied to them. The invention [4] is aimed at reducing the level of pulsed current consumption, the oscillations are carried out relative to half the supply voltage, however, the amplitude of the oscillation signal is not constant and, according to the principle of operation, is lower than the supply voltage.

The technical result of the present invention is the creation of a compact ring CMOS VCO with a low constant value and low ripple current consumption, having fourfold overlap of the operating frequency range, in which the change in the slope of the modulation characteristic does not exceed two. The generator maintains a constant, close to the symmetrical amplitude of the oscillation signal, equal to the supply voltage, and is able to quickly rebuild within the operating range.

This result is achieved due to the fact that in the VCO, consisting of the inverters described in the invention [4], connected in a ring that provides negative DC feedback, where each inverter contains: the first, second and third P-channel transistors and the first , the second and third N-channel transistors, the gates of the first P-channel transistor and the first N-channel transistor are connected to each other and form the inverter input, the drains of the first P-channel transistor and the first N-channel transistor are connected th and form the inverter output, the source of the first P-channel transistor is connected to the drain of the second P-channel transistor, the source of which is connected to the supply voltage line, the source of the first N-channel transistor is connected to the drain of the second N-channel transistor, the source of which is connected to the ground line , the control voltage of the P-channel transistor is supplied to the gate of the second P-channel transistor, the control voltage of the N-channel transistor is supplied to the gate of the second N-channel transistor, the gate of the third R-channel is proposed connect the transistor and the gate of the third N-channel transistor to the inverter output, connect the source of the third P-channel transistor to the drain of the second P-channel transistor, connect the drain of the third P-channel transistor to the ground line, connect the source of the third N-channel transistor to the drain of the second N-channel transistor, the drain of the third N-channel transistor is connected to the supply voltage line.

Thus, in a circular VCO, built on the basis of the proposed inverter, two principles of regulation of the frequency of the oscillation signal operate simultaneously: the well-known from the prototype [4], when the frequency value depends on the duration of the rise and fall of the oscillation signal and the new one when the generation frequency depends on the input inverter switching levels. The principle of the dependence of the frequency on the inverter switching input levels is as follows: when generating frequencies from the upper part of the operating range, the values of the input levels approach each other when the inverter is switched up and down, and diverge when generating frequencies from the lower part of the range. This, with a smaller change in the durations of the front and decay of the oscillation signal, gives the effect of expanding the operating frequency range of the generator, and the amplitude of the oscillation signal is constant and equal to the supply voltage. The presence of different input switching levels of the inverter guarantees self-excitation of the generator. Due to the fact that, limited by control signals, the current through the inverter flows continuously, during the operation of the generator the ripple of the current consumption decreases. High speed tuning of the oscillation frequency is determined by the low inertia of the circuit elements.

The invention is illustrated by the following graphic materials: Figa. The circuit of the inverter with a controlled switching current, presented in the inventions [1, 2].

Figb. The inverter circuit with a controlled switching current, presented in the invention [3].

Figure 2. The inverter circuit with a controlled switching current, presented in the invention [4], selected as a prototype of the claimed invention.

Figure 3. The inverter circuit with a controlled switching current, as claimed in this invention.

Figa. Diagrams showing the change in the voltage level Vnls at the source of the transistor N1 from a change in the normalized control voltage Ncon and the value of the current flowing through the inverter Ivdd. Low voltage is applied to the In input of the inverter.

Figb. Diagrams showing the change in the voltage level Vpls at the source of the transistor P1 from a change in the normalized control voltage Pcon and the value of the current flowing through the inverter Ivdd. High voltage is applied to the In input of the inverter.

Figure 5. The connection option of the inverter claimed in this invention for the formation of a wide-range VCO ring.

Figa, 6B, 6B. Diagrams of the signals of the generated oscillation Fout and the current Ivdd consumed by the generator at normalized control voltages Pcon and Ncon equal to 250 mV, 370 mV and 615 mV.

7. The current consumed by the generator in the entire range of operating frequencies, as well as the type of modulation characteristic in a logarithmic (top) and linear scale.

Fig. 8. Diagrams illustrating the rate of change of the frequency of the signal of the oscillation Fout with a jump-like change in the control voltages Pcon and Ncon.

The inventive circuit of the inverter with a controlled switching current is shown in Fig.3. The inverter includes: the first P-channel transistor P1 and the first N-channel transistor N1, the gates of which are connected and form the input In of the inverter, the drain of the first P-channel transistor P1 and the drain of the first N-channel transistor N1 are connected and form the output Out of the inverter, the drain of the first P-channel transistor P1, the drain of the second P-channel transistor P2 and the source of the third P-channel transistor P3 are interconnected, the source of the first N-channel transistor N1, the drain of the second N-channel transistor N2 and the source of the third N-channel transistor N3 are interconnected, the source of the second P-channel transistor P2 and the drain of the third N-channel transistor N3 are connected to the output voltage terminal VDD, the source of the second N-channel transistor N2 and the drain of the third P-channel transistor P3 are connected to the GND terminal of the earth, the gate of the second The P-channel transistor P2 is connected to the current control terminal Pcon of the P-channel transistor, the gate of the second N-channel transistor N2 is connected to the current control terminal Ncon of the N-channel transistor, the gate of the third P-channel transistor P3 and the gate of the third N-to the anal transistor N3 is connected to the Out terminal of the inverter.

The claimed invention works as follows. Suppose that a positive voltage is applied to the VDD terminal relative to the GND terminal, a current control voltage of the P-channel transistor is supplied to the terminal Pcon, and a current control voltage of the N-channel transistor is supplied to the terminal Ncon. If there is a low level of voltage at the inverter input In, the channel of transistor N1 is closed, and the channel of transistor P1 is open, and through it and transistor P2, the inverter output Out is pulled to a high level of supply voltage VDD. The high level potential at the inverter output Out closes the channel of transistor P3 and opens the channel of transistor N3. Through the transistors N2 and N3, a current flows from the VDD pin to the GND pin, limited by the voltage of the control signal at the Ncon pin. In this case, the voltage level at the source of transistor N1 depends on the resistance value of the open channel of transistor N3 and the magnitude of the flowing current. The lower the value of the flowing current, the higher the voltage level at the source of the transistor N1 and the higher the level of switching of the inverter with a subsequent increase in voltage at the input of the inverter.

If there is a high level voltage at the input In of the inverter, the channel of the transistor P1 is closed, and the channel of the transistor N1 is open and through it and the transistor N2, the output terminal of the inverter is pulled to a low ground GND. The low level potential at the inverter output Out closes the channel of transistor N3 and opens the channel of transistor P3. Through the transistors P2 and P3, a current flows from the VDD terminal to the GND terminal, limited by the voltage of the control signal at the Pcon terminal. The voltage level at the source of the transistor P1 depends on the resistance value of the open channel of the transistor P3 and the magnitude of the flowing current. The lower the value of the flowing current, the lower the voltage level at the source of the transistor P1 and the lower the level of switching of the inverter with a subsequent decrease in voltage at the input In of the inverter.

Thus, when the voltage value of the control signals at the Pcon and Ncon terminals changes, not only does the inverter switching current, which determines the duration of the rise and fall, change, but also the voltage levels at the In input of the inverter necessary to switch it change, and the current from VDD to GND output flows continuously.

Diagrams showing the change in the levels of Vnls and Vpls at the sources of the transistors N1 and P1 from the change in the control voltages Ncon and Pcon and the values of the current Ivdd flowing through the inverter are presented in Figs. 4A and 4B. Fig. 4A shows a situation where a low level voltage is applied to terminal In, and Fig. 4V, when a high level voltage is applied to terminal In. For convenience, the corresponding values of the threshold voltages P and N-channel transistors are subtracted from the voltage values Pcon and Ncon, and we will call these quantities normalized below. The presented results were obtained using Specter modeling.

To form a generating ring, an odd number of inverters shown in FIG. 3 are connected, as shown in FIG. 5. The generated oscillation signal can be removed from the Out terminal of any inverter.

A wide range of generated frequencies is provided as follows. Due to the negative DC feedback, forced oscillations occur in the ring. The frequency of the oscillation signal depends on the value of the switching current, the value of the equivalent load capacitance and the switching thresholds of the inverters. When a low-frequency signal is generated, due to the small value of the switching current, not only the edge and decay of the oscillation signal are obstructed, but also the inverters of the switching thresholds diverge, which leads to an even greater increase in the propagation delay of the signal, and therefore, to a decrease in the oscillation frequency. When a high-frequency signal is generated with a large value of the switching current, not only the edge and decay of the oscillation signal sharpen at the same time, but also the switching thresholds of the inverters come closer, which leads to a decrease in the propagation delay of the signal and, therefore, to an increase in the oscillation frequency. The result of the interaction of these factors is the expansion of the generation frequency range, the amplitude of the generated signal is kept constant and close to the value of the supply voltage.

On figa, 6B, 6B presents a diagram of the waveforms of the oscillation Fout and the current consumption Ivdd circuit generator shown in Fig.5. The diagrams are presented for normalized control voltages of 250 mV, 370 mV and 615 mV. With a normalized control voltage of 250 mV, the oscillation signal frequency is 400 MHz with an average consumption current of 51.2 μA and a current ripple of less than ± 7%. At a voltage of 370 mV, the frequency is 800 MHz, the average current is 76.5 μA, the ripple does not exceed ± 4%. At a voltage of 615 mV, the frequency is 1600 MHz, the average current is 109.5 μA, the ripple does not exceed ± 6%. In all three cases, the amplitude of the oscillation signal is close to the supply voltage VDD equal to 1.8 V. The duty cycle of the oscillation signal at the level of half the supply voltage lies in the range 0.49 ... 0.51.

The magnitude of the current consumed by the generator in the entire range of operating frequencies, as well as the modulation characteristic of the generator are presented in Fig.7. For the operating frequency range, an interval from 400 MHz to 1600 MHz is adopted. In the upper part of the drawing, the frequency of the oscillation signal is presented on a logarithmic scale. Twice changing the slope of the modulation characteristic is quite acceptable for building a stable PLL circuit.

On Fig presents diagrams illustrating the high dynamic rate of change of the frequency of the oscillation signal during a jump change in control voltage.

The proposed circuit design of the inverter ring VCO, due to the additional use of changing the input switching levels, allows you to get four-fold overlap of the operating frequency range of the generator. The amplitude of the oscillation signal is maintained constant and equal to the supply voltage. Close to symmetrical oscillation is carried out relative to the level of half the supply voltage with a duty cycle of 0.49 ... 0.51. The generator has a small constant value and small ripple current consumption. The combination of these qualities allows us to create devices of clock synchronization sources on the same chip with other digital and analog SoC blocks on the basis of this CMOS VCO.

However, the scope of the present invention is not limited to this. The described inverter can also be used in telecommunication and radio frequency systems, frequency synthesizers and other devices where an inverter with a controlled switching delay is required.

Claims (1)

A voltage-controlled broadband ring oscillator in which an odd number of CMOS inverters with a controlled switching current are connected in series in a ring providing negative DC feedback, each inverter contains first, second and third P-channel transistors and first, second and third N- channel transistors, the gates of the first P-channel transistor and the first N-channel transistor are interconnected and form the inverter input, the drains of the first P-channel transistor and the first N-channel transistors are interconnected and form an inverter output, the source of the first P-channel transistor is connected to the drain of the second P-channel transistor, the source of which is connected to the supply voltage line, the source of the first N-channel transistor is connected to the drain of the second N-channel transistor, the source of which is connected to the ground line, the control voltage of the P-channel transistor is supplied to the gate of the second P-channel transistor, the control voltage of the N-channel transistor is supplied to the gate of the second N-channel transistor nzistor, characterized in that the gate of the third P-channel transistor and the gate of the third N-channel transistor are connected to the output of the inverter, the source of the third P-channel transistor is connected to the drain of the second P-channel transistor, the drain of the third P-channel transistor is connected to ground lines, the source of the third N-channel transistor is connected to the drain of the second N-channel transistor, the drain of the third N-channel transistor is connected to the supply voltage line.

Images