RU2357372C1 - Start-stop communication system with signal frequency keying - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: proposed start-stop communication system pertains to wireless communication and can be used in different communication lines. The start-stop communication system with signal frequency keying has on the transmission side an information source, first shift register, OR circuit, carrier frequency generator, transmitter, first trigger flip-flop, first AND circuit and a pseudorandom sequence generator. On the receiving side, the system has a receiver, frequency discrimination circuit, interrupter switch, matched filter, decision device, pulse former, non-linear element, first adder, delay line, second adder, threshold device, RS-trigger, first key, comparator, second shift register, second key, minimum signal selection circuit, N switches, second trigger flip-flop and a second AND circuit.

EFFECT: increased noise immunity of communication.

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Description

The invention relates to electrical and radio communications and can be used in wired radio, radio relay and meteor communication lines.

A known communication system for the continuous transmission of discrete information, in which a sounding key is sent before each message. If this signal arrives, the receiver opens to register the message and after receiving it sends a receipt on the return channel. Otherwise, the receiver remains closed and the transmitter repeats the message, continuing to try to obtain the desired receipt [1]. However, such a communication system has low noise immunity, and in start-stop mode - an unacceptably high probability of false alarm.

The closest in technical essence to the proposed communication system is a start-stop communication system with frequency-shift keying [2], adopted as a prototype.

The scheme of the prototype system is presented in figure 1, where indicated

on the transmitting side:

1 - source of information;

2 - the first shift register (PC);

3 - OR scheme;

4 - carrier frequency generator (LFO);

5 - transmitter;

8 - pseudo-random sequence generator (GPSP);

on the receiving side:

9 - receiver;

10 - frequency discriminator (BH);

11 - breaker;

12 - matched filter (SF);

13 - a decisive device (RU);

14 - pulse shaper (FI);

15 - non-linear element (NE);

16 - the first adder;

17 - delay line (LZ) with n taps;

18 - second adder;

19 - threshold device (PU);

20 - RS-trigger;

21 is the first key;

22 - a comparator;

23 - second PC;

24 - the second key;

29 - communication line.

The prototype system contains on the transmitting side: a source of information 1, a first PC 2, an OR 3 circuit, an LFO 4 and a transmitter 5, as well as a GPS 8, whose output is connected to the second input of the OR 3 circuit, the second output of information source 1 being connected in series with a clock input of the first PC 2 and the first input of the GPS 8, the second input of which is connected to the third output of the information source 1 and the second input of the transmitter 5, and on the receiving side contains: serially connected receiver 9, BH 10, chopper 11, SF 12, RU 13 and FI 14, sequentially connect ennye NE 15, the first adder 16 and LZ 17, serially connected second adder 18, the first n inputs of which are connected via a bus 17 to the outputs LZ, and (n + 1) th input is connected to its input; PU 19 and RS-trigger 20; the second key 21 and the serially connected comparator 22, the second PC 23 and the second key 24, the output of which is the output of the system, the first output of FI 14 is connected to the clock inputs of the comparator 22 and the second PC 23, and its second output is connected to the second inputs of the chopper 11 and PU 19, the output of the BH 10 is connected to the signal input of the comparator 22 and the input of the NE 15, the output of the SF 12 is connected to the first input of the first key 21, the second input of the first key 21 is combined with the output of the RU 13 and the second input of the RS flip-flop 20, and its output is connected to the second input of the first adder 16, the output of the RS-trig EPA 20 is connected to the second input of the second switch 24; the receiving and transmitting sides of the system are connected via a communication line 29. The prototype system operates as follows.

Information source 1 at a random moment in time creates a message at the first output consisting of n binary symbols of the same duration τ, and at the second and third outputs at the time of the beginning of the message, a grid of S short pulses with a repetition period τ and a positive pulse, respectively. At the same time, a synchronization signal is formed in GPSP 8 — a pseudo-random binary sequence consisting of S elements of duration τ, and the message is delayed in PC 2 for a time equal to Sτ. As a result of this, a sequence consisting of a clock signal and a message is formed at the output of the OR 3 circuit. Elements of these signals are used to control the frequency of the LFO 4. The obtained frequency-manipulated signal is amplified in the transmitter 5, turned on by a pulse of duration (n + S) τ, acting on the third output of the information source 1, and transmitted via communication line 29.

On the receiving side, after general filtering in the receiver 9, the received signal is demodulated in BH 10 and the synchronized signal is filtered in SF 12, which together with block 13 constitutes the first measuring channel, which is an optimal measurement device for the temporal position of the clock signal (see, for example, page 115, Fig. 7.2 in the book of Yu.S. Lezin “Introduction to the theory and technique of radio engineering systems”, M., “Radio and communications”, 1986).

RU 13 compares the input signal with a certain threshold and, if it is exceeded by the signal, generates a short pulse at the moment of its maximum value, which, in the absence of interference, exactly coincides in time with the end of the clock signal at reception. A positive edge of this pulse at the first output of FI 14 with a delay of time τ creates a grid of 2n short clock pulses of duration α (α << τ) with a period τ, and at the second one, a pulse of duration nτ + 2α, which disconnects using the interrupt 11 input SF 12 from the output of block 10. In the comparator 22 at the time of the first n output clock pulses of block 14, according to the sign of the output signals of BH 10, decisions are made to receive n binary message symbols, which are written in the same pulses to the (n + 1) -bit PC 23, the next n clock pulses read information from PC 23 to the first input of the second key 24. The output signal of the SF 12 at the time of the output pulse RU 13 from the output of the first key 21 through the first adder 16 enters L3 17 with n taps, the distance between which (in time) is τ.

In NE 15, the modular values of the elements of the output signal BH 10 are calculated, which through the same adder 16 go to the input of the LZ 17. Then the input signal LZ 17 and the output signals from n of its outputs are summed in the second adder 18 and the received signal at the moment of the trailing edge of the pulse at the second output, FI 14 is compared in PU 19 with a certain threshold. If it exceeds the threshold, the RS-trigger 20, set by the output pulse of the RU 13 to the zero state, is transferred to the single state. At the same time, key 24 is opened and information from its first input is transmitted to its output. If the threshold in the control unit 19 is not exceeded by the signal, then the input signal of block 24 will not be output.

The disadvantage of the prototype system is the low noise immunity of the communication.

The invention is aimed at improving the noise immunity of communication.

To achieve this, a start-stop communication system with frequency-shift keying signal (MSSM), containing on the transmitting side a series-connected information source, a first PC, an OR circuit, an LFO and a transmitter, as well as GPS, the output of which is connected to the second input of the OR circuit, the second output the information source is connected to the clock input of the first PC and the first input of the GPS, the second input of the GPS is connected to the third output of the information source and the second input of the transmitter, and on the receiving side, the receiver, BH, interrupts are connected in series Atelier SF, PN and PI; series-connected NEs, the first adder and LZ; connected in series to the second adder, the first n inputs of which are connected via bus to the n outputs of the LP, and the (n + 1) -th input is connected to the input of the LP, a threshold device and an RS-trigger; the first key and the comparator in series, the second PC and the second key, the output of which is the output of the MSSM, the first FI output connected to the clock inputs of the comparator and the second PC, and its second output connected to the second inputs of the chopper and the control panel, the BH output is connected to the signal input comparator and NE input, the SF output is connected to the first input of the first key, the second input of the first key is combined with the RU output and the second input of the RS trigger, and the output of the first key is connected to the second input of the first adder, the output of the RS trigger is connected to the second second input of the second key; The receiving and transmitting sides of the MSSM are connected via a communication line, according to the invention, they are introduced on the transmitting side: the fourth output of the information source, the third input of the OR circuit, and the first T-trigger and the first circuit And, the second input of which is connected to the fourth output of the information source, and the output connected to the third input of the OR circuit, and the counting input of the first T-trigger is connected to the output of the first PC, and its installation input is connected to the third output of the information source, and at the receiving side it is additionally entered : (n + 1) -th tap of the LH, 2n installation inputs and n outputs of the second PC, (n + 2) -th input of the second adder connected to the (n + 1) -th tap of the LH, minimum signal selection circuit (CBM) connected by n inputs through the bus with the first n outputs of the LZ, and (n + 1) -th - with the input of the LZ, n switches, each of which is connected by the first input to the corresponding output of the CBM, the second - from the corresponding output of the second PC, and a pair of outputs - with the corresponding pair of installation inputs of the second PC; the second T-trigger connected in series with the counting input to the output of the comparator, and the installation input to the output of the switchgear, and the second circuit I, the output of which is connected to the gate input of the CBM, and the second input is connected to the output of the control panel.

Figure 2 presents the functional diagram of the proposed SSSM.

It contains on the transmitting side a series-connected information source 1, a first PC 2, an OR 3 circuit, an LFO 4 and a transmitter 5; the first T-flip-flop 6 and the first And 7 circuit are connected in series, the second input of which is connected to the fourth output of the information source 1, and the output is connected to the third input of the OR 3 circuit, and the counting input of the first T-flip-flop 6 is connected to the output of PC 2, and its installation input is combined with the third output of the information source 1 and the second input of the transmitter 5; GPSSP 8, the first input of which is combined with the clock input of PC 2 and connected to the second output of the information source, the second input is connected to the third output of the information source 1, and the output is connected to the second input of the OR 3 circuit, and on the receiving side it contains: series-connected receiver 9 , BH 10, chopper 11, SF 12, RU 13 and FI 14; connected in series NE 15, the first adder 16 and LZ 17; connected in series to the second adder 18, the first n inputs of which are connected through the bus to the n outputs of the LZ 17, the (n + 1) -th input is connected to the input of the LZ 17, and the (n + 2) -th - to the (n + 1) -m the output of the LZ 17, PU 19 and RS-trigger 20; the first key 21 and the comparator 22 connected in series, the second (n + 2) -bit PC 23 and the second key 24, the output of which is the output of the MSSM, the first output of FI 14 being connected to the clock inputs of the comparator 22 and the second PC 23, and its second output connected to the second inputs of the chopper 11 and PU 19, the output of the BH 10 is connected to the signal input of the comparator 22 and the input of the NE 15, the output of the SF 12 is connected to the first input of the first key 21, the second input of which is combined with the output of the RU 13 and the second input of the RS-flip-flop 20 , and its output is connected to the second input of the first adder 16, the output RS flip-flop 20 is connected to the second input of the second key 24; and also contains: CBM 25, connected by n inputs through the bus with the first n outputs of LZ 17, and (n + 1) -th - with the input of LZ 17, n switches (26-1) - (26-n), each of which connected to the first input with the corresponding output of CBM 25, the second to the corresponding output of PC 23 (starting from the output of the second discharge), and the pair of outputs to the corresponding pair of installation inputs of PC 23 (starting from the pair of installation inputs of the second discharge); connected in series to the second T-flip-flop 27, connected by a counting input to the output of the comparator 22, and the installation input to the output of the RU 13, and a second circuit And 28, the output of which is connected to the gate input of the CBM 25, and the second input to the output of the PU 19; the receiving and transmitting sides of the MSSM are connected via a communication line 29.

Start-stop communication system with frequency signal manipulation works as follows.

Information source 1 at a random moment in time creates a message at the first output consisting of n-binary symbols of the same duration τ, at the second and third outputs at the time the message starts, a grid of S short pulses with a repetition period τ and a positive pulse, respectively, and the fourth is an impulse of duration τ at the moment the last impulse acts on its second output.

At the same time, a synchronization signal is formed in GPSP 8 — a pseudo-random binary sequence consisting of S elements of duration τ, and the message is delayed in PC 2 for a time equal to Sτ.

If the number of characters “1” in the message is odd, then the T-trigger 6, set by the leading edge of the pulse acting on the third output of the information source 1 to state “0”, goes into state “1” and this signal passes through the first circuit AND 7 to the third input of the OR circuit 3 is a pulse from the fourth output of the information source 1, which is a check symbol of the code. With an even number of characters “1” in the message, the pulse will not arrive at the third input of the OR 3 circuit. As a result of all this, at the output of the OR 3 circuit, a sequence is formed consisting of a clock signal, a message, and the symbol “1” or “0” (depending on the number of characters “1” in the message). Elements of these signals are used to control the frequency of the LFO 4. The resulting frequency-manipulated signal is amplified in the transmitter 5, which is switched on by a pulse of duration (n + S + 1) τ, acting on the third output of the information source and transmitted via communication line 29.

On the receiving side, after general filtering in the receiver 9, the received signal is demodulated in BH 10 and the synchronized signal is filtered in SF 12, which, together with block 13, makes up the first measuring channel the same as in the prototype system. RU 13 compares the input signal with a certain threshold and, if it is exceeded by the signal, generates a short pulse, duration α, at the moment of its maximum value, which, in the absence of interference, exactly coincides in time with the moment of receiving the clock signal at reception. On the positive front of this pulse, a grid of [(n + 1) + n] short clock pulses of duration α with a period of τ is created at the first output of FI 14 with a delay of time τ, and a pulse of duration (n + 1) τ + 0.5α, which, using a chopper 11, disconnects the input of the SF 12 from the output of block 10. In the comparator 22, at the time of the leading edges of the first (n + 1) output clock pulses of block 14, the decisions on the reception of n binary message characters and code verification character, which are written in the same pulses in ( n + 2) -bit PC 23. The output signal of the SF 12 at the time of the output pulse of RU 13 from the output of the first key 21 through the first adder 16 enters LZ 17 with (n + 1) taps, the distance between which (in time) is τ .

NE 15 calculates the modular values of the elements of the output signal BH 10, which through the same adder 16 are fed to the input LZ 17. Then the input signal LZ 17, the output signals from the first n of its inputs (bus) and the output signal of the (n + 1) th additional output are summarized in the second adder 18 and the received signal at the time of the trailing edge of the pulse at the second output of FI 14, are compared in the PU 19 with a certain threshold. If it exceeds the threshold, the RS-trigger 20, set by the output pulse of the RU 13 to the zero state, is transferred to the single state. This opens the key 24. If the threshold in the control room 19 by the signal is not exceeded, then the key 24 does not open. Blocks 25, 26, 27 and 28 are designed to detect and correct a single error in the received code combination. To this end, the input signal LZ 17 and its output signals (via the bus) from the n-first taps are fed to the inputs of the CBM 25, and (n + 1) output binary symbols of block 22 are sent to the first input of the second T-trigger 27. If the number of characters is “ 1 ”turns out to be odd (which indicates a distortion of the code combination interference), then at the output of the second circuit And 28, at the moment of the leading edge of the output signal of the PU 19, the voltage drop will act and in the CBM 25 the output signal number will be sampled with the lowest level, so that only on one of her exits will there be action pulse with level “1”, and on the rest - zero signal.

This pulse will be fed to the input of the corresponding switch 26, to the second input of which the output signal of the corresponding discharge PC 23 is supplied, and if its level, for example, will be equal to “1”, then the pulse from the first input of the switch will go to one of the pair of its outputs, which will set the corresponding discharge PC 23 to the opposite state. This will correct the erroneously received character. The last n output pulses from the first output of FI 14 information from PC 23 will be read through the public key 24 to the output of the communication system. Naturally, such a method of error correction does not allow correcting them with a probability equal to unity. However, the calculations showed that with real signal-to-noise ratios in the 12-14 dB communication channel, the probability of erroneous message reception is less than in the prototype system by almost an order of magnitude. Moreover, the comparison of the two systems was carried out at the same energy costs during transmission. This advantage of the proposed system compared to the known one is illustrated by the curves of the probability of erroneous reception of the message P (for n = 12) on the ratio s / w h (where the dashed line shows the curve for the proposed system and the solid line for the known) obtained by statistical modeling.

Thus, the application of the proposed start-stop communication system with frequency signal manipulation allows to increase the noise immunity of the communication.

Information sources

1. Kanevsky Z.M., Ledovskikh V.I. Transfer of discrete information on channels with feedback with interruptions. "Telecommunication", No. 2, 1970

2. G. B. Volobuev, V. I. Ledovsky. On noise immunity of start-stop communication systems with frequency signal manipulation. “Theory and technique of radio communication”, issue No. 2, 1998

Claims (1)

A start-stop communication system with frequency-shift keying of the signal, comprising, on the transmitting side, a source of information, a first shift register, an OR circuit, a carrier frequency generator and a transmitter, and a pseudo-random sequence generator whose output is connected to the second input of the OR circuit, the second output of the information source connected to the clock input of the first shift register and the first input of the pseudo-random sequence generator, the second input of the pseudo-random sequence generator connected to the third output of the information source and the second input of the transmitter, and on the receiving side there are serially connected receiver, frequency discriminator, chopper, matched filter, resolver and pulse shaper; serially connected non-linear element, the first adder and the delay line; connected in series to the second adder, the first n inputs of which are connected via bus to the n outputs of the delay line, and the (n + 1) -th input is connected to the input of the delay line, a threshold device and an RS-trigger; the first key and the comparator in series, the second shift register and the second key, the output of which is the output of the communication system, the first output of the pulse shaper connected to the clock inputs of the comparator and the second shift register, and its second output connected to the second inputs of the chopper and threshold device, output the frequency discriminator is connected to the signal input of the comparator and the input of the nonlinear element, the output of the matched filter is connected to the first input of the first key, the second input of the first key is combined nen with the output of the solving device and the second input of the RS-trigger, and the output of the first key is connected to the second input of the first adder, the output of the RS-trigger is connected to the second input of the second key; the receiving and transmitting sides of the communication system are connected via a communication line, characterized in that the fourth output of the information source, the third input of the OR circuit, and the first T-trigger and the first And circuit, the second input of which is connected to the fourth output, are connected in series on the transmitting side information source, and the output is connected to the third input of the OR circuit, and the counting input of the first T-trigger is connected to the output of the first shift register, and its installation input is connected to the third output of the information source, and at the receiving Orone additionally introduced: (n + 1) -th tap of the delay line, 2n installation inputs and n outputs of the second shift register, (n + 2) -th input of the second adder connected to the (n + 1) -th tap of the delay line, circuit select the minimum signal, connected by n inputs through the bus with the first n outputs of the delay line, and (n + 1) -m with the input of the delay line, n switches, each of which is connected by the first input to the corresponding output of the minimum signal selection circuit, the second - with the corresponding output of the second shift register, and the pair of outputs with the corresponding pair oh installation inputs of the second shift register; a second T-trigger connected in series with the counting input to the output of the comparator, and the installation input to the output of the deciding device, and a second AND circuit, the output of which is connected to the gate input of the minimum signal selection circuit, and the second input is connected to the output of the threshold device.

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