RU2333531C1 - Analog-digital multiprocessor device for calculation of discrete fourier transformation - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention refers to the means of specialised calculation equipment and can be used for real-time spectrum analysis of the signals. The technical result is reached due to calculation of real, imaginary part and pulse height of k signal spectrum harmonic. So far as the calculation time is inversely related to maximum tolerance frequency of the input informative signal, then reduction of the processing time leads to increase of maximum tolerance frequency of the input signal. The device contains 2 processors, performing folding the input signal with specific coefficients, and one processor, performing calculation of k spectrum harmonic pulse height. The outputs of the device are informative outputs of the first two processors, real and imaginary parts of k spectrum harmonic in the analog form, and informative outputs of the third processor - k spectrum harmonic pulse height in digital and analog form.

EFFECT: increase of performance and input signal spectrum enhancement due to vectorisation of calculation of real and imaginary parts and introduction of staging.

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Description

The invention relates to specialized computer technology and may find application in the spectral analysis of signals in real time.

Known devices [1] and [2], allowing to perform discrete Fourier transform. The disadvantages of the devices include the lack of a result of calculating the harmonic amplitude of the signal in analog form and the sequential calculation of the real and imaginary parts of the harmonic.

The closest in technical essence is a device for performing discrete Fourier transform [3]. Upon receipt of the trigger signal, the device selects the input value and sequentially calculates the real and imaginary parts and the amplitude of the kth harmonic of the Fourier spectrum.

The prototype has the following disadvantages: the device performs the operations of calculating the real and imaginary parts and the result module sequentially in time. Because the maximum allowable frequency of the input information signal in this problem is inversely proportional to the calculation time, then reducing the processing time will increase the maximum allowable frequency of the input analyzed signal.

The purpose of the invention is to increase the speed of the prototype and expand the spectrum of the input analyzed signal by 2 times by parallelizing the calculation of the real and imaginary parts and introducing pipelining.

The device is designed to determine the real and imaginary components of the harmonics of the expansion of the measured quantity in a discrete Fourier series in accordance with the expressions

In addition, the device provides the calculation of both the sine and cosine components of the harmonics of the expansion of the signal in a Fourier series in accordance with (1), and the absolute amplitude of the signal harmonic

The drawing shows a structural diagram of a device.

The device comprises a sampling unit 1, a controlled inversion unit 2, a scaling potentiometer 3, two scaling resistors 4 and 5, an operational amplifier 6, two sampling units 7 and 8, a switch 9, a read-only memory unit 10, combined into a first processor of the first type, a reference source voltage 11, switch 12, controlled inversion unit 13, scaling potentiometer 14, successive approximation register 15, comparator 16, two scaling resistors 17 and 18, operational amplifier 19, two switches 20 and 21, four sampling units 22, 23, 24, 25 two comm tator 26 and 27, combined into a second processor, delay unit 28, register 29, clock 30, element 31, first and second counters 32 and 33, second read-only memory 34, second register 35, second element 36 , a third counter 37, a third read-only memory unit 38 integrated into a control unit, a sampling unit 39, a controlled inversion unit 40, a scaling potentiometer 41, two scaling resistors 42 and 43, an operational amplifier 44, two sampling units 45 and 46, a switch 47, a read-only memory unit 48 combined in a second processor first th type.

The device operates as follows.

By an external start signal supplied to the Start input, the device switches to its initial state, in which the counters 32 and 33 are reset (zeroed) at the R inputs. Next, the start signal with a delay in element 28 switches (arming) the register 29, which releases the And 31 element The clock pulses of the generator 30 begin to arrive at the counting input from the counter 33. The outputs of the counter 33 are connected to the address inputs of the read-only memory 34, the outputs of which are connected to the control inputs of the blocks 1, 7, 8, 9, 39, 45, 46, 47 and the clock the input of the counter 32. Thus At least the counter account 33 to permanent memory unit 34 having outputs signals that control operation of the first and second processors of the first type, calculating the real and imaginary parts of the k-th harmonic of the Fourier spectrum. Upon completion of the calculation of the real and imaginary parts from N samples at the output P of the counter 32, a signal is set that sets “1” register 35 at the input S, the element And 36 passes the clock pulses to the counter 37, the output of which goes to the read-only memory unit 38, issuing control signals to the processor of the second kind. According to the control signals of the permanent memory unit 38, the values of the results of the calculation of the first and second processors of the first kind are stored in blocks 22 and 24 of the sample processor of the second kind and the amplitude of the kth harmonic of the Fourier spectrum is calculated. From the moment of saving the calculation results in the second processor type sample blocks, the device waits for the Start signal to appear for processing the next N samples of the input signal in the first type processors.

The blocks of read-only memory of processors of the first kind 10 and 48 store digital binary codes corresponding to the modules of the Fourier coefficients (taking into account the sign):

for the first and second processors, respectively,

where k is the number of the measured harmonic;

i is the number of the current calculation cycle;

N is the total number of samples.

The first processor of the first kind works as follows.

The input of the operational amplifier 6 is a node for summing three currents: I ₁ - from the output of the scaling potentiometer 3, I ₂ - from the output of amplifier 6 and I ₃ - from the output of switch 9.

Wherein

where U ₁ is the voltage at the output of the controlled inversion block 2;

U ₂ - voltage at the output of the switch 9;

U _output - the output voltage of the operational amplifier 6;

R ₁ is the resistance of the scaling potentiometer 3;

R ₂ is the resistance of the scaling resistor 4;

R ₃ is the resistance of the scaling resistor 5;

L is the value of the code supplied to the control inputs

scaling potentiometer 3.

Given that the input current of modern operational amplifiers is negligible, according to the first law of Kirchhoff

I ₁ + I ₂ + I ₃ = 0.

Then, taking R ₁ = R ₂ = R ₃ , from (5) we obtain

Expression (6) can serve as the basis for performing the basic operation of the discrete Fourier transform.

Let the voltage of the input information signal U _s0 , U _s1 , U _s2 , U _s3 , ... U _{s (N-1)} stored in block 1 of the sample be selected in time, then to obtain the real (imaginary) part of the kth harmonic signal spectrum need to perform an operation

Let U _r0 , U _r1 , U _r2 , U _r3 , ... U _{r (N-1)} be the voltage values stored alternately in blocks 7 and 8 of the sample after performing operation (6) (even sample values are stored in block 7 of the sample, the odd values of the samples are stored in block 8 of the sample). Then

U _r0 = - (L ₀ U _s0 )

U _r1 = - (L ₁ U _s1 -L ₀ U _s0 ) = - L ₁ U _s1 + L ₀ U _s0

U _r2 = - (L ₂ U _s2 - (L ₁ U _s1 -L ₀ U _s0 )) = - L ₂ U _s2 + L ₁ U _s1 -L ₀ U _s0

U _r3 = - (L ₃ U _s3 - (L ₂ U _s2 - (L ₁ U _s1 -L ₀ U _s0 ))) = - L ₃ U _s3 + L ₂ U _s2 -L ₁ U _s1 + L ₀ U _s0

where sgn (L _i ) is the sign of L _i (sng (-1) = - 1, sgn (1) = 1), N is an even number.

Indeed, for

expression (8) can be reduced to expression (7).

; для получения из выражения (8) выражения (7) необходимо инвертировать входной сигнал нечетных выборок U_s(2m-1). Таким образом, в блоке постоянной памяти 10 каждого из процессоров должны храниться модули функции косинуса (синуса)

и значения управляющего сигнала входа блока 2 управляемой инверсии, управляющие сигналы для входа блока 2 управляемой инверсии должны формироваться следующим образом: все произведения

·U_si с четными номерами индекса i должны иметь знак коэффициента sgn(L_i), все произведения

·U_si с нечетными номерами индекса i должны иметь знак, обратный знаку коэффициента косинуса sgn(L_i).The trigonometric functions cos (2πik / N) and sin (2πik / N) can have an arbitrary sign, and the digital scaling potentiometer 3 provides multiplication of the analog voltage U ₁ only by a positive value of the binary code

; To obtain expression (7) from expression (8), it is necessary to invert the input signal of odd samples U _{s (2m-1)} . Thus, in the block of read-only memory 10 of each processor, modules of the cosine (sine) function must be stored

and the values of the control signal of the input of the controlled inversion block 2, the control signals for the input of the controlled inversion block 2 should be formed as follows: all products

· U _si with even index numbers i must have the sign of the coefficient sgn (L _i ), all products

· U _si with odd numbers of index i must have the opposite sign of the cosine coefficient sgn (L _i ).

In each cycle of calculations, the read-only memory 34 generates a control signal, which provides a sample of the input information signal from the information input X of the device in block 1 of the sample. The output signal of the block 1 of the sample is inverted or not inverted (depending on the number of the sample and the sign of the coefficient) on the block 2 of the controlled inversion and, multiplied by the coefficient of the scaling potentiometer 3, is fed to the inverting input of the operational amplifier 6.

At the outputs of blocks 10 of read-only memory, as shown above, a digital binary code is set. In this case, at the output of the operational amplifier 6, a signal U _output

At the next step, the steady-state value of the output of the operational amplifier 6 is stored in one of the blocks 7 or 8 of the sample (alternately depending on the number of the calculation cycle being performed) U _ri , and the switch 9 switches to the position that allows passage to the scaling resistor 5 of the partial amount accumulated in the previous calculation cycle (from the output of block 7 or 8 of the sample, depending on the number of the calculation cycle being performed). In this case, blocks 7 or 8 of the sample used to store the partial sum in the ith and i + 1th cycles of calculations should be different.

In the first cycle of calculations i = 0, a signal is turned on at the enable input of switch 9, which disables its output, which ensures the summation of the product with zero

and the value of U _{oOU0 is} stored in the sample block 8.

With even sample numbers (with the exception of i = 0) i = 2, 4, ... (N-2) (N is an even number), the voltage U _{output Oi i is} stored in sample block 8, and to the input of the scaling resistor 5 from the output of the switch 9, the voltage of the sampling unit 7 is supplied.

With odd sample numbers i = 1, 3, 5, ... (N-1), the voltage U _{output Oi i is} stored in the sample block 7, and the voltage of the sample block 8 is supplied to the input of the scaling resistor 5 from the output of the switch 9.

The sequence of actions of the second processor of the first kind coincides with the sequence of actions of the first processor of the first kind, while the used expressions and blocks of the first processor are replaced by the following: blocks 1, 7 and 8 of the sample blocks 39, 45 and 46, block controlled inversion 2 on the block controlled inversion 40, a scaling potentiometer 3 to a scaling potentiometer 41, a permanent memory unit 10 to a read-only memory unit 48, scaling resistors 4 and 5 to scaling resistors 42 and 43, an operational amplifier 6 for operation nny amplifier 44, the switch 9 to the switch 47, the expression (7) on the

,

,

expression (9) on

L _i = sin (2πik / N),

expression (10) on

,

,

expression (11) on

U _{output OU0} = U _s0 sin (2π0k / N) +0

Thus, upon completion of the N-1 cycle, a signal is generated at the output of the sample block 7 of the first processor of the first kind that satisfies the expression

and is the real component of the harmonic k of the expansion of the signal in a Fourier series. At the output of block 45 of the second processor of the first kind, a signal is formed that satisfies the expression

and is the imaginary component of the harmonic k of the expansion of the signal in a Fourier series.

The first processor of the second kind works as follows.

At the end of the calculation of N samples, the overflow output P of the counter 32 cocks the register 35, the output of which allows the receipt of clock pulses to the counter 37, the output of which is the address input of the read-only memory unit 38, which provides control signals to a second processor.

The switches 20 and 21 are installed in a state that ensures the passage of the signal from the information output of the first and second processors 1 of the form. Blocks 22 and 24 of the sample receive control signals to preserve the real and imaginary parts of the kth harmonic of the spectrum. The switch 12 is installed in a state that ensures the passage of the signal from the output of the reference voltage source 11 to the input of the controlled inversion unit 13. The output of the switch 26 is disabled using the permission signal from the output of the block 38 of read-only memory. The switch 27 is installed in a state that ensures the passage of the signal from the sampling unit 22 to the analog second input of the comparator 16. The signal from the output of the operational amplifier 19 is received at the first input of the comparator. At the same time, the output signal of the sequential approximation register 15 is received. Next, from the output of the constant memory unit 38, n (n is the bit capacity of the code) clock pulses are fed to the clock input of the register 15 of successive approximations. At the end of the process of successive approximations, the voltages supplied to both inputs of the comparator 16 become equal. At one input of the comparator, voltage is supplied from the output of block 22 of the sample Re (Sk), and to the other input - U _OP · N _RPP , where U _OP is the output voltage of the reference voltage source 11, N _RPP is the output code of the successive approximation register. In this way

Re (Sk) = U _OP · N _RPP

or

N _RPP = Re (Sk) / U _OD

Then, the switch 12 switches to a state that ensures the passage of the signal from the output of the switch 27 to the input of the controlled inversion unit 13. In this case, a signal appears at the output of the operational amplifier 19

where M is a scaling factor equal to 1 / U _OP .

The output voltage of the operational amplifier 19 is fixed in the block 23 of the sample.

The switch 12 is installed in a state that ensures the passage of the signal from the output of the source 11 of the reference voltage 1 to the input of the block 12 of the controlled inversion. The switch 27 switches to a state that ensures the passage of signals from the output of the sampling unit 24 to the second analog input of the comparator 16. The output of the operational amplifier 19 is supplied to the first analog input of the comparator 19. The constant memory unit 38 provides signals for performing the sequential approximation operation. Then, similarly to the case considered, at the output of the register of successive approximations, the code N _RPP = Im (Sk) / U _{OP is formed} .

The switch 12 is switched to a position that ensures the passage of the signal from the output of the switch 27 to the input of the controlled inversion unit 13. The switch 26 switches to the active state and ensures the passage of the signal from the output of the sample block 23 to the scaling resistor 18. In this case, a voltage is generated at the output of the operational amplifier 19

U _o = Im (Sk) · N _RPP + M · (Re (Sk)) ² = M · (Im (Sk)) ² + M · (Re (Sk)) ² ,

which is fixed in block 25 of the sample.

The switch 12 is switched to a position that ensures the passage of the signal from the output of the reference voltage source 11 to the information input of the controlled inversion block 13. The switch 26 is blocked by the enable signal received at its control input. The switch 27 switches to a state that ensures the passage of the signal from the output of the sampling unit 25 to the second analog input of the comparator 16. The output signal of the operational amplifier 19 is supplied to the first analog input of the comparator. A start pulse is received at the start input of the register 15 of successive approximations, and then the first clock pulse register register clock. Simultaneously with the arrival of a clock pulse, a sampling block 23 is opened, which ensures the fixation of the product U _OP by the first bit of the generated code. At the end of the sampling process, the switch 12 switches to a position that ensures the passage of the signal from the output of block 23 to the input of block 13 of the controlled inversion. Therefore, at the output of the operational amplifier 19, a signal is generated

,

,

where I is the approximation measure number.

At the end of the process of establishing the voltage at the output of the operational amplifier 19, the next clock pulse arrives at the clock input of the register 15 of successive approximations and the output value of the comparator 16 is fixed in the register. Next, the switch 12 switches to the position that ensures the passage of the signal from the output of the reference voltage source 11, the block opens 23 samples and the sequential approximation process is repeated for all n bits of the generated code.

At the end of the process of generating the code, the output voltage of the operational amplifier 19 is

or

Thus, at the outputs of the register of 15 successive approximations, a digital binary code appears, which is equal to the modulus of the kth harmonic of the signal under study. This code is the digital output of the signal amplitude of the second processor and device 50.

The switch 12 is switched to a state that ensures the passage of the signal from the output of the voltage reference source 11. In this case, a signal is generated at the output of the operational amplifier 19

At the same time, the sampling unit 25 is opened, which ensures the fixation of the output voltage. The generated analog signal is fed to the analog output of the signal amplitude of the processor of the second type and is the output of the device 49.

When the counter 37 is overflowed, a signal is generated at the overflow output, which sets the register 35 to zero. The work of the second type processor ends before the next calculation of Re (Sk) and Im (Sk) in the first and second processors of the first type from N samples of the input signal of the device.

The expansion of the input range is provided by more than 2 times due to the parallel calculation of the real and imaginary components and the introduction of the conveyor. The conveyor consists in the fact that due to the processor of the second kind, which calculates the amplitude of the kth harmonic from N samples, the process of convolution from the next N samples of the input information signal is performed in the processors of the first kind.

Information sources

1. RF patent No. 2182358 from 2000.02.28.

2. RF patent №2000104761 from 2002.03.27.

3. USSR patent No. 1679501 from 1989.03.03.

Claims (1)

An analog-to-digital multiprocessor device for computing the discrete Fourier transform containing the first, second and third sampling units, the first controlled inversion unit, the first scalable potentiometer, the first read-only memory block containing digital binary codes corresponding to the module of Fourier coefficients, the first and second scaling resistors, operating amplifier, switch, combined in the first processor of the first kind, delay unit, first register, clock, element And, the first and second account the second block of read-only memory, the information input of the first block of the sample is the information input of the processor of the first kind, the output of the first block of controlled inversion is connected to the information input of the first scaling potentiometer, the output of which is connected to the inverting input of the first operational amplifier and the inputs of the first and second scaling resistors, output the first operational amplifier is connected to the output of the first scaling resistor and to the information inputs of the second and third sample blocks, in the output of the second sampling unit is connected to the first information input of the first switch and is the information output of the processor, the output of the third sampling unit is connected to the second information input of the first switch, the output of which is connected to the output of the second scaling resistor, the non-inverting input of the first operational amplifier is grounded, the device start input is connected to the input of the delay unit and the reset inputs of the first and second counters, the output of the delay unit is connected to the installation input in "1" of the first register, the output One of which is connected to the second input of the first element And, the first input of which is connected to the output of the clock generator, the output of the first element And is connected to the clock input of the second counter, the output of which is connected to the address input of the second block of read-only memory, the output of which is connected to the clock input of the first counter the overflow output of which is connected to the reset input of the first register, characterized in that the fourth, fifth and sixth sampling blocks, the second controlled inversion block, the second scaling pot a cytometer, a third block of read-only memory, containing digital binary codes corresponding to the module of Fourier coefficients, third and fourth scaling resistors, a second operational amplifier, a second switch combined in a second processor of the first kind, a reference voltage source, switches from third to seventh, the third block is controlled inversions, third scaling potentiometer, successive approximation register, comparator, third operational amplifier, fifth and sixth scaling resistors, gray sampling units the fifth to the tenth, combined into the first processor of the second kind, the second register, the second element AND, the third counter, the fourth block of read-only memory, the information input of the fourth sample block is the information input of the second processor of the first kind, the output of the second controlled inversion block is connected to the information input of the second scaling potentiometer, the output of which is connected to the inverting input of the second operational amplifier and the inputs of the third and fourth scaling resistors, the output of the second operational the amplifier is connected to the output of the third scaling resistor and to the information inputs of the fifth and sixth sample blocks, the output of the fifth sample block is connected to the first information input of the second switch and is the information output of the second processor of the first kind, the output of the sixth sample block is connected to the second information input of the second switch, the output of which connected to the output of the fourth scaling resistor, the non-inverting input of the second operational amplifier is grounded, the output of the first sampling unit the first processor of the first kind is connected to the input of the first block of controlled inversion, the control input of which is connected to the first output of the first block of read-only memory, the remaining outputs of which are connected to the control input of the first scaling potentiometer, the output of the fourth block of the second processor of the first kind is connected to the input of the second block of controlled inversion whose control input is connected to the first output of the third block of read-only memory, the remaining outputs of which are connected to the control input of the second scaling potentiometer, the overflow output of the first counter is connected to the installation input in “1” of the second register, the output of which is connected to the second input of the second element And, the first input of which is connected to the output of the clock generator, the output of the second element And is connected to the clock input of the third counter, the overflow output of which is connected to the reset input of the second register, the information output of the third counter is connected to the address input of the fourth permanent memory block, the output of the reference voltage source under is connected to the first information input of the third switch, the output of which is connected to the information input of the third block controlled by inversion, the output of which is connected to the information input of the third scaling potentiometer, the output of which is connected to the inverting input of the third operational amplifier and the inputs of the fifth and sixth scaling resistors, the output of the third operational amplifier connected to the output of the fifth scaling resistor, the first input of the comparator, the information input of the eighth and tenth sample blocks, the first information input of the fourth and fifth switches and is the analog output of the harmonic amplitude of the signal of the first processor of the second type and device, the outputs of the fourth and fifth switches are connected to the information inputs of the seventh and ninth sample blocks, the output of the seventh sample block is connected to the first information input of the sixth and the seventh switch, the output of the eighth sampling unit is connected to the second information input of the sixth and seventh switches and to the third the input of the third switch, the output of the ninth sampling block is connected to the third information input of the sixth and seventh switches, the output of the tenth sampling block is connected to the fourth information input of the sixth and seventh switches, the output of the sixth switch is connected to the output of the sixth scaling resistor, the output of the seventh switch is connected to the second information the input of the third switch and the second input of the comparator, the output of which is connected to the information input of the register of successive approximations The output of which is connected to the control input of the third scaling potentiometer and is the digital output of the harmonic amplitude of the signal of the first processor of the second type and device, the non-inverting input of the third operational amplifier is grounded, the first information input of the first processor of the second type is connected to the second information input of the fourth switch, and the second information input the first processor of the second kind is connected to the second information input of the fifth switch, the output of the fourth block post memory is connected to the address inputs of the third, fourth, fifth, sixth and seventh switches, to the resolution input of the sixth switch, to the control inputs of the seventh, eighth, ninth and tenth sample blocks, to the control input of the third block of controlled inversion, to the setup and clock inputs of the register successive approximations, the outputs from the second to the sixth second block of read-only memory are connected to the control inputs of the first and fourth blocks of the sample, to the control inputs of the second and fifth blocks of the sample, to the input inputs of the third and sixth sample blocks, to the enable input of the first and second switches, to the address input of the first and second switches, the output of the first counter is connected to the address inputs of the first and third blocks of read-only memory, the information input of the device is connected to the information inputs of the first and second processors of the first type, the information output of the first processor of the first type is connected to the first information input of the first processor of the second type and is the output of the device real h Because of the k-th harmonic of the signal spectrum, the information output of the second processor of the first kind is connected to the second information input of the first processor of the second kind and is the output of the imaginary part of the k-th harmonic of the signal spectrum.