RU2291483C1 - Automated system for collecting and processing electronic polls data of gas "election" - Google Patents

Abstract

FIELD: computer engineering, automated system for collecting and processing electronic polls data.

SUBSTANCE: system consists of input messages receiving unit, data from server database receiving unit, election committee identification unit, first and second units for candidates base addresses identification, polls results disclosure time cycles selection unit, polls results recording time cycles selection unit, input messages receiving time cycles selection unit, database read and write signals forming unit, final polls results data forming unit.

EFFECT: increased system performance due to database entries address localization using receiving messages identifiers and forming of progressive total of polls results in real-time.

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Description

The invention relates to computer technology, in particular to an automated system for collecting and processing electronic voting data of the state automated system (GAS) “ELECTIONS”, which is a geographically distributed system whose organizational structure is determined by the electoral system of the Russian Federation and corresponds to the structure of election commissions.

The objects of the system are equipped with complexes of automation tools that form a four-level hierarchical structure aimed at implementing new information and selective technologies used in the development of this system.

The upper (first) level of the system is a set of automation tools (hereinafter referred to as the KSA) of the Central Election System of the Russian Federation, the second level of the system is the KSA of the election commissions of the constituent entities of the Russian Federation, the third level is the KSA of the district election commissions, the fourth level is the KSA of the territorial election commissions. The development of the system provides for the further automation of precinct election commissions and the creation of a fifth-level KSA, the KSA of the precinct election commission.

KSA of all levels consist of technical, software and information support, are combined into an information and communication network using state and commercial channels, communication and data networks.

At the same time, the system should provide a solution to a set of functional tasks, including the solution of the task of summarizing the results of voting in all constituent entities of the Russian Federation, the peculiarity of the solution of which is that after the completion of voting at polling stations and the tabulation of the results of voting by territorial election commissions of the constituent entities of the Russian Federation (RF) , an automated system for collecting and processing electronic voting data could ensure the collection and automatic processing of data as soon as possible the work of the total voting data in all constituent entities of the Russian Federation with the issuance of final voting results for each candidate

Known systems that could be used to solve the problem [1, 2].

The first of the known systems comprises data reception and storage units connected to control and data processing units, search and selection units connected to data storage and display units, the synchronizing inputs of which are connected to the outputs of the control unit [1].

A significant drawback of this system is the impossibility of solving the problem of online updating of data stored in memory in the form of relevant documents in real time.

Another system is known, containing a telecommunication network of data processing units, the information inputs of which are connected to data and control units, and the outputs are connected to the first group of memory units, the central processor, the inputs of which are connected to the outputs of the memory units of the first group and data processing units, and the outputs are connected to the inputs of the memory blocks of the second group and data display blocks [2].

The last of the above technical solutions is closest to the described.

Its disadvantage lies in the low speed of the system, due to the fact that the procedure for updating the data collected by the system from geographically distributed objects of the system via a telecommunication data transmission network is implemented through the procedure of their search in the entire volume of the system database with the subsequent processing of the updated data by the central processor that with large amounts of data the database system inevitably leads to a large investment of time.

The purpose of the invention is to increase the system’s speed by localizing the addresses of database records by identifiers of messages received by the system and forming a cumulative total of voting results in real time

This goal is achieved by the fact that in a known system containing an input message receiving unit, the information and synchronizing inputs of which are the first information and synchronizing inputs of the system, and the first information output is the first information output of the system, while the information input of the input message receiving unit is designed to receive codograms from the election commissions, the synchronizing input of the input messages receiving unit is intended for receiving synchronizing signals of entering ograms of election commissions to the input messages receiving unit, and the first information output of the input messages receiving unit is intended for issuing codograms of election commissions to the server information input, the server database records receiving unit, the information and synchronizing inputs of which are the second information and synchronizing system inputs, while the information input of the server database records receiving block is intended for receiving server database records, and the synchronizing input of the recording block is This server database is intended for receiving synchronization signals for entering server database records into the server database records receiving block, a block for generating final data of voting results, one information input of which is connected to the output of the server database records receiving block, and another information input of the final data generating block the voting results is connected to the second output of the input message receiving unit, and the output of the unit for generating the final data of the voting results is the second a system information output unit, a database read and write signal generation unit, the information output of which is an address output of the system, and one clock output of a database read and write signal generation unit is the first synchronization output of the system, characterized in that the system comprises an election commission identification unit the information input of which is connected to the third information output of the input message receiving unit, synchronizing the input of the electoral identification unit commissions is connected to the first synchronizing input of the system, while the information output of the election commission identification unit is connected to the first information input of the read and write database signal generation unit, and the synchronizing output of the election commission identification unit is the second synchronizing output of the system, the first candidate reference address identification unit , the information input of which is connected to the fourth output of the input message receiving unit, and the synchronizing input is sub is connected to the synchronizing output of the electoral commission identification unit, while the information output of the first candidate reference address identification unit is connected to the second information input of the read and write database signal generation unit, and the synchronizing input of the first candidate reference address identification unit is connected to the first synchronizing input of the signal generating unit read and write database, the second block identifying the reference addresses of candidates, the information output of which is connected to the third information input of the read and write database signal generation unit, and the synchronizing output of the second candidate reference address identification unit is connected to the second synchronization input of the read and write database signal generation unit, the selection block of temporary cycles for recording voting results, the input of which is connected to the second by the synchronizing input of the system, the first output of the block for selecting time cycles for recording voting results is connected to the synchronizing input of the block the formation of the final data of the voting results, the second output of the selection block of temporary cycles of recording the results of voting is the third synchronizing output of the system, and the third output of the block of selection of temporary cycles of recording the results of voting is connected to the installation input of the identification block of election commissions, the selection block of temporary cycles of receiving input messages, the input of which connected to the third output of the selection block of temporary cycles of recording voting results, and one output of the selection block of temporary of input message reception cycles is the first signal output of the system, and the selection block of time cycles for issuing voting results, one input of which is connected to the other output of the selection block of time cycles for receiving input messages, the other input of selection block for temporary cycles of issuing voting results is connected to the second synchronizing output of the generating unit read and write database signals, the information output of the selection block of the temporary cycles of the issuance of voting results is connected to the information m the input of the second block of identification of reference addresses of the candidates, the synchronizing output of the selection block of temporary cycles of issuing voting results is connected to the synchronizing input of the second block of identification of the reference addresses of candidates, and the signal output of the block of selection of temporary cycles of issuing voting results is the second signal output of the system.

The invention is illustrated by drawings, where Fig. 1 is a structural diagram of a system, Fig. 2 shows an example of a specific structural embodiment of an identification block of election commissions, Fig. 3 is an example of a specific constructive implementation of a first block of identification of reference addresses of candidates, Fig. 4 - an example of a specific constructive implementation of the second block of identification of reference addresses of candidates, figure 5 is an example of a specific constructive implementation of the block selection of time cycles for issuing the result in voting, FIG. 6 is an example of a specific structural embodiment of a block for selecting time cycles for recording voting results, FIG. 7 is an example of a specific structural embodiment of a block for selecting time cycles for receiving input messages, FIG. 8 is an example of a specific structural embodiment for a block for generating read signals and database records, figure 9 shows a generalized structure of geographically distributed election commissions of GAS "Vybory".

The system (Fig. 1) contains a block 1 for receiving input messages, a block 2 for receiving records of the server database, a block 3 for identifying election commissions, a first 4 and a second 5 blocks for identifying reference addresses of candidates, a block 6 for selecting time cycles for issuing voting results, a block 7 for selection time cycles for recording voting results, block 8 for selecting time cycles for receiving input messages, block 9 for generating read and write database signals, block 10 for generating final data for voting results.

Figure 1 shows the first 21 and second 22 information inputs of the system, the first 23 and second 24 synchronizing inputs of the system, the first 25 and second 26 information outputs of the system, the address 28 output of the system, as well as the first 29, second 30 and third 31 synchronizing outputs of the system , the first 32 and second 33 signal outputs of the system.

Block 1 receiving input messages from election commissions is made in the form of a register having an information input 21, a synchronizing input 23, as well as the first 12, second 13, third 14 and fourth 15 information outputs.

Block 2 receiving records of the server database is made in the form of a register having an information input 22, a synchronizing input 24, as well as an information output.

The election commission identification unit 3 (FIG. 2) comprises a decoder 40, a memory unit 41 made in the form of a permanent storage device, a counter 42, a trigger 43, an OR element 44, AND elements 45-49, delay elements 50-52.

The drawing shows information 53, synchronizing 54 and installation 55 inputs, as well as information 57 and synchronizing 58 outputs.

The first candidate reference address identification unit 4 (FIG. 3) comprises a decoder 60, a memory unit 61 made in the form of read-only memory, a register 62, AND elements 63-65, delay elements 66, 67.

The drawing shows information 68 and synchronizing 69 inputs, as well as information 70 and synchronizing 71 outputs.

The second block 5 identification of the reference addresses of the candidates (figure 4) contains a decoder 80, a block 81 of the memory, made in the form of read-only memory, elements 82-84 And, elements 85-1, 85-2 delay register 86.

The drawing shows information 87 and synchronizing 88 inputs, as well as information 89 and synchronizing 90 outputs.

Block 6 selection of time cycles for the issuance of voting results (figure 5) contains a counter 91, register 92, comparator 93, OR element 94 and delay element 95.

The drawing shows the first 97 and second 98 clock inputs, as well as information 99, the first 100 and second 118 clock outputs.

Block 7 selection of time cycles for recording the results of voting (Fig.6) contains a counter 101, a register 102, a comparator 103 and delay elements 104, 105.

The drawing shows a clock input 106, as well as a first 107, a second 108 and a third 109 clock outputs.

Block 8 selection of time cycles for receiving input messages (Fig.7) contains a counter 111, a register 112, a comparator 113 and a delay element 114.

The drawing shows a clock input 115, as well as the first 116 and second 117 outputs.

The block 9 for generating read and write database signals (Fig. 8) contains triggers 120-121, groups 122-124 of AND elements, group 125 of OR elements, OR element 126, delay elements 127, 128.

The drawing shows information 130-132, synchronizing 133-134 and installation 135 inputs, as well as information 28 output, the first 29 and second 136 synchronizing outputs.

Block 10 forming the final data of the voting results is made in the form of an adder having the first 137 and second 138 information and synchronizing 139 inputs and information 26 output.

All nodes and elements of the system are made on standard potential-impulse elements. To simplify the drawing, the chains of the initial installation of the nodes and blocks of the system in the initial state are not shown.

This system is equipped with election commissions at all levels of the hierarchy, with the exception of precinct election commissions, which act as sources of data on the number of voters who participated in the vote at a particular point in time and on the number of votes cast for the respective candidates.

When solving the problem of collecting and processing data on the results of electronic voting, information (codes) from the Election Commissions of the constituent entities of the Russian Federation on the voting process of voters in the respective constituent entities of the Russian Federation in the form of a final file having the following sequence of records is sequentially sent to the information input of 21 systems on the data transmission path:

Message Record Number Identifier of the election commission of a subject of the Russian Federation Candidate identifier in the form of initial letters of his surname, name and patronymic TOTAL number of votes cast for a given candidate First recording IR identification number Candidate No. 1 K1 Second record Candidate No. 2 K2 ........................... .................................... last record Candidate AGAINST ALL CPV

The first record of the codogram from the information input 21 of the system is entered into the register of block 1 with a synchronizing pulse from input 23, which passes to the synchronizing input of the register of block 1.

From output 12, the entire contents of the register of block 1 is output to output 25 of the system for subsequent documentation of entries in the database of the system.

From the exit 14 of block 1, the identifier of the election commission of the subject of the Russian Federation is fed to the input 53 of block 3 and then fed to the input of the decoder 40, which decodes the code of the identifier of the election commission, and opens one of the elements 45-47 And one input.

For definiteness, we assume that a high potential is received at one input of element 45 I.

At this time, the synchronizing pulse from the input 23 of the system goes to the input 54 of block 3 and then to the inputs of the elements 48 and 49 I. By this time, the trigger 43 is in the initial state and at its inverse output there will be a high potential, opening the element 48 And one at a time the entrance. As a result of this, the synchronizing pulse from the input 23 of the system passes through the element 48 AND, is delayed by the element 50 while receiving the code of the input message to block 1 and the operation of the decoder 40 and then goes to the polling state of the elements 45-47 I.

Considering the fact that only the AND element 45 will be open at one input, then passing through this AND element, the clock pulse arrives, firstly, at the read input of a fixed memory cell of the permanent storage device 41, where the base address of the memory cell is stored in the server database, assigned to this election commission, and reads it at the entrance of the counter 42.

In addition, the same pulse of reading the code of the base address of the election commission from the output of element 50 is delayed by element 51 for the duration of reading the contents of a fixed ROM cell and arrives at the clock input of the counter 42, fixing the base address of the memory cell assigned to this election commission in it.

The code from the output of the counter 42 through the output 57 of block 3 is output to the input 130 of block 9 and then goes to one of the inputs of elements 122 And groups, the other inputs of which at this point in time from the inverse outputs of triggers 120 and 121 are high potentials, since both triggers are in the initial state. The base address code through elements 122 AND groups through elements 125 OR groups is issued to the address output 28 of the system.

In parallel with this, the read pulse from the output of element 51 passes through the OR element 44, then it is delayed by element 52 while the base address of the election commission is entered in the counter 42 and then, firstly, from the output of the delay element 52 it is issued to the trigger trigger 43 single input, setting it in a single state, in which the element 49 And will be open, and the element 48 And is closed, and, secondly, from the output 58 of block 3, it is output to the output 31 of the system and then to the input of the first channel of the server interrupt (not shown) .

Based on this signal, the server switches to the subroutine for documenting the first codogram record from the system output 25 at the base address of the election commission, which from the output of counter 42 is issued to the address 28 of the system output.

In parallel with the process of documenting the first record in the system database, the same synchronizing write pulse from the output 58 of block 3 goes to the input 69 of block 4, to the information input 68 of which the candidate identifier code of the first record comes from the output 15 of block 1. The received code is decrypted by the decoder 60 and opens one input of one of the elements 63-65 I.

For definiteness, we assume that a high potential is received at one input of element 63 I.

At the same time, the synchronizing pulse from the input 69 of block 4 goes to the interrogation of the state of elements 63-65 I. Given the fact that only one element 63 And will be open at one input, then, after passing through this element And, the clock pulse arrives, firstly, to the read input of a fixed memory cell of the permanent storage device 61, where the address of the memory cell is stored in the server database assigned to this candidate, and reads its contents to the information input of the register 62.

Secondly, the same pulse of reading the code of the address of the memory cell in the server database assigned to the first candidate is delayed by the delay element 66 for the time of reading the contents of the fixed ROM cell; it arrives at the synchronizing input of the register 62, fixing the address of the memory cell assigned to it the first candidate from the first entry of the input message. The code from the output of the register 62 through the output 70 of block 4 is fed to the input 131 of block 9 and then to one inputs of the elements 123 And of group 123, the other inputs of which are supplied with potentials from the direct output of trigger 120 and the inverse output of trigger 121.

In parallel with this process, the synchronizing pulse from the output of element 66 of block 4 is delayed by element 67 while recording the address of the memory cell assigned to the first candidate from the first entry of the input message in register 62, and then from output 71 of block 4 it goes to input 133 of block 9, from where he, firstly, immediately goes to the direct input of the trigger 120, setting it to a single state, in which the high potential from the direct output of the trigger 120 opens the elements 123 And groups, and low potential from the inverse output of the trigger 120 closes Group VI elements 122

Thus, the elements of the 123 AND group will be open, since high potentials come from the direct output of the trigger 120 and from the inverse output of the trigger 121. Due to this, the code of the address of the memory cell assigned to the first candidate from the first record of the input message passes through the elements 123 And groups and elements 125 OR groups to the address output 28 of the system.

Secondly, simultaneously with this process, the synchronizing pulse from the input 133 is delayed by the element 126 for the duration of the trigger 120 and the issuance of the code of the address of the memory cell assigned to the first candidate from the first record of the input message to address output 28, and then issued through the output 29 of the system to the input of the second channel of the server interrupt (not shown in the drawing).

By this signal, the server goes to the subroutine for reading the contents of the memory cell assigned to the first candidate from the first entry of the input message, which stores the number of votes cast for this candidate.

The contents of the address of the memory cell assigned to the first candidate from the first record of the input message is read from the server database and through the information input 22 of the system goes to the information input of the register of block 2, where it is entered by the synchronizing pulse of the server received at the synchronizing input 24 of the system.

In addition, the synchronizing pulse from the output of element 127 is delayed by element 128 for the duration of reading the contents of the memory cell and is supplied to the installation input of trigger 120, returning it to its original state, when it with high potential from the inverse output again opens the elements of And groups 122, connecting the counter output 42 of block 3 to the address output 28 of the system.

It should be noted that before the system began to work, all its nodes and blocks were set to their initial state, and the contents of the server database memory cells assigned to each of the candidates were reset. In this regard, when reading the contents of the database memory cell assigned to the first candidate, a zero code will be read to the input of the register of block 2, and therefore, the register of block 2 will remain in its original state.

The contents of the register of block 2 (in this case, it is zero) is fed to the input 138 of block 10, made in the form of an adder. To another input 137 of adder 10 from output 13 of block 1, a code is given for the number of voters who cast their votes for this candidate.

At the same time, the synchronizing server pulse from the input 24 of the system goes to the input 106 of block 7, where it is delayed by the element 104 for the time the code is entered into the register of block 2 and then fed to the synchronizing input of the comparator 103 of block 7, to the information inputs of which codes from the outputs of the counter 101 are supplied and register 102.

At the same time, the pulse from the output 107 of the comparator 103 is delayed by the delay element 105 for the response time of the adder 10 and, firstly, from the output 108 of the block 7 is issued to the output 32 of the system and then to the input of the third channel of the server interrupt. By this signal, the server switches to the subroutine for recording the number of voters from system output 26 at the address of the memory cell assigned to the first candidate from the system address output 28, and issuing a signal for receiving the next record from the input codegram (not shown in the drawing).

Secondly, the same pulse from the output of the delay element 105 goes to the counting input of the counter 101, fixing the fact of recording the number of voters who voted for the first candidate in the system database.

According to the reception signal, the next record from the input codogram, containing information about the number of voters who voted for the second deputy, from input 21 again goes to the information input of the register of block 1, where it is entered by a synchronizing pulse from input 23.

The next record of the codogram from the information input 21 of the system is entered into the register of block 1 by a synchronizing pulse from input 23, which passes to the synchronizing input of the register of block 1.

From output 12, the entire contents of the register of block 1 is again output to the output 25 of the system for subsequent documentation of entries in the database of the system.

In contrast to the mode of receiving the first record, the synchronizing pulse from the input of the system 23 through the input 54 of block 3 does not pass through the element 48 AND, but through the element 49 AND, since at this point in time the trigger 43 is in a single state and there will be a high potential at its direct output opening element 49 And one input. As a result of this, the synchronizing pulse from the input 54 of block 3 passes through the element 49 AND and immediately goes to the counting input of the counter 42, adding one to the base address of the memory cell assigned to this election commission, and thereby, forming the next address for documenting the second records from the input codogram.

The code from the output of the counter 42 through the output 57 of block 3 is output to the input 130 of block 9 and then goes to one of the inputs of elements 122 And groups, the other inputs of which at this point in time from the inverse outputs of triggers 120 and 121 are high potentials, since both triggers are in the initial state. The base address code through elements 122 AND groups through elements 125 OR groups is issued to the address output 28 of the system.

In parallel with this, the read pulse from the output of the element 51 passes through the OR element 44, then it is delayed by the element 52 for the duration of the counter 42 operation and then, firstly, from the output of the delay element 52 it again goes to the single input of the trigger 43, confirming its single state, which element 49 And will remain open, and element 48 And - closed, and, secondly, from the output 58 of block 3 it is output to the output 31 of the system and then again goes to the input of the first channel of the server interrupt (not shown).

By this signal, the server switches to the subroutine for documenting the next codogram record from the output 25 of the system at the next address, which from the output of counter 42 is issued to the address 28 of the system output.

In parallel with the process of documenting the next record in the system database, the same synchronizing write pulse from the output 58 of block 3 is again fed to the input 69 of block 4, the information input of which 68 receives the candidate identifier code of the next record from the output 15 of block 1. The received code is decrypted by the decoder 60 and opens one input of one of the elements 63 - 65 I.

For definiteness, we assume that a high potential is received at one input of element 64 I.

At the same time, the synchronizing pulse from the input 69 of block 4 goes to the interrogation of the state of elements 63-65 I. Given the fact that only one element 64 And will be open at one input, then, after passing through this element And, the clock pulse arrives, firstly, to the read input of a fixed memory cell of the permanent storage device 61, where the address of the memory cell is stored in the server database assigned to the next candidate, and reads its contents to the information input of the register 62.

Secondly, the same pulse of reading the code of the address of the memory cell in the server database assigned to the next candidate is delayed by the delay element 66 for the time of reading the contents of the fixed ROM cell; it arrives at the synchronizing input of the register 62, fixing the address of the memory cell assigned to it candidate from the next entry of the input message. The code from the output of the register 62 through the output 70 of block 4 is fed to the input 131 of block 9 and then to one inputs of the elements 123 And of group 123, the other inputs of which are supplied with potentials from the direct output of trigger 120 and the inverse output of trigger 121.

In parallel with this process, the synchronizing pulse from the output of element 66 of block 4 is delayed by element 67 while recording the address of the memory cell assigned to the first candidate from the first entry of the input message in register 62, and then from output 71 of block 4 it goes to input 133 of block 9, from where he, firstly, immediately goes to the direct input of the trigger 120, setting it to a single state, in which the high potential from the direct output of the trigger 120 opens the elements 123 And groups, and low potential from the inverse output of the trigger 120 closes Group VI elements 122

Thus, the elements of the 123 AND groups will be open, since high potentials come from the direct output of the trigger 120 and from the inverse output of the trigger 121. Due to this, the code of the address of the memory cell assigned to the candidate from the next record of the input message passes through the elements 123 AND groups and elements 125 OR groups to address output 28 of the system.

Secondly, simultaneously with this process, the synchronizing pulse from the input 133 is delayed by the element 126 for the duration of the trigger 120 and the code of the address of the memory cell assigned to the candidate from the next record of the input message to the address output of the system, and then through the output 29 of the system is issued to the input of the second channel of the server interrupt (not shown in the drawing).

By this signal, the server switches to the subroutine for reading the contents of the memory cell assigned to the candidate from the next entry of the input message, which stores the number of votes cast for this candidate.

The contents of the address of the memory cell assigned to the candidate from the next entry of the input message is read from the server database and through the information input 22 of the system goes to the information input of the register of block 2, where it is entered by the synchronizing pulse of the server received at the synchronizing input 24 of the system.

In addition, the synchronizing pulse from the output of element 126 of block 9 is delayed by element 129 for the duration of reading the contents of the memory cell and is supplied to the installation input of trigger 120, returning it to its original state, in which it with high potential from the inverse output again opens the elements And groups 122, again connecting the output of the counter 42 of block 3 to the address output 28 of the system.

The contents of the register of block 2 (in this case, it is also equal to zero) is fed to the input 138 of block 10, made in the form of an adder. To another input 137 of adder 10 from output 13 of block 1, a code is given for the number of voters who cast their votes for the next candidate.

At the same time, the server synchronizing pulse from the input 24 of the system enters the input 106 of block 7, where it is delayed by the element 104 for the time the code is entered in the register of block 2 and then fed to the synchronizing input of the comparator 103 of block 7, the information inputs of which are supplied with the codes from the outputs of the counter 101 and register 102.

Given that at this point in time, the readings of the counter 103 will still be less than the number of candidates in the register 102, then an output is generated at the output 107 of the comparator 103, which is fed to the synchronizing input 139 of the adder 10, which fixes the number of voters who voted for this candidate, and gives the result to the output 26 of the system.

At the same time, the pulse from the output 107 is delayed by the delay element 105 for the response time of the adder 10 and, firstly, from the output 108 of the block 7 is issued to the output 32 of the system and then to the input of the third channel of the server interrupt. By this signal, the server switches to the subroutine for recording the number of voters from system output 26 at the address of the memory cell assigned to the first candidate from the system address output 28, and issuing a signal for receiving the next record from the input codegram (not shown in the drawing).

Secondly, the same pulse from the output of the delay element 105 goes to the counting input of the counter 101, fixing the fact of recording the number of voters who voted for the first candidate in the system database.

According to the reception signal, the next record from the input codogram, containing information about the number of voters who voted for the next deputy, from input 21 again goes to the information input of the register of block 1, where it is entered by a synchronizing pulse from input 23. From output 12, the entire contents of the register of block 1 again is issued to the output 25 of the system for subsequent documentation of entries in the system database.

The described process of entering the number of voters who voted for the respective deputies into the fixed cells of the database assigned to the respective candidates continues until the comparator 103 of block 7 fixes the fact that the number of entries in the counter 101 is equal to the number of candidates stored in the register 102. In this a point in time at the output of the comparator 109, a signal is generated indicating that all entries from the input message from the corresponding election commission are entered in the corresponding memory cells, attached to the respective candidates.

The pulse from the output 109 of the comparator, firstly, is supplied to the installation input 55 of block 3, from where it is supplied to the installation input of the trigger 43, setting it to the initial state, in which the high potential from the inverse output of the trigger 43 opens the And element 48 and prepares the synchronization circuit pulse from input 54 through element 48 I.

Secondly, the pulse from the output 109 of block 7 goes to the input 115 of block 8, from where it is fed to the counting input of the counter 111, which counts the number of election commissions that sent their messages. In this case, the counter 111 will record the fact of receiving entries from the first election commission. In the register 112, the number of election commissions is constantly kept, which must send their messages on the voting results.

In addition, the synchronization pulse from input 115 is delayed by the delay element 114 for the response time of counter 111 and then is transmitted to the synchronization input of comparator 113, which compares the readings of counter 111 and register 112 using this synchronization signal. Considering the fact that counter 111 recorded only one selective the commission that sent its results, then his testimony at this point in time will be less than the total number of election commissions recorded in the register 112.

As a result of this, at the output 116 of the comparator 113, a signal is received that starts receiving input data of the next election commission, which is output to the output 33 of the system and then goes to control the reception of the input message of the next election commission (not shown).

After that, the incoming message of the next election commission is received, the records are accepted, the votes cast for the respective deputies are summed up, and the final results are entered in the memory cells assigned to the respective candidates as described above.

The reception of input messages from the election commissions of the constituent entities of the Russian Federation and their processing as described above continues until the comparator 113 of block 8 fixes the fact of the equality of the readings of the counter 111 and the register 112, the formation of a pulse at the output 117. The appearance of this pulse indicates that messages of all election commissions are documented, and the number of votes cast by voters for the respective deputies is summed up, recorded in dedicated memory cells assigned to the respective candidates idatami, and it is ready to issue on the display board and print.

To this end, the pulse from the output 117 of block 8 is fed to the input 97 of block 6, where the OR element 94 passes and then goes to the counting input of the counter 91, which records the fact of reading and issuing the final voting data for the first candidate. In this case, the counter 91 recorded the first unit, and its readings through the output 99 of block 6 go to the input 87 of block 5 and then to the input of the decoder 80. The number of candidates who participated in the vote is entered in the register 92 of block 6.

In addition, the pulse from the output of the OR element 94 is delayed by the element 95 for the duration of the operation of the counter 91 and is transmitted to the synchronization input of the comparator 93, which compares the readings of the counter 91 and the register 92 using the synchronization signal. Considering the fact that the counter 91 registered only one candidate, the results voting for which are to be issued, then his testimony at this point in time will be less than the total number of candidates recorded in the register 92.

As a result of this, at the output 100 of the comparator 93, a signal is generated to start issuing the final voting data for the first candidate, which goes to the input 88 of block 5 and then goes to the polling of the state of elements 82-84 I. The state of these elements is determined by the decoder 80, which decrypts the input code and opens the corresponding element 82-84 I. Suppose that such an element is element 82 I.

Firstly, the clock pulse from input 88 passes through the And element 82 and is fed to the read input of a fixed memory cell of the read-only memory device 81, where the address of the memory cell is stored in the server database assigned to the first candidate and reads it to the input of the register 86.

In addition, the same pulse from input 88 of block 5 is delayed by element 85-1 for the duration of reading the contents of a fixed ROM cell and arrives at the synchronizing input of register 86, fixing the address of the memory cell assigned to the first candidate in it. The code from the output of the register 86 through the output 89 of the block 5 is issued to the input 132 of the block 9 and then goes to one of the inputs of the elements 124 And groups.

In parallel with this, the pulse from the output of element 85-1 is delayed by element 85-2 for the time the memory address is entered into register 86 and then from output 90 of block 5, it is output to the trigger input 121 via input 134 of block 9, setting it to a single state, which elements 124 AND groups and element 129 And will be open, and elements 122, 123 And groups are closed.

Simultaneously with this process, the synchronizing pulse from input 134 is delayed by element 127 for the duration of trigger 121 and the issuance of the address code of the memory cell assigned to the first candidate to address output 28 through elements 124 AND groups and elements 125 OR groups, and then through output 30 of the system issued to the input of the third channel of the server interrupt (not shown in the drawing).

By this signal, the server switches to a subroutine for reading the contents of the memory cell assigned to the first candidate, which stores the total number of votes cast for this candidate, and issuing the total number of voters who voted for the first candidate on the display and print panel (not shown shown).

In addition, the same pulse of output from the output of element 127 is delayed by element 128 for the duration of the program for reading the final data and issuing them to the display board and printing, and then from the output 136 of block 9 it enters the input 98 of block 6, where the OR element 94 passes, and then again enters the counting input of the counter 91, increasing its readings by one. The new readings of the counter 91 through the output 99 of block 6 go to the input 87 of block 5 and then to the input of the decoder 80. The register 92 of block 6 still contains the number of candidates who participated in the vote.

In addition, the pulse from the output of the OR element 94 is delayed by the element 95 for the duration of the operation of the counter 91 and again goes to the synchronizing input of the comparator 93, which compares the readings of the counter 91 and the register 92 by the synchronizing signal. Considering the fact that the counter 91 has already recorded the second candidate , the results of the vote for which are to be issued, then his testimony at this point in time will be less than the total number of candidates recorded in the register 92.

As a result of this, at the output 100 of the comparator 93, a signal is generated to start issuing the final voting data for the next candidate, which goes to the input 88 of block 5 and then goes to the polling of the state of elements 82-84 I. The state of these elements is determined by the decoder 80, which decrypts the received code and opens the corresponding element 82-84 I. Suppose that such an element is now element 83 I.

First, the synchronizing pulse from input 88 passes through the And element 83 and is fed to the read input of a fixed cell of the permanent storage device 81, where the address of the memory cell is stored in the server database assigned to the next candidate. And reads it to the input of the register 86.

In addition, the same pulse from input 88 of block 5 is delayed by element 85-1 for the duration of reading the contents of a fixed ROM cell and arrives at the synchronizing input of register 86, fixing the address of the memory cell assigned to the next candidate in it. The code from the output of the register 86 through the output 89 of the block 5 is issued to the input 132 of the block 9 and then appears on one of the inputs of the elements 124 And groups.

In parallel with this, the pulse from the output of element 85-1 is delayed by element 85-2 for the time the memory address is entered in register 86 and then from output 90 of block 5 through input 134 of block 9 it is issued to the single input of trigger 121, confirming its single state, in which elements 124 And groups and element 129 And will be open, and elements 122, 123 And groups will be closed.

Simultaneously with this process, the synchronizing pulse from input 134 is delayed by element 127 for the duration of trigger 121 and the issuance of the code of the address of the memory cell assigned to the next candidate to address input 28 of the system through elements 124 AND groups and elements 125 OR groups, and then through output 30 the system again goes to the input of the fourth channel of the server interrupt (not shown in the drawing).

By this signal, the server again switches to the subroutine for reading the contents of the memory cell assigned to the next candidate, which stores the total number of voters who voted for this candidate on the display panel and print (not shown in the drawing).

In addition, the same output pulse from the output of element 127 is delayed by element 128 for the duration of the program for reading the final data and issuing them to the display and printing board, and then from the output 136 of block 9 again goes to the input 98 of block 6.

This process continues until the readings of the counter 91 become equal to the readings of the register 92. This moment will be fixed by the comparator 93 by issuing a pulse to output 118, from which this synchronizing pulse is firstly output to the system output 34 as an end signal issuing the final data, and secondly, it goes to the input 135 of block 9, where it goes to the installation input of the trigger 121 and returns it to its original state.

Thus, the introduction of new nodes and blocks and new constructive connections made it possible to significantly increase the system performance by eliminating the time costs associated with performing the preliminary recording of all received information in the database, their subsequent search and processing, by localizing the addresses of database records by identifiers received a system of messages and the formation of a cumulative total of voting results in real time.

Information sources

1. US Patent No. 0,005,651, M class. G 06 F 13/40, 13/38, 1992.

2. US Patent No. 05129083, M class. G 06 F 12/00, 15/40, 1992 (prototype).

Claims (1)

An automated system for collecting and processing electronic voting data of the state automated system “Vybory”, containing an input message receiving unit, the information and synchronizing inputs of which are the first information and synchronizing inputs of the system, and the first information output is the first information output of the system, while the information input of the receiving unit of input messages is intended for receiving codograms from election commissions, synchronizing the input of the input receiving unit messages is intended for receiving synchronization signals of entering the codograms of election commissions into the input messages receiving unit, and the first information output of the input messages receiving unit is intended for issuing codograms of election commissions to the server information input, the server database record receiving unit, the information and synchronizing inputs of which are the second information and synchronizing system inputs, while the information input of the server database record receiving unit is intended for volume of server database records, and the synchronizing input of the server database records receiving block is intended for receiving synchronizing signals of entering the server database records into the server database records receiving block, the block for generating the final data of the voting results, one information input of which is connected to the output of the records receiving block server database, another information input of the block for forming the final data of the voting results is connected to the second output of the input messages receiving block, and the output the unit for generating the final data of the voting results is the second information output of the system, the unit for generating the read and write database signals, the information output of which is the address output of the system, and one clock output of the unit for generating the read and write database signals is the first synchronizing output of the system, characterized in that the system contains an identification block for election commissions, the information input of which is connected to the third information output of the block the input messages, the synchronizing input of the election commission identification unit is connected to the first synchronizing input of the system, while the information output of the election commission identification unit is connected to the first information input of the read and write database signal generation unit, and the synchronizing output of the election commission identification unit is the third synchronizing output system, the first block of identification of reference addresses of candidates, the information input of which is connected to even the output of the input message receiving unit, and the synchronizing input is connected to the synchronizing output of the election commission identification unit, while the information output of the first candidate reference address identification unit is connected to the second information input of the read and write database signal generation unit, and the synchronizing output of the first reference identification unit candidate addresses connected to the first synchronizing input of the block for generating read and write database signals, the second block identification of reference addresses of candidates, the information output of which is connected to the third information input of the read and write database signal generation unit, and the synchronization output is connected to the second synchronization input of the read and write database signal generation unit, the selection block for temporary cycles of recording voting results, the input of which connected to the second synchronizing input of the system, the first output of the block selection of time cycles for recording voting results is connected to the synchronization the input to the unit for generating the final data of the voting results, the second output of the selection block for temporary cycles of recording the results of voting is the fourth synchronizing output of the system, and the third output of the block for selecting temporary cycles for recording the results of voting is connected to the installation input of the block for identifying election commissions, the block for selecting temporary cycles for receiving input messages , the input of which is connected to the third output of the block of selection of time cycles for recording voting results, and one output is is the first signal output of the system, and a block for selecting time cycles for issuing voting results, one input of which is connected to another output of a block for selecting time cycles for receiving input messages, and another input of a block for selecting time cycles for issuing voting results is connected to the second synchronizing output of the unit for generating read and write signals database, the information output of the selection block of the temporary cycles of the issuance of voting results is connected to the information input of the second identification unit and reference addresses of candidates, the synchronizing output of the selection block of temporary cycles for issuing voting results is connected to the synchronizing input of the second block for identifying the reference addresses of candidates, and the signal output of the block for selecting temporary cycles for issuing voting results is the second signal output of the system.

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