RU2287865C1 - Memory element for electrically erasable programmable read-only memory - Google Patents

Abstract

FIELD: computer engineering; electrically erasable programmable read-only memory.

SUBSTANCE: memory element for electrically erasable programmable read-only memory consists of semiconductor base with source and drain, tunnel layer, storage layer, blocking layer and conductive gate implemented on the planar side. Base is made of p-type silicon, tunnel layer is made of silicon oxide (SiO₂), storage layer is made of silicon nitride (Si₂N₄), blocking layer is made of silicon oxide (SiO₂), and the conductive gate is made of platinum silicide (PtSi). The depth of tunnel layer is 1.8-5.0 nm.

EFFECT: increased memory element reliability in read mode.

2 cl, 1 dwg

Description

The invention relates to computing, and in particular to storage devices, in particular to electrically reprogrammable read-only memory (EEPROM), which stores information when the power is turned off, and can be used in memory devices of computers, microprocessors, portable memory devices, flash memory electronic cards.

Known memory element for flash (fast) electrically programmable read-only memory (S. Minami, K. Ujiie, M. Terasawa, K. Komori, K. Furusawa, Y. Kamigaki "A 3-volt 1 Mbit full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology (IECE Transaction on Electronics, v. E77-C, N.8, pp1260-1269, 1990), comprising a semiconductor substrate with a source and drain provided on the planar side, a tunnel layer located on the substrate, a storage layer located on the tunnel layer, a blocking layer located on the storage layer, and a conductive gate located on the blocking layer. The substrate is made of p-type silicon, the tunnel layer is made of silicon oxide (SiO ₂ ), the storage layer is made of silicon nitride, the blocking layer is made of silicon oxide (SiO ₂ ), the conductive gate is made of n-type polysilicon. The thickness of the tunnel layer is 1.8 nm, the thickness of the storage layer is 14.5 nm, the thickness of the blocking layer is 3.0 nm.

The value of the memory window (the difference in threshold voltages corresponding to the logical "0" and "1") in this memory element after 10 years at 85 ° C is 0.8 V.

A disadvantage of the known technical solution is the low percentage of suitable devices in the production of memory elements. This technical solution is characterized by a small size of the memory window. The above drawback is due to the constructive implementation of the memory element, which leads to the presence of spurious injection of electrons into the storage layer made of silicon nitride of an n-type polysilicon gate made of silicon nitride.

Another disadvantage is the low reliability of the device in the mode of reading information. The above disadvantage is associated with the thickness of the tunnel layer, which is 1.8 nm.

The closest technical solution to the claimed is a memory element for flash (fast) electrically reprogrammable read-only memory device (FRLibsch, MHWhite "Charge Transport and Storage of Low Programming Voltage SONOS / MONOS Memory Device" Solid State Electronics, v.33, pp.105- 126, 1994), comprising a semiconductor substrate with a source and drain provided on the planar side, a tunnel layer located on the substrate, a storage layer located on the tunnel layer, a blocking layer located on the storage layer, and a conductive gate located on the blocks uyuschem layer. The substrate is made of p-type silicon, the tunnel layer is made of silicon oxide (SiO ₂ ), the storage layer is made of silicon nitride, the blocking layer is made of silicon oxide (SiO ₂ ), the conductive gate is made of gold. The thickness of the tunnel layer is 2.0 nm, the thickness of the storage layer is 10.0 nm, the thickness of the blocking layer is 5.0 nm.

The disadvantage of the closest technical solution is the low percentage of suitable devices in the production of memory elements. The above drawback is due to the choice of structural materials, namely, the choice of the material for the manufacture of a conductive gate of gold, characterized by poor adhesion to silicon dioxide, of which the blocking layer is made. Poor gold adhesion is the cause of failure of the devices at the stage of manufacturing the shutter of the memory element during the photolithography operation.

Another disadvantage is the low reliability of the device in the mode of reading information. The above disadvantage is associated with the thickness of the tunnel layer, which is 1.8 ÷ 2.0 nm.

The technical result of the invention is to increase the yield of devices in the production of memory elements and increase the reliability of the memory element in read mode.

The technical result is achieved by the fact that in the flash memory element of an electrically reprogrammable read-only memory device containing a semiconductor substrate with a source and drain made on the planar side, a tunnel layer located on the substrate, a storage layer located on the tunnel layer, a blocking layer located on the memory layer, and a conductive gate located on the blocking layer, the substrate is made of p-type silicon, the tunnel layer is made of silicon oxide (SiO ₂ ), remembering the third layer is made of silicon nitride (Si ₃ N ₄ ), the blocking layer is made of silicon oxide (SiO ₂ ), and the conductive gate is made of platinum silicide (PtSi), and the thickness of the tunnel layer is 1.8-5.0 nm.

In the memory element, the storage layer may be made of silicon nitride enriched with excess silicon (SiN _x ).

The invention is illustrated by the following description and the attached drawing. The drawing shows the design of a memory element for flash EEPROM, where 1 is a semiconductor substrate, 2 is a source, 3 is a drain, 4 is a tunnel layer, 5 is a storage layer, 6 is a blocking layer, 7 is a conductive gate.

The increase in the yield of suitable devices in the production of memory elements for flash EEPROM is achieved as a result of the use of platinum silicide as the material of the conductive gate. Such a gate is characterized by a large work function (4.2 eV), its use allows blocking spurious electron injection at a negative bias. Platinum silicide has good adhesion to silicon dioxide, from which the blocking layer is made, therefore at the stage of manufacturing the memory elements during the photolithography operation on platinum silicide, this can significantly reduce the percentage of defective products.

Improving the reliability of the memory element for flash EEPROM is ensured by optimizing the choice of the thickness of the tunnel layer, its optimal thickness lies in the range 1.8 ÷ 5.0 nm.

The memory element for flash EEPROM contains (see the drawing) a semiconductor substrate (1), a source (2), a drain (3), a tunnel layer (4), a storage layer (5), a blocking layer (6), a conductive gate (7) . In this case, the source (2) and drain (3) are made on the planar side of the substrate, the tunnel layer (4), the storage layer (5), the blocking layer (6) are sequentially made on the same side of the substrate, and a conductive shutter is made on top of the blocking layer (7). The materials used are: p-type silicon for the substrate, silicon oxide (SiO ₂ ) for the tunnel layer, silicon nitride (Si ₃ N ₄ ) for the storage layer, silicon oxide (SiO ₂ ) for the blocking layer, for the conductive layer shutter - platinum silicide (PtSi). Silicon nitride enriched with excess SiN _x silicon can also be used as the material of the storage layer. The main requirement for the storage layer is the presence of a high density of traps. The choice of silicon dioxide to create the tunneling and blocking layers is associated with high breakdown fields of this material.

The tunnel layer (4) is 1.8–5.0 nm thick. When the tunnel layer (4) is less than 1.8–2.0 nm thick, the charge draining in the memory element is sharply accelerated due to the tunneling of carriers through the tunnel layer (4) to the substrate (1). Drainage of the charge leads to a decrease in threshold voltages corresponding to the logical "0 and" 1, and, consequently, to a decrease in the reliability and percentage of usable memory elements of flash EPPU in the manufacture of products. An increase in the thickness of the tunnel layer (4) leads to an increase in the storage time of information in the flash memory element of the EEPROM. However, an increase in the thickness of the tunnel layer (4) to a value of more than 5.0 nm leads to an undesirable increase in the duration and amplitude of the reprogramming pulse due to the voltage drop across the tunnel layer (4). Thus, the optimal thickness of the tunnel layer (4) lies in the range 1.8–5.0 nm.

The memory element for flash EEPROM is used as follows.

The initial threshold voltage of the memory element (transistor) for flash EEPROM is close to zero. Information is recorded (logical "0") by applying a positive voltage to the substrate (1) relative to the substrate (1), creating an electric field in the tunnel layer (4) with a strength equal to (9 ÷ 14) × 10 ⁶ V / cm. In this case, the electrons tunnel through the tunnel layer (4) into the storage layer (5) and trap them, the high density of which is characterized by the storage layer (5). The capture of electrons by the traps of the storage layer (5) leads to the accumulation of a negative charge and puts the memory element in a non-conductive state (since the channel of the transistor memory element is in a non-conductive state) with a high positive threshold voltage, which corresponds to a logical "0".

Reprogramming the flash memory element of the EEPROM memory (logical “1” record) is carried out by applying a negative voltage to the gate (7) relative to the substrate (1). In this case, an electric field is created in the storage medium, that is, the storage layer (5), stimulating the ionization of electron traps with trapped electrons and leaving them in the substrate (1) and injection of holes from the substrate (1). As a result, the injected holes are trapped by the traps of the storage layer (5) and a positive charge is accumulated in it. The presence of a positive charge in the storage layer (5) leads to a shift in the threshold voltage in the direction of the negative potential, and the channel of the transistor flash memory element EEPROM goes into a conducting state, which corresponds to a logical "1".

Thus, the memory element for flash EEPROM works, in which reprogramming is carried out by tunneling injection of electrons and holes from the substrate into the storage layer.

The method of functioning of the inventive device itself opens up the possibility of increasing the thickness of the tunnel layer made of silicon oxide from 1.8 to 5.0 nm in order to increase the threshold voltage after 10 years of information storage at 85 ° C by suppressing the spreading of electrodes from the storage layer by silicon nitride based.

Reducing the voltage and duration of the reprogrammable pulse can be achieved in the flash memory element for EPPU by reprogramming by injecting hot electrons and holes from the substrate channel into the storage layer.

Claims (2)

1. A memory element for a flash of an electrically reprogrammable read-only memory device, comprising a semiconductor substrate with a source and drain provided on the planar side, a tunnel layer located on the substrate, a storage layer located on the tunnel layer, a blocking layer located on the storage layer, and a conductive gate located on the blocking layer, the substrate is made of p-type silicon, the tunnel layer is made of silicon oxide (SiO ₂ ), the storage layer is made of silicon nitride (Si ₂ N ₄ ), b the locking layer is made of silicon oxide (SiO ₂ ), characterized in that the conductive gate is made of platinum silicide (PtSi), and the thickness of the tunnel layer is 1.8 ÷ 5.0 nm. 2. The memory element according to claim 1, characterized in that the storage layer is made of silicon nitride enriched with excess silicon (SiN _x ).