RU2284443C1 - Tank armament stabilizer - Google Patents

Abstract

FIELD: automatic control and adjustment systems, in particular, tank armament stabilizers.

SUBSTANCE: the stabilizer has a control unit, weapon training drive mechanically linked with the turret, weapon elevation drive mechanically linked with the gun, gyro transmitters mechanically linked with the tank turret and gun, the outputs of the control unit are connected to the inputs of the training drive and the elevation drive, and the gyro transmitters connected to the three-phase power mains are connected via their outputs to the inputs of the control unit. In addition, use is made of the first computer, second computer, "modulo 2 sum" logical element, the first counter, second counter, third counter, fourth counter, the first register, second register, third register, clock pulse-generator, the first comparison device, second comparison device, fourth comparison device, fifth comparison device, the first OR gate, second OR gate, the first AND gate, second AND gate, third AND gate, fourth AND gate, the third OR gate, the comparators are connected to the phases of the three-phase mains, and the gates are interconnected for revealing the nature of the fault of the three-phase mains.

EFFECT: enhanced safety of stabilizer use due to elimination of the emergency situation - non-controllable change of the turret state and putting of the gun to the stop at an absence of one or several phases of the alternating supply voltage of the gyro transmitters.

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Description

The invention relates to automatic control and regulation systems, in particular to stabilizers of tank weapons.

Known stabilizer tank weapons 2E42. The stabilizer 2E42 is made according to the electric circuit principle BS1.370.008EZ and is described in BS1.370.008TO, TU (see also figure 1). This stabilizer is taken as a prototype. The stabilizer has two power drives of horizontal (GN) and vertical guidance (HV) mechanically connected respectively to the turret and gun of the tank, the control unit for the drives of the GN and HV and gyroscopic sensors mechanically connected to the turret and gun of the tank, and the signals from the gyroscopic sensors are processed by the unit controls and are introduced into the drive control loop. Gyroscopic sensors are powered by a three-phase network of the tank of alternating voltage 36V 400Hz.

The disadvantage of the prototype stabilizer is the occurrence of uncontrolled transfer of the tower (movement at maximum speed in an arbitrary direction) and the gun is put in focus when one or several phases of the tank's AC voltage disappear.

The invention solves the problem of improving the safety of stabilizer operation by eliminating an emergency situation - uncontrolled transfer of the turret and putting the gun in focus in the absence of one or more phases of the alternating voltage of the gyroscopic sensors.

To achieve the technical result provided by the invention, a stabilizer comprising a control unit, a GN drive mechanically connected to the turret, a VN drive mechanically connected to the gun, gyroscopic sensors mechanically connected to the turret and the tank gun, the control unit outputs connected to the GN drive inputs and HV drive, and gyroscopic sensors connected to a three-phase power supply, connected to the inputs of the control unit by outputs, according to the invention, a first comparator and a second compa ator, “modulo two sum” logic element, first counter, second counter, third counter, fourth counter, first register, second register, third register, clock generator, first comparison device, second comparison device, third comparison device, fourth comparison device the fifth comparison device, the first logical element OR, the second logical element OR, the first logical element AND, the second logical element AND, the third logical element AND, the fourth logical element AND, the third logical element OR, moreover, the first input of the first comparator is connected to the first phase of the three-phase network, the second input of the first comparator is connected to the second phase of the three-phase network, the first input of the second comparator is connected to the third phase of the three-phase network, the second input of the second comparator is connected to the second phase of the three-phase network, the output of the first comparator is connected to the first input of the logic element "sum modulo two" and the first input of the second counter, the output of the second comparator is connected to the second input of the logic element "sum modulo two" and the first input third counter, the first input of the first counter is connected to the inverting output of the "modulo two sum" logic element, the second input of the first, second and third counters is connected to the first output of the fourth counter, the third input of the first, second and third counters and the input of the fourth counter are connected to the output clock generator, the first input of the first register is connected to the output of the first counter, the first input of the second register is connected to the output of the second counter, the first input of the third register is connected to the output of the third counter , the second input of the first, second and third register is connected to the second output of the fourth counter, the output of the first register is connected to the input of the first comparison device, the output of the second register is connected to the input of the second and third comparison device, the output of the third register is connected to the input of the fourth and fifth comparison device, the output of the first comparison device is connected to the third input of the first logical element AND, the output of the second comparison device is connected to the first input of the first logical element OR, the third output about the comparison device is connected to the second input of the first OR gate, the output of the fourth comparison device is connected to the first input of the second OR gate, the output of the fifth comparison device is connected to the second input of the second OR gate, the first output of the first OR gate is connected to the first input of the second and the third logical element AND, the second inverting output of the first logical element OR is connected to the first input of the first logical element And and the second input of the fourth logical And, the first output of the second OR gate is connected to the first input of the fourth AND gate and the second input of the third AND gate, the second inverting output of the second OR gate is connected to the second input of the first and second AND gate, the outputs of the first, second, third and the fourth element AND are connected respectively to the first, second, third and fourth input of the third logical element OR, the output of which is connected to the control unit.

Comparative analysis with the prototype shows that the inventive stabilizer is characterized by the presence of new elements: the first comparator, the second comparator, the logic element "sum modulo two", the first counter, the second counter, the third counter, the fourth counter, the first register, the second register, the third register, clock generator, first comparison device, second comparison device, third comparison device, fourth comparison device, fifth comparison device, first OR gate, second OR gate, he first AND gate, a second AND gate, the third AND gate, a fourth AND gate, a third OR gate) - and their relationships with other stabilizer components. Comparison of the proposed solution with other technical solutions shows that the newly introduced elements are quite well known in the art (Horowitz P., Hill W. The art of circuitry: In 3 volumes. Translated from English - 4th ed. Revised and extended .- M .: Mir, 1993), but when introduced into the stabilizer in the indicated connection, it allows solving the problem of eliminating the emergency situation when one or several phases of the alternating voltage disappear, which was typical for the prototype. In addition, most of the new elements are more convenient to implement as part of the software of the digital control unit, with the first and second comparator being discrete ports of the controller of the digital control unit, providing, if necessary, galvanic isolation, and the frequency of the clock generator will be determined by the frequency of the digital signal processing cycles control unit.

Figure 1 shows the structural diagram of the stabilizer prototype. Figure 2 presents the structural diagram of the inventive stabilizer. The stabilizer comprises a control unit 1, a GN 2 drive mechanically connected to the turret 4, a BH 3 drive mechanically connected to the gun 5, gyroscopic sensors 6 mechanically connected to the turret 4 and the tank gun 5, the outputs of the control unit 1 being connected to the inputs of the GN drive 2 and the VN 3 drive, and the gyroscopic sensors 6 connected to the three-phase power supply network are connected by outputs to the inputs of the control unit 1, and also contains a first comparator 7, a second comparator 8, a logic element “sum modulo two” 9, the first counter 10, second counter 11, mp this counter 12, the fourth counter 13, the first register 14, the second register 15, the third register 16, the clock generator 17, the first comparison device 18, the second comparison device 19, the third comparison device 20, the fourth comparison device 21, the fifth comparison device 22, the first logic element OR 23, second logic element OR 24, first logic element AND 25, second logic element AND 26, third logic element AND 27, fourth logic element AND 28, third logic element OR 29, wherein the first input of the first comparator 7 is connected with the first phase of the three-phase network, the second input of the first comparator 7 is connected to the second phase of the three-phase network, the first input of the second comparator 8 is connected to the third phase of the three-phase network, the second input of the second comparator 8 is connected to the second phase of the three-phase network, the output of the first comparator 7 is connected to the first input logic element "sum modulo two" 9 and the first input of the second counter 11, the output of the second comparator 8 is connected to the second input of the logic element "sum modulo two" 9 and the first input of the third counter 12, the first input is counter 10 is connected to the inverting output of the “modulo two” sum 9 logic element, the second input of the first 10, second 11 and third 12 counters is connected to the first output of the fourth counter 13, the third input of the first 10, second 11, third 12 counters and the input of the fourth counter 13 are connected to the output of the clock generator 17, the first input of the first register 14 is connected to the output of the first counter 10, the first input of the second register 15 is connected to the output of the second counter 11, the first input of the third register 16 is connected to the output of the third counter 12, the second input One of the first 14, second 15 and third 16 registers is connected to the second output of the fourth counter 13, the output of the first register 14 is connected to the input of the first comparison device 18, the output of the second register 15 is connected to the input of the second 19 and third 20 of the comparison device, the output of the third register 16 is connected with the input of the fourth 21 and fifth 22 of the comparison device, the output of the first comparison device 18 is connected to the third input of the first logical element AND 25, the output of the second comparison device 19 is connected to the first input of the first logical element OR 23, the output of the third comparison device 20 is connected to the second input of the first OR gate 23, the output of the fourth comparison device 21 is connected to the first input of the second OR gate 24, the output of the fifth comparison device 22 is connected to the second input of the second OR gate 24, the first output of the first the OR gate 23 is connected to the first input of the second 26 and the third 27 of the AND gate, the second inverting output of the first OR gate 23 is connected to the first input of the first AND gate 25 and the second input of the fourth logical element AND 28, the first output of the second logical element OR 24 is connected to the first input of the fourth logical element And 28 and the second input of the third logical element And 27, the second inverting output of the second logical element OR 24 is connected to the second input of the first 25 and second 26 of the logical element AND, the outputs of the first 25, second 26, third 27 and fourth 28 of the logical element And are connected respectively to the first, second, third and fourth input of the third logical element OR 29, the output of which connected to control unit 1.

The stabilizer works as follows.

In the normal state of the three-phase power supply, the linear voltage at the input of the first comparator 7 (the third phase relative to the second) is ahead of the phase voltage of the input voltage of the second comparator 8 (the first phase relative to the second) by 60 degrees. The first 7 and second 8 comparators convert the alternating voltage of a sinusoidal shape at their inputs into a sequence of active (with a positive value of the instantaneous voltage) and passive (with a negative value of the instantaneous voltage) logic levels at the outputs. An active logic level appears on the inverting output of the logic element “sum modulo two” 9 if the logic signal levels are either active or passive at its inputs; in other cases, the output is a passive logic level. Thus, the first comparator 7 generates a logic signal in accordance with the sign of the line voltage of the first and second phases, the second comparator 8 generates a logic signal in accordance with the sign of the linear voltage of the third and second phases, and the logic element “sum modulo two” 9 generates a logic signal by comparing the signs of the linear voltage of the first-second and third-second phases. The frequency of the clock generator 17 (500 Hz) can be selected slightly higher than the frequency of a three-phase network (400 Hz) and must be multiple to it. When the next edge of the pulse from the clock generator 17 arrives at the third inputs of the first 10, second 11 and third 12 counters, they increase the accumulated amount by one if the first inputs have an active logic level coming from the inverting output of the “modulo two” sum logic element 9 , from the output of the first comparator 7 and from the output of the second comparator 8, respectively. Thus, with the frequency of the clock generator 17, the second counter 11 counts the number of positive signs of the linear voltage of the first and second phases, the third counter 12 - the number of positive signs of the linear voltage of the third and second phases, and the first counter 10 - the number of identical signs. The fourth counter 13, having a volume of 100, counts the number of pulses received at the input from the clock generator 17; when reaching 100 on the second output, the fourth counter 13 generates a write signal for the first 14, second 15 and third 16 registers, and on the first output - a reset signal for the first 10, second 11 and third 12 counters, and the reset signal is supplied to the counters after recording the results accounts in registers. Thus, every 100 pulses of the clock generator 17 at the outputs of the second 15, third 16 and first 14 registers, the counting result of the second 11, third 12 and first 10 counters for 100 pulses of the clock generator 17 line voltage signs of the first and second phases, the third and second is updated phases, as well as the number of matches of these signs, respectively. The counting results come from the first register 14 to the first comparison device 18, from the second register 15 to the second 19 and third 20 of the comparison device, and from the third register 16 to the fourth 21 and fifth 22 of the comparison device. The first comparison device 18 forms an active logic level if the input number is less than 20. The second 19 and fourth 21 comparison devices form an active logic level if their inputs have a number less than 7. The third 20 and fifth 22 comparison devices form an active logic level if at their inputs, the number is more than 93. Logic elements OR, if at least one input has an active level of a logical signal, forms an active logic level at the output, and a passive logic signal at the inverting output. Logic elements And in the presence of at least one input of a passive level of a logical signal, a passive logical level is formed at the output. The comparison results from the outputs of the comparison devices are received on the first 23, second 24 logical elements OR, as well as on the first 25, second 26, third 27 and fourth 28 logical elements AND, connected according to figure 2. At the output of the second logical element AND 26, an active logical level will appear if the active level comes from the first output of the first logical element OR 23 to the first input (i.e., the sign of the linear voltage of the first and second phases for a hundred cycles of the clock generator 17 rarely changed), and the second input will receive an active level from the second inverting output of the second logical element OR 24 (i.e., the sign of the linear voltage of the third and second phases for a hundred cycles of the clock generator 17 often changed) and will mean the disappearance of the first phase . At the output of the fourth logical element AND 28, an active logical level will appear if the first input receives an active level from the first output of the second logical element OR 24 (i.e., the sign of the linear voltage of the third and second phases for one hundred cycles of the clock generator 17 rarely changed), and the second input will receive an active level from the second inverting output of the first logical element OR 23 (i.e., the sign of the linear voltage of the first and second phases for a hundred cycles of the clock generator 17 often changed) and will mean the loss of the third phase. At the output of the first logical element And 25, an active logical level will appear if the active input from the first comparator 18 arrives at the third input (i.e., the signs of the line voltage of the first, second and third and second phases for one hundred cycles of the clock generator 17 rarely coincided), the first input will receive an active level from the second inverting output of the first logical element OR 23 (i.e., the sign of the linear voltage of the first and second phases for a hundred cycles of the clock generator 17 often changed), and the second input will receive an active level the second inverting output of the second OR gate 24 (i.e., the sign of the line voltage third and second phases hundred cycles per timing generator 17 is often changed) and will mean the loss of the second phase. An active logic level will appear at the output of the third AND gate 26 if the first level receives an active level from the first output of the first OR gate 23 (i.e., the sign of the line voltage of the first and second phases in a hundred cycles of the clock generator 17 rarely changed), and the second input will receive an active level from the first output of the second logical element OR 24 (i.e., the sign of the linear voltage of the third and second phases for one hundred cycles of the clock generator 17 also rarely changed) and will mean the disappearance of two or all three ex phases. Thus, by analyzing the state of the outputs of the first 25, second 26, third 27, and fourth 28 logical elements AND, it is possible to diagnose a malfunction of a three-phase network - which phase has disappeared or more than one phase has disappeared. Upon receipt of at least one active logical level from the outputs of the first 25, second 26, third 27, fourth 28 logical elements AND to the inputs of the third logical element OR 29, the latter generates a signal to the control unit to reset the control signals of the GN and VN drives, which eliminates inadequate operation stabilizer - uncontrolled transfer of the tower and putting the gun on the stop - in the absence of one or more phases of the alternating voltage of the gyroscopic sensors.

The claimed invention improves the safety of the operation of the stabilizer by eliminating the emergency situation - uncontrolled transfer of the tower and putting the gun at the stop - in the absence of one or more phases of the alternating voltage of the gyroscopic sensors, and also allows you to identify the nature of the malfunction of the three-phase power network.

The expediency of the stabilizer, implemented according to the claimed structural scheme, is confirmed by the positive results of combined (State) tests of the stabilizer 2E42M1 as part of the facility.

Information sources

Stabilizer 2E42. Technical description. - Archive of OJSC SKB PA, 1988, p. 18, 26, 27

Claims (1)

A tank weapon stabilizer comprising a control unit, a horizontal guidance (GN) drive mechanically connected to a turret, a vertical guidance (VN) drive mechanically connected to a cannon, gyroscopic sensors mechanically connected to the turret and the cannon of the tank, the outputs of the control unit being connected to the inputs GN drive and VN drive, and gyroscopic sensors connected to a three-phase power supply network, with outputs connected to the inputs of the control unit, characterized in that the first comparator swarm comparator, modulo two sum logic element, first counter, second counter, third counter, fourth counter, first register, second register, third register, clock generator, first comparison device, second comparison device, third comparison device, fourth device comparison, the fifth comparison device, the first logical element OR, the second logical element OR, the first logical element AND, the second logical element And, the third logical element And, the fourth logical element And, the third logical element OR, the first input of the first comparator connected to the first phase of the three-phase network, the second input of the first comparator connected to the second phase of the three-phase network, the first input of the second comparator connected to the third phase of the three-phase network, the second input of the second comparator connected to the second phase of the three-phase network, the output of the first the comparator is connected to the first input of the "modulo two sum" logic element and the first input of the second counter, the output of the second comparator is connected to the second input of the "modulo two sum" logical element and the first m is the input of the third counter, the first input of the first counter is connected to the inverting output of the "modulo two sum" logic element, the second input of the first, second and third counters is connected to the first output of the fourth counter, the third input of the first, second and third counters and the input of the fourth counter are connected with the output of the clock generator, the first input of the first register is connected to the output of the first counter, the first input of the second register is connected to the output of the second counter, the first input of the third register is connected to the output of the third about the counter, the second input of the first, second and third register is connected to the second output of the fourth counter, the output of the first register is connected to the input of the first comparison device, the output of the second register is connected to the input of the second and third comparison device, the output of the third register is connected to the input of the fourth and fifth device comparison, the output of the first comparison device is connected to the third input of the first logical element AND, the output of the second comparison device is connected to the first input of the first logical element OR, you One of the third comparison device is connected to the second input of the first OR gate, the output of the fourth comparison device is connected to the first input of the second OR gate, the output of the fifth comparison device is connected to the second input of the second OR gate, the first output of the first OR gate is connected to the first input of the second and the third logical element AND, the second inverting output of the first logical element OR is connected to the first input of the first logical element And and the second input of the four of the logical AND gate, the first output of the second OR gate is connected to the first input of the fourth logical gate AND and the second input of the third logical gate AND, the second inverting output of the second logical gate OR is connected to the second input of the first and second logical gate And, the outputs of the first, second, the third and fourth elements AND are connected respectively to the first, second, third and fourth input of the third logical element OR, the output of which is connected to the control unit.

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