RU2261937C2 - Method of forming of polycrystalline silicon layers - Google Patents

Abstract

FIELD: microelectronics; methods of manufacture of microcircuit chips.

SUBSTANCE: the offered invention is pertaining to the field of microelectronics, in particular, to the methods of manufacture of microcircuit chips. The offered method includes a loading of semiconductor slices in a reactor having hot walls perpendicularly to a gas stream, pumping-out of the reactor air up to the ultimate vacuum, introduction of monosilane for deposition of layers of polycrystalline silicon, silane supply cutoff, pumping-out of the reactor air up to the ultimate vacuum, delivery of a noble gas into the reactor up to atmospheric air pressure, unloading of the semiconductor slices from the reactor. After introduction of the noble gas into the reactor conduct an additional thermal annealing of layers of polycrystalline silicon at the temperature of no less than 1323K, then keep the slices at this temperature during 40-60 minutes in a stream of noble gas and reduce the temperature down to the temperature of the polycrystalline silicon layers growth. The technical result of the invention is a decrease of heterogeneity of resistance of the polycrystalline silicon layers.

EFFECT: the invention ensures a decrease of heterogeneity of resistance of the polycrystalline silicon layers.

1 dwg, 2 tbl, 1 ex

Description

The scope of the invention is microelectronics, namely the technology for manufacturing integrated circuits. Currently, in the production of ICs, layers of polycrystalline silicon are formed in once-through reactors of low pressure with a hot wall at T _oc = (873-923) K and pressure in the reactor (1-50) Pa by the pyrolysis of monosilane (SiH ₄ ). (VLSI technology. Edited by S.Z. Book 1. Moscow: Mir 1986, p.127-139) [1].

The disadvantage of this method of forming layers of polycrystalline silicon (SEC) is the presence in the reactor:

- a positive temperature gradient along the gas reagent (towards pumping), i.e. lack of isothermal deposition conditions;

- a negative pressure gradient along the gas reagents (towards pumping), i.e., the absence of isobaric deposition conditions.

A positive temperature gradient along the gas reagent is set to obtain a homogeneous thickness of the SEC in the deposition zone. A negative pressure gradient is obtained due to the dissipation of the energy of the moving gas reagent and the resistance of the pumping lines.

The absence of isothermal and isobaric conditions of deposition, as well as the heterogeneity of the energy state of the surface of the plates contribute to the heterogeneity of the properties of the SEC (grain size, direction of growth, imperfection) in the deposition zone. So, with ionic doping with boron, an SEC with a thickness of 400 nm with E = 30 keV and B = 20 μCul / cm ² with subsequent thermal annealing of T = 1273 K for 60 min, the inhomogeneity of the resistance of the SEC over the deposition zone is - (30-40)%, cm. drawing.

The resistance of the SPK is determined mainly by the following parameters:

- average grain size, L;

- the temperature of the final heat treatment;

- the density of trap states at the grain boundaries (GB), N _t ;

- the height of the potential barrier (φ _B ) and the width of the SCR at the grain boundaries;

- concentration of impurities, N.

The heterogeneity of the resistance of the SEC over the deposition zone is mainly determined by the grain size, grain defectiveness, and the density of trap states at the grain boundaries.

With a decrease in grain size, the area of grain boundaries increases, which entails an increase in trap states, as well as an increase in SCR, which entails an increase in φ _B. A decrease in grain size leads to an increase in the resistance of the SEC.

The grain size increases with increasing temperature and decreasing pressure along the deposition zone of the reactor, and therefore the resistance of the SEC decreases towards the end of the deposition zone.

The closest technical solution to the present invention is a method for producing polycrystalline polysilicon layers (Pat. USA N 3900597 С 23 C 11/00, 1975. System and process for deposition of polycrystalline silicon with silane in vacuum [2], which includes loading semiconductor wafers into a reactor with hot walls perpendicular to the gas flow, pumping the reactor to extreme vacuum, monosilane inlet (SiH ₄ ) to precipitate SPK, shutting down monosilane, pumping the reactor to maximum vacuum, inert gas to atmospheric pressure, unloading the floor conductor plates.

The disadvantages of the prototype include:

- heterogeneity of the resistance of the SEC (after doping with impurity and activation) over the deposition zone of the reactor;

- heterogeneity of the resistance of the SEC on the plate.

The objective of the present invention is to obtain a technical result, which consists in reducing the heterogeneity of the resistance of the SEC on the plate and the deposition zone of the reactor. The problem is solved in a method of forming layers of polycrystalline silicon, including loading semiconductor wafers into a reactor with hot walls perpendicular to the gas flow, pumping the reactor to the ultimate vacuum, letting in monosilane to deposit SPK, stopping the supply of monosilane, pumping the reactor to the limit of vacuum, letting inert gas into the reactor to atmospheric pressure, unloading semiconductor wafers from the reactor, after inert gas is introduced into the reactor, the temperature of the reactor is increased to supplement After thermal annealing of the SEC to T → 1323 K, then the plates are kept (modify the SEC) at this temperature for at least 40-60 min in an inert gas stream, and the temperature is reduced to the SEC growth temperature. Additional thermal annealing (modification of SEC) can also be carried out in a diffusion furnace.

Thus, the hallmark of the invention is the combined process of the formation of the SEC, which consists in its modification by additional thermal annealing (modification) at the place of its deposition or in a diffusion furnace. Additional thermal annealing of the SEC stabilizes the size of polysilicon grains on the plates located along the deposition zone (grain size increases, GB area, trap density, etc. decrease), which helps to reduce the inhomogeneity of the SEC resistance over the plate and the deposition zone, as well as its absolute decrease.

Patent studies have shown that the set of features of the invention is new, which proves the novelty of the proposed method. In addition, patent studies showed the lack of published data showing the influence of the distinctive features of the claimed invention on the achievement of a technical result, which confirms the inventive step of the proposed method. This set of distinctive features allows us to solve the problem.

Example. After standard chemical treatment, silicon dioxide was formed on monocrystalline substrates in trichlorethylene with oxygen with a thickness of 50 nm. The oxidized plates were loaded into the boat with a pitch of 2.38 mm, the boat with the plates was loaded into the reactor. The plates on the boat were located as follows: 1st plate at the beginning of the deposition zone (n.a.); 2nd dam in the middle of the deposition zone (north-west); 3rd plate at the end of the deposition zone (KZ). The reactor was pumped to the ultimate vacuum and then at Q _ar = 60 l / h. The reactor was pumped out for 25 min (temperature stabilization). The reactor was pumped out without feeding argon to a vacuum of 0.3 Pa, after which 10% monosilane was introduced into the reactor at a rate of 120 l / h for 40 minutes. In this case, the deposition temperature was 893 K in the center of the deposition zone. After 40 minutes, the monosilane supply was stopped, the reactor was pumped out to the ultimate vacuum, after which the reactor was pumped out with Q _ar = 60 l / h for 10 minutes, the argon supply was stopped, the reactor was pumped to the maximum vacuum and the reactor was depressurized. Then the plates were unloaded from the reactor. Conducted 6 processes of deposition of SEC. The thickness of the SEC was 400 nm ± 3% for all processes. SECs were doped with boron E = 30 keV and D = 40 μCool / cm ² , and the other part of the plates from these processes was thermally annealed (modified) before ion doping in a diffusion furnace at T = 1323 K for 60 min, then the modified SEC was doped with boron E = 30 keV and D = 40 μCoul / cm ² . Impurities were activated at T = 1323 K for 30 min. Table 1 presents the results of the heterogeneity of the resistance of the SEC over the plate and the process without additional thermal annealing (modification of the SEC).

From the data given in tables 1 and 2, it follows that additional thermal annealing (modification of SEC) improves the heterogeneity of resistance in the deposition zone by 4-5 times, in a series of processes by 5 times, and on the plate by 2-2.5 times.

Claims (1)

A method of forming polycrystalline silicon layers, including loading semiconductor wafers into a hot-wall reactor perpendicular to the gas flow, pumping the reactor to the ultimate vacuum, monosilane inlet to deposit polycrystalline silicon layers, stopping monosilane supply, pumping the reactor to the ultimate vacuum, inert gas to the reactor to inert gas pressure, unloading the semiconductor wafers from the reactor, characterized in that after the inert gas is introduced into the reactor, an additional second polycrystalline silicon layers of thermal annealing at a temperature of not less than 1323 K, then the plate was kept at this temperature for 40-60 minutes in a stream of inert gas and reducing the temperature to growth temperature polycrystalline silicon layers.