RU2261527C1 - Random-length pulse shaper - Google Patents

Abstract

FIELD: generating modulated-length pulses.

SUBSTANCE: proposed random-length pulse shaper that can be used for simulating signals of data transfer system has first delay unit, circuit of second controlled delay units, pseudorandom pulse generator, and flip-flop.

EFFECT: ability of shaping random-length pulses having desired statistical characteristics.

1 cl, 2 dwg

Description

FIELD OF THE INVENTION

The present invention relates to a technique for generating modulated electric pulses and can be used to simulate signals from data transmission systems.

State of the art

The health margin of receivers of digital data signals transmitted over real communication lines is estimated by modeling signals with distortions, which manifest themselves as a random deviation of the pulse duration from the average value with specified statistical parameters.

For this purpose, a device can be used in the form of a comparator connected by inputs to the output of a periodic sawtooth pulse generator and a noise voltage source [1], which can be any known noise generator [2]. In such a device, the noise voltage is linearly converted to the pulse duration, which, therefore, acquires the statistical properties of the initial noise voltage. The disadvantage of this analogue is the low accuracy and stability of the statistical characteristics of the duration of the generated pulses due to the analogous nature of the processes in it.

The same method is implemented in a uniformly distributed random pulse generator [3], which consists of a comparator, the inputs of which are connected to the outputs, respectively, of a device for sampling and storing the instantaneous noise voltage and a ramp generator, the control inputs of which are connected to the output of the reference clock. The accuracy of modeling the noise deviation of the pulse duration at the output of the comparator in this analogue is also low due to the analogous nature of the process, in which the change in the statistical characteristics of the noise voltage when the temperature or supply voltage deviates leads to a distortion of the set probabilistic moments of the pulse duration.

It is also known a device [4] for generating pulses with phase jitter, consisting of a reference generator, an output connected simultaneously to the input of a pseudo random number generator (PRNG) and a matched multi-tap delay line. The taps of the delay line are connected to the corresponding information inputs of the multiplexer, in which the address inputs are connected to the group of adjacent outputs of the PRNG through a digital summing unit made in the form of read-only memory. In this analogue, built entirely on digital blocks, the noise modulation of the phase of the output pulse of the multiplexer is carried out. Thanks to the digital method of controlling the phase of the pulses, the device has increased accuracy and stability when generating pulses with a random phase. The disadvantage of the prototype device is the limited functionality that does not allow it to be used to obtain pulses of random duration.

Of the known analogues, the closest in technical essence to the present invention is a pulse generator with normalized phase noise [5], containing a serial circuit of controlled delay elements and a PRNG connected to the input terminal, connected to the output of the serial circuit of controlled delay elements, and the outputs to the control inputs of the corresponding controlled delay elements. The reference inputs of all controlled delay elements are connected to a common clamp of an adjustable reference voltage, and the input of a series circuit of controlled delay elements is connected to the output of the clock generator.

The principle of operation of the prototype device is based on summing in each clock cycle the delay times of all controlled delay elements in a serial circuit, and the delay time of each controlled delay element is determined by the logical state of the corresponding PRNC output. It is known that the sum of the contents of adjacent PRNG discharges obeys the binomial, and with a large number of discharges, normal distribution law [6]. Therefore, the moment the pulse appears at the output of the serial circuit of the controlled delay elements is random, its distribution is close to the normal distribution. The disadvantage of the prototype device is its limited functionality that does not allow using it directly to obtain pulses of random duration.

SUMMARY OF THE INVENTION

The purpose of the present invention is the expansion of the functionality of the device, providing pulses of random duration with predetermined statistical characteristics with high accuracy and stability inherent in digital devices.

To do this, into the device containing the input terminal, through the first delay element connected to the serial circuit of the second controlled delay elements, and the PRNG, the input connected to the output of the serial circuit of the second controlled delay elements, and the corresponding outputs to their control inputs, and the reference inputs of all second controlled delay elements are connected to a common terminal of the second reference voltage, a trigger and a terminal of the first reference voltage are introduced. In this case, the trigger inputs are connected respectively to the input terminal and the output of the serial circuit of the second controlled delay elements, the trigger output is connected to the output terminal of the device, and the reference input of the first delay element is connected to the terminal of the first voltage reference.

второго элемента И-НЕ. При низком уровне "1" на управляющем входе положение фронта выходного импульса не изменяется, а спад импульса задерживается дополнительно на время Δt, определяемое постоянной времени RC-цепи и уровнем напряжения на опорном входе.Each second controlled delay element included in the device can be made in the form of a pair of AND-NOT logic gates with paraphase outputs, for example, ESL gates in the negative logic agreement, and a parallel RC circuit connected simultaneously to the inverse output of the first of the AND gates NOT and one input of the second gate AND NOT. In this case, one input of the first AND gate NOT serves as the control input of the delay element, and the remaining inputs of both gates AND NOT the paraphase input of the delay element. The reference input of the second controlled delay element is the free output of the resistor of the RC circuit, the capacitor of which is connected to a common bus. In such a delay element, at a high level “0” of the control signal from the PRNG, the front and the decay of the output pulse are delayed relative to the input pulse only for the propagation delay time

second element AND NOT. With a low level of “1” at the control input, the position of the front of the output pulse does not change, and the pulse decay is delayed additionally by the time Δt, determined by the time constant of the RC circuit and the voltage level at the reference input.

The first delay element is a well-known one-shot, the pulse duration of which depends on the voltage at the reference input, for example, a delay device on ESL elements [7].

In the proposed device, the installation of the trigger is performed directly by the input pulse, and the reset is performed by the pulse of the last controlled delay element from the serial circuit, which appears at random times. Therefore, the duration of the output pulse of the trigger is a random variable with a given PRNG and the delay time of the controlled delay elements distribution.

List of drawings

Figure 1 presents the electrical functional diagram of a pulse shaper of random duration according to the present invention.

Figure 2 shows the electrical schematic diagram of a variant of the second controlled delay element, which is part of a pulse shaper of random duration.

Information confirming the possibility of carrying out the invention

Shown in figure 1, the pulse shaper circuit of random duration contains connected to the input terminal 1 of the first delay element 2 and a series circuit of the second controlled delay elements 3 ... 9. The reference input of the first delay element 2 is connected to the terminal 10 of the first reference voltage, and the reference inputs of all of the second controlled delay elements 3 ... 9 are connected to a common terminal 11 of the second reference voltage. The device also includes a PRNG 12, an input connected to the output of the specified serial circuit of the second controlled delay elements 3 ... 9, and outputs to their control inputs, as well as trigger 13. In this case, the trigger inputs are connected respectively to input terminal 1 and the output of the serial circuit controlled elements 2 ... 8 delays, and the output of the trigger 13 is connected to the output terminal 14 of the device.

In the considered embodiment of the device, an RS-trigger 13 with dynamic inputs is used, it is cocked and reset by the drops of its input pulses. The PRNG 12 is also clocked by the decay of the output pulses of the controlled delay element 9.

Figure 2 presents a diagram of a possible implementation of the second controlled element 3 ... 9 delay included in the device of figure 1. The circuit is made on emitter-coupled logic (ESL) valves with paraphase signal transmission. These gates perform a logical AND-NOT function in a negative logic convention. The circuit is equipped with signal paraphase inputs 15, 16 connected to the first inputs of the valves 17 and 18. The outputs of the valve 17 are the paraphase outputs 19 and 20 of the delay element. The timing elements of the circuit are a resistor 21 and a capacitor 22 connected by one lining to the common bus, and the second together with one output of the resistor 21 to the inverse output of the valve 18 and the second input of the valve 17. The second input of the valve 18 serves as a control input 23, and the remaining output of the resistor 21 - reference input 24 of each second controlled element 3 ... 9 delay.

вентиля 17. При низком уровне логической "1" на управляющем входе 23 спад импульса на выходе 19 и соответственно фронт импульса на выходе 20 задерживаются относительно импульса на сигнальных входах 15, 16 на время, определяемое скоростью разряда конденсатора 22 через резистор 21 в направлении напряжения на опорном входе 24. По достижении уровнем напряжения на конденсаторе 22 порогового уровня переключения вентиля 17 И-НЕ происходит совпадение уровней "1" на входах этого вентиля, в результате вентиль 17 переключается с задержкой

+Δt. Фронт импульса со входа 15 передается на выход 19 практически без задержки (собственная задержка

мала).With a high voltage level of logical "0" at the control input 23 at the inverse output of the valve 18, the logic level "1" is held, so the pulse delay at the outputs 19, 20 relative to the pulses at the inputs 15, 16 is equal only to its own delay

gate 17. With a low level of logic "1" at the control input 23, the pulse drop at the output 19 and, accordingly, the pulse front at the output 20 are delayed relative to the pulse at the signal inputs 15, 16 for a time determined by the discharge rate of the capacitor 22 through the resistor 21 in the direction of the voltage across the reference input 24. Upon reaching the voltage level at the capacitor 22 of the threshold switching level of the valve 17 AND NOT coincides with the levels "1" at the inputs of this valve, as a result, the valve 17 switches with a delay

+ Δt. The pulse front from input 15 is transmitted to output 19 with virtually no delay (intrinsic delay

small).

The pulse generator random duration works in the following order. The drop in the pulse at the input terminal 1 triggers 13, and the drop in the pulse from the output of the series-connected first delay element 2 and the second controlled delay elements 3 ... 9 is reset. Due to this, the pulse at the output terminal 14 of the device - the output of the trigger 13 starts at a fixed point in time, and ends at a random point in time, which is determined by the sum of the current logical states of the outputs of the PRNG 12 and the values of the delay times of the first and second delay elements.

Since the sum of the contents of adjacent discharges of the PRNG is normally distributed, the duration of the output pulses is also normally distributed. Let the delay time of the first delay element 2 is t _З1 , and the delay time of each i-th second controlled delay element 3 ... 9 is

- неизменная составляющая, Δt - регулируемая составляющая, Q_i - логическое состояние i-го выхода ГПСЧ. Тогда при n выходов ГПСЧ и соответственно n вторых управляемых элементов задержки выходные импульсы устройства характеризуются следующими параметрами:Where

is a constant component, Δt is an adjustable component, Q _i is the logical state of the i-th PRNS output. Then, with n outputs of the PRNG and, accordingly, n second controlled delay elements, the output pulses of the device are characterized by the following parameters:

- minimum duration -

- maximum duration -

- expectation of duration -

- variance of duration -

- the width of the energy spectrum of the deviations t _AND - from f _IN / (2 ^m -1) to f _IN , where f _IN is the frequency of the input pulses, m is the width of the basic shift register in the PRNG;

- the number of steps of quantization of duration - n.

The average value of the duration of the output pulses is regulated by adjusting the time t _{Z1 of the} first delay element 2 by changing the voltage at terminal 10 of the first reference voltage. By changing the voltage at terminal 9 of the second reference voltage, you can change the delay time of each included second controlled delay element 3 ... 9 and, therefore, set the rate of deviation of the duration of the output pulse at terminal 14. The possibility of electronic control of the mathematical expectation and the norm of the random duration of the output pulse, as well as the possibility of an external launch, expand the functionality of the device, for example, when it is automatically configured.

Literature

1. Tukhareli K.D., Shulga V.G. Devices simulating phase jitter of pulses of code sequences. On Sat "Semiconductor electronics in communication technology", issue 19. - M .: Communication, 1978, p. 154-161, Fig. 4.

2. Bobnev M.P. Random signal generation. - M .: Energy, 1971.

3. A generator of uniformly distributed random pulses. - RF patent No. 2107941, IPC G 06 F 7/58.

4. Chulkov V.A. Pulse generator with phase jitter. - Instruments and experimental equipment, 1996, No. 2, p. 73-74.

5. A pulse generator with normalized phase noise. - RF patent No. 2133552, IPC N 03 K 5/159 (prototype).

6. Korn G. Modeling of random processes on analog and analog-digital machines. - M .: Mir, 1968.

7. Leonov A.V., Mironov B.S., Rosenberg A.V., Choklin V.I. Electronic delay device. - Exchange of experience in the radio industry, 1980, No. 9, p. 59-60, Fig. 1.

Claims (1)

A random-duration pulse generator containing an input terminal, through a first delay element connected to a serial circuit of second controlled delay elements, and a pseudo-random number generator, connected to an output of a serial circuit of second controlled delay elements, and corresponding outputs to their control inputs, with reference inputs all the second controlled delay elements are connected to a common terminal of the second voltage reference, characterized in that a trigger is inserted into it, the inputs of the connection connected respectively with the input terminal and the output of the serial circuit of the second controlled delay elements, and the output connected to the output terminal of the device, the reference input of the first delay element is connected to the terminal of the first reference voltage.

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