RU2246130C2 - System for data transfer for governmental population recording system - Google Patents

Abstract

FIELD: computers.

SUBSTANCE: system has nine registers, four address selectors, triggers, AND elements, OR elements and delay elements.

EFFECT: higher speed.

8 dwg

Description

The invention relates to computer technology, in particular to a data transmission system of the automated system “State Population Register”.

Known systems that could be used to solve the problem [1, 2].

The first of the known systems comprises data reception and storage units connected to control and data processing units, search and selection units connected to data storage and display units, the synchronizing inputs of which are connected to the outputs of the control unit [1].

A significant drawback of this device is the impossibility of solving the problem of updating data stored in memory in the form of relevant documents at the same time as solving the problem of delivering the contents of these documents to users in real time.

Another system is known, comprising a central processing unit, memory units for storing data structures connected to a central processing unit, receiving registers and data processing units [2].

The last of the above technical solutions is closest to the described.

Its disadvantage is the low speed of the system, due to the fact that user queries are implemented through data retrieval procedures for querying the entire database and their subsequent processing in the buffer zone of the server’s memory, which is inevitable with large amounts of data contained in the State Register of Population leads to unreasonably large costs of time to obtain a result.

The purpose of the invention is to improve system performance by updating the database of reporting and reference data at the time of receipt of transactions in real time.

This goal is achieved by the fact that in a known system containing a first register, the information input of which is the first information input of the system, the synchronizing input is the first synchronizing input of the system, and the outputs of the first register are the first information output of the system, the first address selector, the information inputs of which are connected to the corresponding outputs of the second register, the synchronizing input is connected to the output of the first OR element, the output of which is connected to the synchronizing input of the second first register, the third register, the information inputs of which are connected to the information outputs of the first address selector, the synchronizing output of which is connected to the synchronizing input of the third register, the first group of OR elements, the inputs of which are connected to the corresponding outputs of the AND elements of the first and second groups, and the outputs are connected to the information inputs of the second register, the second group of OR elements, the inputs of which are connected to the corresponding outputs of the AND elements of the third and fourth groups, and the outputs are connected to information ion inputs of the fourth register, the synchronizing input of which is connected to the output of the second OR element, the first delay element, the input of which is connected to the first synchronizing input of the system, and the output is connected to one input of the first AND element, and the output is connected to one input of the first OR element, the first trigger , the single input of which is connected to the first synchronizing input of the system, the direct output is connected to another input of the first AND element and to one inputs of the AND elements of the first and fourth groups, the other inputs of which are connected to the corresponding outputs of the first register, the inverse output of the first trigger is connected to one of the inputs of the And elements of the second and third groups, the other inputs of which are the second and third information inputs of the system, respectively, the second address selector, the information inputs of which are connected to the outputs of the fourth register, the information outputs are connected to the information to the inputs of the fifth register, the synchronizing output is connected to the synchronizing input of the fifth register and to the input of the second delay element, and the output of the fifth register RA is the third information output of the system, the second AND element, one input of which is the second synchronizing input of the system, the other input is connected to the inverse output of the first trigger, and the output is connected to the other input of the first OR element, the output of which is connected to one input of the second OR element, the third element And, one input of which is connected to the direct output of the first trigger, the other is connected to the output of the second delay element, and the output is the first synchronizing output of the system, the third delay element, the input of which of the second is connected to the output of the third AND element, and the output is connected to the installation inputs of the first trigger, the first, third, and fifth registers, the fourth AND element, whose inputs are connected to the inverse output of the first trigger and the output of the second delay element, respectively, and the output is connected to one input the third OR element, the fourth delay element, the output of which is connected to the input of the fifth delay element, and the sixth delay element, the sixth register is introduced, the information inputs of which are the fourth information input system, and the clock input is connected to the output of the third OR element, the third address selector, the information inputs of which are connected to the corresponding outputs of the sixth register, and the clock input is connected to the output of the third OR element, the seventh register, the information inputs of which are connected to the information outputs of the third address selector, the clock input is connected to the clock output of the third address selector, the installation input is connected to the output of the fifth delay element, and the outputs are the fourth m information output of the system, the eighth register, the information inputs of which are the fifth information input of the system, and the synchronizing input is connected to the synchronizing output of the third address selector output, the fourth address selector, the information inputs of which are connected to the corresponding outputs of the eighth register, the synchronizing input is connected to the synchronizing output of the third address selector, and the synchronizing output is connected to the input of the fourth delay element, the output of which is the second synchronization system output, the ninth register, the information inputs of which are connected to the information outputs of the fourth address selector, the synchronization input is connected to the synchronization output of the fourth address selector, the installation input is connected to the output of the fifth delay element, and the outputs are the fifth information output of the system, fifth element And, one the input of which is the third synchronizing input of the system, the other is connected to the inverse output of the first trigger, and the output is connected to the input of the sixth element ki, the second trigger, the single input of which is connected to the output of the fifth element And, the installation input is connected to the synchronizing output of the fourth address selector, and the inverse output of the second trigger is connected to the third input of the second element And, the sixth element And, whose inputs are connected to the direct output of the second trigger and the output of the sixth delay element, and the output is connected to another input of the second and third OR elements, and the fourth OR element, the inputs of which are connected to the synchronizing output of the first address selector and the output estogo AND gate, and an output connected to the clock input of the second selector addresses.

The invention is illustrated by drawings, where Fig. 1 is a structural diagram of a device, Fig. 2 is a structural diagram of an address selector, Fig. 3 shows a structure of a codogram, Figs. 4-8 show examples of displaying inquiries on user requests.

The system (figure 1) contains the first 1, second 2, third 3, fourth 4, fifth 5, sixth 6, seventh 7, eighth 8 and ninth 9 registers, the first 10, second 11, third 12 and fourth 13 address selectors, first 14 and second 15 triggers, first 16, second 17, third 18, fourth 19, fifth 20 and sixth 21 elements AND, first 22, second 23, third 24, fourth 25 elements OR, first 26, second 27, third 28 and fourth 29 groups of AND elements, first 30, second 31, third 32, fourth 33, fifth 34 and sixth 35 delay elements, the first 36 and second 37 groups of OR elements.

Figure 1 also shows the first 40, second 41-1, third 41-2, fourth 41-3 and fifth 41-4 information inputs of the system, the first 42 and second 43 synchronizing inputs of the system, the first 45, second 46-1, third 46-2, fourth 46-3 and fifth 46-4 information outputs of the system, the first 47 and second 48 synchronizing outputs of the system.

The address selector 10-13 (FIG. 2) comprises a decoder 50, a first 51, a second 52 and a third 53 AND elements, a memory unit 54 made in the form of read-only memory, an OR element 55, a first 56 and a second 57 delay elements.

2 also shows information 58 and synchronizing 59 inputs of the address selector and information 60 and synchronizing 61 outputs of the address selector.

All nodes and elements of the system are made on standard potential-impulse elements. The hardware of the system consists of the hardware of the server, hardware of the workstations and the LAN.

The system software is implemented in a client-server architecture. It consists of server software and workstation software.

The server part of the system operates in any of the possible operating systems; the Oracle 9.0.1 database management system is installed on the server. End-user workstations are running Windows 95 (98) or Windows NT Workstation 4.0, Windows 2000 Professional.

On client sites, the client part of the Oracle 9.0.1 DBMS is installed.

The system operates as follows.

Information input 40 of the system along the data transmission path consistently receives messages (codograms) from information source objects, which may include passport and visa services, registry offices and other regional sources of information on the population of the regions of the Russian Federation.

The codograms contain the feature and information parts (figure 3).

The codegram code from input 40 is entered into register 1 by a synchronizing pulse from input 42, which simultaneously arrives at the direct input of trigger 14 and sets it to a single state. High potential from the direct output of the trigger 14 opens on one input elements 26, 29 And the first and fourth groups, connecting the outputs of the first and second feature parts of register 1 through the corresponding elements 36 and 37 OR of the first and second groups to the information inputs of registers 2 and 4, respectively. In addition, elements 16 and 18 I also open with high potential from the direct output of trigger 14.

The synchronizing pulse from input 42 is delayed by the delay element 30 for the duration of the trigger 14, and passes through the elements 16 AND, 22 OR to the synchronizing input of the register 2, and additionally through the element 23 OR to the synchronizing input of the register 4, ensuring that the region codes are entered into the indicated registers and territories, information about the population of which was sent in the codogram.

The region code from the output of register 2 goes to the input of address selector 10 (Fig. 2), from where it goes to the input of decoder 50.

The decoder 50 of the selector 10 determines the sign of the region, giving out one of its outputs high potential. For definiteness, we assume that a high potential has been received at one input of element 51 I. In parallel with this, a synchronizing pulse from the output of element 22 OR is fed to input 59 of selector 10, where it is delayed by element 56 for the duration of operation of decoder 50, and then polls the states of elements 51- 53 I. Given the fact that only one element 51 And will be open at one input, then passing this element And, the clock pulse arrives, firstly, at the read input of a fixed memory cell of the permanent memory 54, where it is stored the starting address of the server’s memory zone (not shown in the drawing) where it is necessary to record the information received by register 1 from the corresponding region.

Secondly, the same read pulse at the output of the OR element 55 is delayed by the delay element 57 for the duration of reading the contents of a fixed ROM cell and then it is fed to the synchronizing input of register 3, fixing the address code of the memory zone in it.

In parallel, the same clock pulse is transmitted through an OR element 25 to the synchronizing input 59 of the address selector 11, which, similarly to the one described above, provides the server memory zone address code to the information inputs of register 5, where it is necessary to record information received from the territory of the indicated region.

The synchronizing pulse from the output 61 of the selector 11 is delayed by the delay element 31 for the time the territory code was written into the register 5 and through the element 18 opened by the high potential of the trigger 14, element 18 And, firstly, it is output through the system output 47 to the database server interrupt input, and, second, fed to the installation input of the trigger 14, returning it to its original state.

The outputs 45, 46-1, 46-2 of the registers 1,3,5 are connected to the server of the information system (not shown in the drawing), which, upon an interrupt signal from the output 47, polls the contents of the indicated registers and launches the update program for all reports related to the given territory the specified region and the Russian Federation as a whole. For this, the read data is used by the server as input to the functional tasks to be solved in the client-server information system.

To perform the above functions, the information-analytical system uses personality traits recorded in the registration system:

- personal code,

- last name;

- name;

- patronymic;

- gender;

- citizenship;

- date of birth;

- Place of Birth;

- type and details of an identity document;

- address of the place of residence (or place of stay);

- kinship (type of relationship, relative's personal identification code, information about the father

- personal code, surname, name, patronymic, citizenship; information about the mother;

information about the spouse; information about children);

- date of arrival at the place of residence or at the place of stay;

- date of disposal and reason for leaving the Russian population

Federation

- date of entry of the latest information.

The indicators characterizing the size and composition of the population include indicators characterizing the resident population — the population permanently residing in a given territory, the present population — the population residing in a given territory for a given period of time and temporarily absent and temporarily residing, respectively.

The output of the task is quantitative data on the population and its location on a given territory in a given period of time.

The natural movement of a population is a change in population in connection with the processes of birth and death.

Migration is the mechanical movement of a population across a region or between regions of the Russian Federation. Pendulum migration - a systematic movement from city to city (study, etc.).

The result of solving the problem is a summary of the number of residents of a given territory who have changed their place of residence both within the territory and who have left it, as well as a summary of the number of newly arrived residents of this territory for permanent residence.

The solution to the problem of analyzing structural changes in the age and sex composition of the population of the constituent entities of the Russian Federation, depending on a given territory and a given range of years, is based on the use of data on the age level of residents of this territory.

The output of the task is the data on the numerical distribution of the inhabitants of a given territory by various age groups.

The solution to the problem of predicting the population of the constituent entities of the Russian Federation in a given territory in a given range of years is based on the use of adaptive models and population growth curves.

The output of the task is the data characterizing the growth rate (loss) of the population in a given territory in a given period.

The fundamental coincidence of the capabilities of adaptive models and the real conditions of Russian demographic reality suggests that adaptation procedures not only can, but must be used in forecasting the prospective population of the regions of the Russian Federation.

Adaptive models include the Brown, Holt, and Box-Jenkins models. A comparison of adaptive models by such parameters as the average modulus of residuals, the relative approximation error, the Darbin-Watson criterion, the determination coefficient, etc., as well as the meaningful logical analysis of the results they give, allow us to state that the Box-Jenkins model does not look much, but is preferable to competing forecast versions.

The solution to the problem of issuing problem-oriented lists of citizens according to specified address, age and other criteria (voter lists, lists of potential pensioners for the coming years, lists of pre-conscripts, etc.) is also based on signs of registration of citizens.

The output of this task is problem-oriented lists of citizens according to specified address, age and other criteria (voter lists, lists of potential pensioners for the coming years, lists of pre-conscripts, etc.)

We will consider the further operation of the system by the example of obtaining data by users according to the results of solving the problem "Assessment of the dynamics of changes in the number and distribution of the population of the constituent entities of the Russian Federation (fertility and mortality) by the given territory in a given range of years."

To do this, at the user's workplace, a request is generated on “Dynamics of the population”, the volume of the reference “All regions” is indicated, the period, the population indicator is selected and the “Issue all regions” button is pressed (Fig. 4).

After the user presses the button “Issue all regions”, an input 44 receives a pulse that passes through element 20 AND, open at the second input with a high potential from the inverse output of trigger 14 to the direct input of trigger 15 and sets it to a single state, in which trigger 15 opens the element 21 And and closes the element 17 And, blocking the passage of the clock from the input 43.

After passing through the element 21 AND, the synchronizing pulse, firstly, passes through the element 23 OR to the synchronizing input of the register 4, writing into it the territory code from the information input 41-2 and through the element 25 OR to the synchronizing input of the selector 11, forming the memory address of the server, serving a given territory and recorded in the register 5 as described above.

Secondly, the same pulse through the OR element 24 is supplied to the synchronizing inputs of the register 6, writing to it the selected code of the population indicator from the information input 41-3, and address selector 12.

The decoder 50 of the selector 12 decrypts the code of the population indicator, giving out one of its outputs high potential. For definiteness, we assume that a high potential is received at one input of element 52 I. In parallel with this, the synchronizing pulse from input 59 of selector 12 is delayed by element 56 for the duration of operation of decoder 50 and then polls the states of elements 51-53 I. Given the fact that open on one input there will be only element 52 AND, then passing through this element AND, the clock pulse arrives, firstly, at the read input of a fixed memory cell of the permanent storage device 54, where the starting address of the selected indicator is stored population size.

The read pulse at the output of the OR element 55 of the selector 12 is delayed by the delay element 57 for the time of reading the contents of the fixed ROM cell and then goes to the clock input of the register 7, fixing in it the code of the starting address of the memory zone of the selected population indicator.

The pulse from the output 61 of the selector 12 is fed to the clock inputs of the register 8, writing the code of the selected period into it, and to the clock input of the address selector 13.

The decoder 50 of the selector 13 decodes the code of the period for which it is required to provide an indicator of the population, giving out one of its outputs a high potential.

For definiteness, we assume that a high potential is received at one input of element 53 I. In parallel with this, the synchronizing pulse from input 59 of selector 13 is delayed by element 56 for the duration of operation of decoder 50 and then polls the states of elements 51-53 I. Given the fact that open on one input there will be only element 53 AND, then passing through this element AND, the clock pulse arrives, firstly, at the read input of a fixed memory cell of the permanent storage device 54, where the starting address of the selected indicator is stored population, and secondly, the read pulse at the output of the OR element 55 of the selector 13 is delayed by the delay element 57 for the duration of reading the contents of the fixed ROM cell and then goes to the synchronizing input of the register 9, fixing in it the memory address code of the selected period.

After that, the clock from the output 61 of the selector 13, delayed by the delay element while the code is being written to register 9, is output through output 48 to the other interrupt input of the database server, by which the server polls register 5 from output 46-2, register 7 from output 46 -3 and register 9 from output 46-4 and displays the requested data on the screen of the workstation as shown in Fig.4.

In addition, from the output 61 of the selector 13, the sync pulse arrives at the installation input of the trigger 15, returning it to its original state, and the system is ready for a new cycle of operation.

If it is necessary to obtain data for only one region, another key “Issue region” is pressed. In this case, the trigger 15 will remain in its original state and the clock from the input 43 will pass through the element 17 AND, the element 22 OR to the synchronizing input of the register 2, connecting it to work, and as a result, the address of the memory zone of the corresponding region described above way.

Thus, the introduction of new nodes and blocks and new constructive connections made it possible to significantly increase the system’s speed, eliminating the time spent waiting for problems to be solved after requests are received, which made it possible to organize the delivery of data to users in real time.

Sources of information

1. US patent No. 5136708, M. cl. G 06 F 15/16, 1992.

2. US Patent No. 5129083, M. cl. G 06 F 12/00, 15/40, 1992 (prototype).

Claims (1)

The data transmission system of the automated system “State Register of Population”, containing the first register, the information input of which is the first information input of the system, the synchronizing input is the first synchronizing input of the system, and the outputs of the first register are the first information output of the system, the first address selector, the information inputs of which are connected to the corresponding outputs of the second register, the synchronizing input of the first address selector is connected to the output of the first element OR the output of which is connected to the synchronizing input of the second register, the third register, the information inputs of which are connected to the information outputs of the first address selector, the synchronizing output of which is connected to the synchronizing input of the third register, the first group of OR elements, the inputs of which are connected to the corresponding outputs of the AND elements of the first and second groups, and the outputs are connected to the information inputs of the second register, the second group of OR elements, the inputs of which are connected to the corresponding outputs of the AND elements in the fourth group, and the outputs are connected to the information inputs of the fourth register, the synchronizing input of which is connected to the output of the second OR element, the first delay element, the input of which is connected to the first synchronizing input of the system, and the output is connected to one input of the first AND element, and the output is connected to one input of the first OR element, the first trigger, a single input of which is connected to the first synchronizing input of the system, the direct output is connected to another input of the first element AND to one input of the elements AND the first and fourth groups, the other inputs of which are connected to the corresponding outputs of the first register, the inverse output of the first trigger is connected to one of the inputs of the AND elements of the second and third groups, the other inputs of which are the second and third information inputs of the system, respectively, the second address selector, the information inputs of which are connected with outputs of the fourth register, the information outputs of the second address selector are connected to the information inputs of the fifth register, the synchronizing output is connected to the synchronizing the input of the fifth register and with the input of the second delay element, and the output of the fifth register is the third information output of the system, the second element And, one input of which is the second synchronizing input of the system, the other input is connected to the inverse output of the first trigger, and the output is connected to another input of the first element OR, the output of which is connected to one input of the second element OR, the third element AND, one input of which is connected to the direct output of the first trigger, the other is connected to the output of the second delay element, and the output is is the first synchronizing output of the system, the third delay element, the input of which is connected to the output of the third AND element, and the output is connected to the installation inputs of the first trigger, the first, third, and fifth registers, the fourth AND element, whose inputs are connected to the inverse output of the first trigger and the output of the second the delay element, respectively, and the output is connected to one input of the third OR element, the fourth delay element, the output of which is connected to the input of the fifth delay element, and the sixth delay element, which differs that it contains a sixth register, the information inputs of which are the fourth information input of the system, and the clock input is connected to the output of the third OR element, the third address selector, the information inputs of which are connected to the corresponding outputs of the sixth register, and the clock input is connected to the output of the third OR element, the seventh register, the information inputs of which are connected to the information outputs of the third address selector, the clock input is connected to the clock output of the third address selector, the installation input is connected to the output of the fifth delay element, and the outputs are the fourth information output of the system, the eighth register, the information inputs of which are the fifth information input of the system, and the synchronization input is connected to the synchronization output of the third address selector, the fourth address selector, information inputs of which connected to the corresponding outputs of the eighth register, the clock input is connected to the clock output of the third address selector, and the clock the output is connected to the input of the fourth delay element, the output of which is the second synchronizing output of the system, the ninth register, the information inputs of which are connected to the information outputs of the fourth address selector, the synchronization input is connected to the synchronizing output of the fourth address selector, the installation input is connected to the output of the fifth delay element, and the outputs are the fifth information output of the system, the fifth element And, one input of which is the third synchronizing input of the system, the goy is connected to the inverse output of the first trigger, and the output is connected to the input of the sixth delay element, the second trigger, a single input of which is connected to the output of the fifth element And, the installation input is connected to the synchronizing output of the fourth address selector, and the inverse output of the second trigger is connected to the third input of the second element And, the sixth element And, the inputs of which are connected to the direct output of the second trigger and the output of the sixth delay element, and the output is connected to another input of the second and third elements OR, and the fourth lement OR, whose inputs are connected to the synchronization output of the first selector and output addresses of the sixth AND gate, and an output connected to the clock input of the second selector addresses.

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