RU2220440C1 - Data input device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device designed for time-shared execution of multichannel reception and conversion of serial self-synchronizing binary codes from channels having equal or different lengths and bit speeds that can receive information using any exchange method including fixed or different lengths and data error detection and bit synchronization failure has switching device, register, decoder, inputs for first and second components of digital differential signals of serial self-synchronizing binary codes, data code input, data code output, two write inputs, clock input, operation result readiness clear input and operation result readiness output, AND gate, space detector, and serial-to parallel/serial code converter. EFFECT: enlarged functional capabilities and enhanced noise immunity of device. 1 cl, 3 dwg

Description

 The invention relates to the field of computer technology, is intended to perform in the time-division mode, the multi-channel reception and conversion of self-synchronizing sequential binary codes from channels with the same or different code lengths and bit rates, with the information being transmitted by fragments (syllables) of a parallel-serial code accompanied by synchronization signals fragment, information error with an even number of units in the received code, bit synchronization failure with the length of the received code that is not a multiple of the length of the fragment, the readiness of the fragment, and the readiness of the result, and can be used to construct devices for inputting information of the type [1] and local area network (CLS) controllers with a radial topology [2, p. 64-69] with separate and / or multiplexed communication lines (channels), for example, CLS of a local area network (SLS) station according to protocols based on GOST 18977-79 and RTM 1495-75, which are widely used in control systems of aviation, ship and other equipment, located, as a rule, on moving objects [2, p. 57-64].

 As part of the SLS, you can select (see, for example, in [2] on p.221 Fig. 5.9) the core (contains a processor or a single-chip electronic computer (computer), a synchronization and initial installation circuit, and a combined memory (in the general case, contains RAM - random access memory, DOS - dual-port RAM, ROM - read-only memory and RPM - programmable ROM)), CLS (contains a device for inputting information, a device for outputting information and a device for controlling exchange (CID) and synchronization (communication unit with the subsystem ) for mutual synchronization and control of the CLS in general), functionally oriented devices for input-output of information during the interaction of the CLS with external objects (operator panel, adjacent systems, actuators, event sensors in control objects, etc.), a power supply unit and system bus (Q-BUS, ISA, VME or another) for the exchange of information between the components of the SLS under computer control.

 It should be noted that there are a significant number of self-synchronizing codes that can be used in constructing various devices for entering information (bi-pulse code, Manchester code, potential code 2B 1Q, redundant codes like 4B / 5V, etc., [3]), but in local networks are most often used [4, p. 30] RZ code (GOST 18977-79 and RTM 1495-75, foreign standards ARING-429 and AR-ING-575) and the Manchester code (GOST 26765.52-87, foreign standards MIL-STD-1533B and MIL-STD-1773) . In this regard, all further presentation is carried out with an orientation to the RZ code, since it is so far the most widely used in the construction of control systems for on-board equipment. We also note that the greatest noise immunity of information exchange over wired LANs in any equipment is provided by the transmission of a self-synchronizing code by a digital differential (difference) signal [5, p.22-24: Signal transmission lines.].

 For a rational distribution of functions between hardware and software, a device for inputting information and a device for outputting information should be flexibly controlled from a computer and be as invariant as possible to the protocols of the local network and to the type of system backbone.

In on-board equipment, information exchange in the RZ code between SLS, sensors, and data consumers is performed using multiplex LAN and / or separate LAN self-synchronizing serial binary codes (words) in a bit series of lengths
{n} = {16 bit, 24 bit, 32 bit}, (1)
low-order bits ahead and high-order bits control the number of units in the lower bits, separated by pauses Tn of duration
Tp = (4-40) • T, (2)
determined by the period T = 1 / F of the repetition rate of F pulses of the bit synchronization of the transmission of a message, which generally belongs to the set
{F} = {12.5 kHz, 48 kHz, 100 kHz, 250 kHz, 500 kHz, 1000 kHz}. (3)
According to RTM 1495-75, on-board equipment can exchange information in the following three ways:
- asynchronous, which is the main one. In this mode, the sensor continuously cyclically outputs from one to 16 codes (words) of information to a separate LAN;
- upon request, in which the sensor provides the required number of information words to a separate or multiplexed LAN only when a PQ signal is received from a consumer on a separate line of the signal - see [2] Fig. 1.26, b;
- according to readiness, in which the sensor on a separate line exposes to all consumers a ready signal RDY about the beginning of transmission (see [2], Fig. 1.26, c), and then provides the required number of information words to a separate or multiplexed LAN, and the RDY signal should set before the transfer and withdrawn not earlier than its end.

In any of the methods, from any sensor of the jth input channel, information is transmitted over the LAN in the RZ code by a digital differential signal
Uj = Uaj-Ubj (4)
in a complex interference environment with significant common-mode interference
Ucj = (Uaj + Ubj) / 2. (5)
The presence of interference Ucj in the drug (5) distorts both components
Uaj = Ucj + Uj / 2, (6)
Ubj = Ucj-Uj / 2, (7)
differential signal Uj (4) at the inputs ja and jb of the device (consumer), which is characterized by the noise immunity
K = {M (Ucj / Uj)} max, (8)
where j = 0, 1, ..., A is the number of the sensor (input channel of the device), varying from 0 to A inclusive;
Uaj and Ubj - respectively, the first (a) and second (b) components of the signal Uj (4), measured at the inputs aj and bj of the device relative to its common bus (case);
/ - hereinafter, the sign of the arithmetic division operation;
M (X) is the operator of selecting the module of the quantity X enclosed in parentheses, i.e. in (8) the quantities X = Ucj / Uj;
{Q} max is the operator for extracting the maximum value of Q contained in curly brackets, ie in (8), the quantities Q = M (Ucj / Uj).

According to GOST 18977-79 (see, for example, [2, pp. 57-63]) in the RZ code, each bit of information is transmitted by a differential signal Uj (4) during the bit period T = T1 + T2 at T1 = T2 = T / 2 so that in the active part T1 of the bit synchronization period during the time T2 return to zero and during the pause Tn (2), the voltage Uj at the inputs of the device (receiver) is completely described by the expressions
Uj = (10 ± 3) V during T1 when receiving “1” code RZ, (9)
Uj = - (10 ± 3) V during T1 upon receipt of the “0” code RZ, (10)
Uj = ± 1 V during Tn (2) or the time T2 of returning to zero. (eleven)
In real conditions, information is transmitted in the on-board equipment in a complex jamming environment with in-phase interference Ucj (5), which can exceed the useful signal Uj (4) by several times. This led, in particular, to the creation of a specialized micro-assembly AP.004 T53.530.006 TU for receiving and decoding a “48 kHz serial code” over two channels with a common-mode interference level {M (Ucj)} max = 15 V, ie at a real indicator of noise immunity
Cr = 15/7> 2. (12)
In devices for inputting information of type [1], when exchanging according to the main asynchronous method, each message receiving and converting operation must be preceded by a pause detection operation Тп (2) to prepare the device for the next operation, and the final result of each receiving and converting operation using any method exchange should be monitored, for example, to generate an information error signal with an even number of units in the received code and a bit synchronization failure signal when the bit depth deviation is input code from the selected row of lengths of type (1).

 In this regard, the creation of on-board equipment a simple device for entering information by any method of exchange from a variety of sensors with different parameters, defined, for example, by sets of type (1) and (3) under conditions (3), (12) and flexible controllability from a computer in terms of maximum independence from the LAN protocols and the type of system backbone, through the CID, it represents, in our opinion, an urgent technical task, the solution of which will improve the quality of the developed CLS, including devices of the type [1] that support local Networks with minimal hardware costs, high reliability of operation during the exchange of self-synchronizing serial binary codes.

 Reliability of operation is a property of a digital device that characterizes the ability of controls to recognize the output result of work as correct or erroneous with the help of hardware-software controls [6, p.5], ensuring its suitability. Controllability - a property of a device that determines the adaptability of control of its technical condition during manufacturing and operation [6, p.153]. It is precisely controllability that makes it possible to obtain in practice the necessary reliability of the functioning of transmission, information processing and control systems [7, p.12], which in modern equipment are also local network stations.

 The main disadvantage of the known devices is the narrow specialization and limited functionality.

 A single-channel device for inputting information [8] is known, comprising a demodulator, digital differential signal inputs of code RZ, which are information inputs of a demodulator, a single pulse generator, a specialized counter, a clock input connected to the first inputs of the shaper and counter, the second inputs of which are connected to a synchronizing output demodulator, a 33-bit shift register, the information and clock inputs of which are connected to the information output of the demodulator and the output of the shaper, d address decoder, information and control group outputs connected respectively to the information group of the shift register outputs and decoder outputs, the gate input of which is connected to the low-order shift register output, which is the readiness output of the device operation result, the decoder inputs are connected to the address group of the shift register outputs, inputs whose settings in the conversion mode and the initial state are connected to the outputs of the counter.

 According to the RZ code signals and clock pulses, the device [8] receives information asynchronously as follows.

 During each fourth period T of the pause Tn (2), the counter, using clock pulses of the frequency FT = 16 / T, generates two signals that translate the shift register to the initial state (10 ... 0) of the reception and conversion mode. With the end of the pause, the reception and conversion mode of duration Tr = (32 • T) begins, during which the driver generates 32 bit synchronization pulses, for each of which the next bit of the serial binary code from the output of the demodulator is received with a shift to the right. After the end of each sequence of 32 pulses of bit synchronization, the shift register is filled and sets through the decoder on one of the control outputs an address signal of readiness for information, which is removed from the information group of the outputs of the shift register by the addressed recipient. After that, the counter resets the shift register to its initial state (10 ... 0), in which it remains until the next sequence of 32 bit synchronization pulses arrives at it.

 The main disadvantage of the device [8] is the limited scope of its application, which is due both to the limitedness of its functional capabilities (there is no possibility of entering the input code in a number of lengths (1) and control of its functioning), as well as the fact that in modern CLS the function of the final transmission of input information the recipient does not own the input device, but is implemented by the computer with the help of the CID and functionally oriented input-output devices.

 A multi-channel device for inputting information [9] is known, which contains blocks of buffer memory, a counter, a multiplexer, a decoder, a shift register, a trigger, a pulse generator, and elements I. This device is specialized narrowly because it performs the function of sequentially transferring the contents of each of the blocks of buffer memory to shift register for transmission to a computer.

 Of the known technical solutions, the closest to the proposed one is a device for inputting information [1], containing a multiplexer for address switching, respectively, components Uaj (6) and Ubj (7) of the signal Uj (4), the first level converter, two-channel programmable frequency divider, three registers a shift, a data decoder, a pulse generator, a second level converter, five registers, a counter, a trigger, an NAND element, the inputs of the first and second components of digital differential signals of self-synchronizing codes, which are info multiplexer inputs, data code input connected to information inputs of the second, fourth and fifth registers, three information recording inputs from the data data input code, result ready reset input, result ready output, error code output, which is the third register output, and information code output , which is the output of the first register.

The operation of the device [1] will be described when each j-channel information input channel of the three-level digital differential signal Uj (4) of the RZ code is input to the aj and bj inputs, the characteristics of which in time T1, T2 and Tn are determined by the set
{(9), (10), (11)}. (thirteen)
In view of the above, we will sequentially consider the operation of four enlarged parts of the device [1] (register memory of control codes, a switch, a decoder, and a converter of a serial binary code into a parallel code) formed by sets of its individual components.

 The register memory of the control codes contains the second, fourth and fifth registers for storing control codes, respectively, by the data decoder, frequency divider, and through the second level converter by addressing the channel j of the multiplexer and the detection threshold voltage “1” or “0” of the code RZ of channel j. In each of these registers, information is recorded on a separate recording pulse from a common code input of data from a computer.

 The switch contains a multiplexer (formed of two demultiplexer multiplexers) for simultaneous address switching of both components Uaj (6) and Ubj (7) of the signal Uj (4), a first level converter (formed by an addressable multiplexer-demultiplexer with limit resistors and two tolerance zone detectors [ 10], each of which is made on two comparators (521CA1 chip with two limiting resistors) with OR outputs combined, the output of the multiplexer-demultiplexer connected to threshold inputs of tolerance zone detectors, the output of reception “1” of the RZ code is the output of the first tolerance zone detector, the inverting input of which is connected to the non-inverting input of the second tolerance zone detector and to the output of the multiplexer component Ubj, the output of the Uaj component of which is connected to the non-inverting input of the first tolerance detector and the inverting input of the second detector of the tolerance zone, the output of which is the output of the reception "0" of the RZ code, and a second level converter for relaying the addressing of all demultiplexers Iplexers from the fourth register and the formation of a group of threshold voltages, the outputs of which are connected to the signal inputs of the multiplexer-demultiplexer of the first level converter.

In the process of functioning of the device [1] for any selected channel j, the first detector of the tolerance zone at a positive (or negative) threshold voltage level at the output of the multiplexer of the first level converter generates a single receive signal "1" of the RZ code with the value Uaj (or Ubj) corresponding to the value (9), and the second tolerance zone detector generates a single reception signal "0" of the code RZ with the value Ubj (or Uaj) corresponding to the value (10). Thus, in the device [1], the RZ code is detected directly by the signal Uaj (6) or Ubj (7), which contains the interference Ucj (4). Therefore, the device [1] is operable only when limited
M (Uj / 2)> M (Ucj), (14)
those. characterized by noise immunity
Kn = {M (Ucj / Uj)} max <0.5, (15)
which is several times smaller than the value (12) required for the on-board equipment.

 The decoder contains a two-channel controlled frequency divider (each channel of the divider is made on a type 133 IE8 chip, which is a 6-bit binary multiplier that can work as a digital integrator with sequential transfer of the number code from the integrand register), second and third shift registers, data decoder , pulse generator and third register. The decoder is designed to generate clock pulses on the first output of the frequency divider, which is connected to the clock inputs of the second and third shift registers and the first input of the NAND element, bit synchronization pulses on the second output of the frequency divider, which is connected to the clock input of the first shift register, counting input the counter and the input of the recording of the third register, a serial binary code of the received information at the bit output of the data decoder, which is connected to the information input of the first shift register , and an error code, the output of which through the third register is connected to the code output of the data decoder.

 During the operation of the device [1], the operation of the data decoder is programmed from the code output of the second register, and each binary multiplier of the frequency divider is programmed from the corresponding 4-bit code output of the fifth register.

The first (or second) binary multiplier for q = 1 (or q = 2) in a continuous sequence of pulses of the pulse generator and a separate code qC (3: 0) operates cyclically with a cycle time of TC = 16 / f (where f is the pulse repetition rate of the generator clock pulses, which is much higher than the frequency F defined by the set (3), for example f / F = 16) so that during the cycle the output generates the number of pulses determined by the number
Q = qC0 + (2 • qC1) + (4 • qC2) + (8 • qC3), (16)
those. during TC at qC (3: 0) = (0000); (0001); ...; (1110); (1111) the frequency divider generates at the clock output (or at the output of shear pulses of bit synchronization) the number of pulses Q = 0; 1;...; 14; 15, according to which the reception signals "1" and "0" of the RZ code are received respectively in the second and third shift registers (or a fragment of a serial code is received in the first shift register with counting the number of received bits by the counter), according to the contents of which and the contents of the third register, the data decoder produces a fragment (one or several bits) of a sequential code on the bit output, and an error code on the code output when there is uncertainty in the analysis of the contents of the second and third registers.

 Since bit synchronization pulses are generated by the second multiplier at q = 2 according to (16) regardless of the reception signals "1" and "0" of the RZ code, the correct operation of the device [1] is possible with high stability of the pulse generator and control from computers and CCA during exchange only by a non-mainstream method (i.e., by availability or upon request) with a rigid mutual synchronization of the sensor by a PQ signal from a computer or a computer by a RDY signal from a sensor.

 The serial binary to parallel converter contains a first shift register, a first register, a counter, a trigger, an NAND element, an information input connected to an output of a serial binary code of a data decoder, a clock input connected to the first input of an NAND gate and the output of the first a programmable frequency divider binary multiplier, a bit synchronization pulse input connected to the clock input of the first register, the counting counter input and the output of the second binary multiplier nth frequency divider, informational code output connected through the first register with the code output of the first shift register, the readiness output of the operation result connected to the trigger output and the second input of the NAND element, and the readiness reset input connected to the reset inputs of the first register and a trigger, the installation input of which is connected to the write input of the first register and the counter overflow output, the reset input of which is connected to the reset input of the first shift register and the output of the AND-NOT element.

 Before the start of the next conversion operation, the converter is in its initial state (pause mode) - the first shift register, the first register, counter, and trigger are reset to zero. Upon receipt, serial information is transmitted to the first shift register by bit synchronization pulses, which are counted by a bit counter. When the first shift register is filled, the counter generates an overflow signal, according to which the contents of the first shift register are sent to the first register and a trigger is set that sets the operation result ready signal to transmit the contents of the first register to the computer during the ready time T1g <Tn (2). According to the ready signal, clock pulses pass through the AND-NOT element and reset the first shift register and counter, and the computer reads the contents of the first register and generates a ready reset signal to continue entering information from the selected channel, and when the channel is changed, the computer first loads into the fourth and fifth registers new information to prepare the input of information from the desired channel, and when generating the PQ request signal (or when receiving the RDY ready signal), the computer through the CID generates a ready reset signal. The readiness reset signal resets the first register and trigger, which prohibits the operation of the NAND element, and the device [1] is ready for the next operation.

 The main disadvantage of the device [1] is the limited scope of its application and hardware complexity with insufficient noise immunity (due to the low noise immunity according to estimate (15) and the asynchronous generation of bit synchronization pulses by the second binary multiplier of the programmable frequency divider with respect to the formation of the first (or second) the detector of the tolerance zone [10] of the reception signal "1" (or "0") of the RZ code) and the limitations of its functionality (for example, there is no possibility to enter input codes number of lengths according to the main asynchronous method), due to the fact that when constructing the converter [1], primary information was insufficiently taken into account both about information input methods (mainly asynchronous and non-basic - upon request or by availability), and about the parameters of the signals input information described, in particular, by sets (1), (3), (13)) masked by interference Ucj (5) under constraint (12).

 The present invention solves the problem of expanding the field of use of the device by increasing its noise immunity (due to both the use of a switch with a noise immunity index (8) satisfying the constraint (12) and the formation of bit synchronization pulses based on the reception signals "1" and "0" of the RZ code ) and a comprehensive expansion of its functionality by providing the device with the ability to receive information using any method of exchange (asynchronous main or non-main upon request or ready) in particular, in a number of lengths of codes of type (1) and a number of bit rates of type (3) by detecting a pause with a programmable threshold, as well as generating the resulting control signals of the device — an information error signal and a bit synchronization failure signal.

 To achieve this technical result, an information input device comprising a switch, a register, a decoder, inputs of the first and second components of digital differential signals of self-synchronizing binary binary codes of input information channels that are information inputs of the switch, a data code input connected through the register to the address input of the switch , the receiving outputs "1" and "0" of the selected channel of which are connected to the inputs of the decoder, two recording inputs, the input for resetting the readiness of the result of the operation, t Actual input (equivalent to a pulse generator), informational code output and readiness output of the operation result, two elements And, a pause detector, a clock input of which is connected to the device’s clock input, a serial binary code to parallel-serial code converter, a parallel-serial code fragment output which is connected to the information code output, a programmable code input of the pause detection threshold, connected to the code input of the pause detector, and synchronization outputs tion fragment parallel-serial, error information, and the bit synchronization failure fragment readiness connected respectively to the first, second, third and fourth inverter outputs.

 The fifth output of the converter is connected to the readiness output of the result of the operation, the first and second inputs of the recording device are connected respectively to the inputs of the installation in the first and second pause states of the pause detector and to the inputs of the first element And, the output of which is connected to the asynchronous inverse input of the register record and the first input of the second element And, the second input of which is connected to the input of the readiness reset of the result of the operation of the device, and the output is connected to the reset input of the converter, the output of the serial binary deco the dera is connected to the information input of the converter, the clock input of which is connected to the output of the bit synchronization pulses of the decoder and the recording input of the pause detector, which contains two setup inputs in the first and second pause states, respectively, code input, clock input, recording input, potential pause signal output, the output signal of the pause start signal, the first element is NOT, the third and fourth elements AND, from the first to fourth elements OR, the first trigger, counter and the first element AND, the first input of which is connected clock input of the detector, coded input of which is connected to data input of the parallel counter outputs of which MSBs are connected to inputs of the first OR gate whose output is connected to second and third inputs of first OR element.

 The setup input to the first detector pause state is connected to the first input of the third element AND the asynchronous inverse reset input of the first trigger, the asynchronous inverse setup input of which is connected to the setup input to the second detector pause state and connected through the first element NOT to the asynchronous counter reset input, the detector recording input connected to the second input of the third element And, the output of which is connected to the asynchronous inverse input of the counter record, the output of the least significant bit of the counter is connected to the second input of the second OR element, the output of which is connected to the first input of the fourth AND element and the second input of the first AND-NOT element, the output of which is connected to the subtracting counter input of the counter and the second input of the third OR element, the output of which is connected to the first input of the fourth OR element and the clock input of the first trigger, the information input of which is connected to the LOGIC 1 bus.

 The direct and inverse outputs of the first trigger are connected respectively to the second inputs of the fourth AND element and the fourth OR element, the outputs of which are respectively the outputs of the potential pause signal and the pulse start signal of the pause, which are connected respectively to the potential and pulse control inputs of the converter, which contains information, clock inputs , potential control, pulse control, reset, parallel-serial code fragment output, five outputs, second and third NOT elements, fifth OR element, shift register with serial-parallel input and parallel output, second to fifth triggers, second, third and fourth AND-NOT elements, fifth AND element and modulo two control element, the code input of which is connected to the output of a fragment of a parallel-serial code, the outputs of the least significant bits of which are connected to the outputs of the highest bits of the shift register, and the output of the highest bits of the fragment is connected to the information serial input of the shift register and the output of the second trigger, info mation input of which it is an information transmitter input, a clock input coupled to an input of a second NOT member and clock inputs of the second latch and shift register, the parallel information input of which is connected to the input constants of the code, in which the highest bit unit, and the other bits zero.

 The first output of the converter is connected to the output of the second AND-NOT element and the clock input of the third trigger, the output of which is connected to the second output of the converter and the bit input of the control element modulo two, the output of which is connected to the information input of the third trigger, the output of the fifth element And is connected to asynchronous inverse the installation inputs of the third and fourth triggers, the third output of the converter is connected to the output of the fourth trigger, the asynchronous inverse reset input of which is connected to the output of the fifth element OR, the first input of which is connected to the output of the third element NOT, the asynchronous inverse inputs of the reset of the shift register and the installation of the second trigger are connected to the potential control input of the converter, the pulse control input of which is connected to the second input of the fifth element OR, the first input of the second element AND NOT and asynchronous the inverse input of the fifth trigger installation, the asynchronous inverse reset input of which is connected to the reset input of the converter and the first input of the fifth AND element, the second input of which is connected to the output of the third AND-NOT element and the clock input of the fifth trigger, the information input of which is connected to the LOGIC 0 bus.

 The fourth output of the converter is connected to the output of the lower zero bit and the control input "parallel write / shift to the right" of the shift register, the input of the third element NOT and the first input of the fourth element NAND, the output of which is connected to the second input of the second element NAND, the fifth output of the converter connected to the output of the fifth trigger and the first input of the third AND-NOT element, the output of the first least significant bit of the shift register is connected to the second input of the third AND-NOT element, the third input of which is connected to the second input of the fourth electric ment and AND-NOT output of the second element.

 The authors are not aware of technical solutions containing distinctive features equivalent to distinctive features (the introduction of two AND elements, a pause detector, a serial binary code to parallel-serial code converter, a programmable code input for the pause detection threshold and synchronization outputs of a parallel-serial code fragment, information error, failure bit synchronization and readiness fragment) of the proposed device, which, compared with the prototype [1] simplify the device and p expand the scope of its use by increasing its noise immunity and the comprehensive expansion of its functionality due to how to provide information input in any way (asynchronous, ready or on request) with different code lengths and bit rates, for example, belonging to sets (1) and (3) respectively, and the formation of the resulting control signals of the device (information error and bit synchronization failure).

 In FIG. Figure 1-3 shows a functional diagram of a device for inputting information when it is implemented, for example, using a library of integrated circuit elements (ICs) of the 533 series for working with sequential self-synchronizing RZ codes under constraint (12) with parameters defined by sets (1), (3 ) and (13) with a fragment length of a parallel-serial code equal to a byte.

 A device for inputting information (Fig. 1) contains a switch 1, register 2, decoder 3, first 4 and second 5 elements AND, a pause detector 6, a converter 7 of a serial binary code into a parallel-serial code, the first 8 and second 9 recording inputs, connected respectively to the inputs of the installation in the first and second pause states of the detector 6 and the inputs of the element 4, the output of which is connected to the asynchronous inverse input of the register 2 and the first input of the element 5, the input 10 reset readiness result, connected to the second input of the element 5, the output of which is connected to the reset input of the converter 7, the inputs of the first 11 and second 12 components of the digital differential signals of self-synchronizing binary binary codes of input information channels, which are information inputs of switch 1, data code input 13, connected through register 2 to the address input of switch 1, programmable code input 14 of the pause detection threshold connected to the code input of the detector 6, clock input 15 connected to the clock input of the detector 6, outputs 16 and 17 of the switch 1, soy shared with the information inputs of decoder 3 and being respectively the reception outputs "1" and "0" of the self-synchronizing channel code selected by switch 1, output 18 of the serial binary code of decoder 3 connected to the information input of converter 7, output 19 of the synchronization bits of decoder 3 connected with the recording input of the detector 6 and the clock input of the converter 7, the information code output 20, which is the output of a fragment of a parallel-serial code of the converter 7, synchronization outputs fra ment, information error, bit synchronization failure, fragment readiness and result readiness, which are respectively the first 21, second 22, third 23, fourth 24 and fifth 25 outputs of the converter 7, and outputs 26 and 27 of the potential pause signal and the pulse start signal of the detector pause 6 connected respectively to the potential and pulse control inputs of the Converter 7.

 The pause detector 6 (Fig. 2) contains the inputs 8 and 9 of the installation, respectively, in the first and second pause states, code input 14, clock input 15, recording input 19, output 26 of the potential pause signal, output 27 of the pulse pause signal, first element 28 NOT, the third 29 and fourth 30 AND elements, OR elements from the first 31 to the fourth 34, the first trigger 35, the counter 36, and the first AND 37 NAND element, the first input of which is connected to the input 15, the input 8 is connected to the first input of the element 29 and trigger asynchronous inverse reset input 35, asynchronous inverse input is set ki which is connected to the input 9, which is connected through the element 28 to the reset input of the counter 36, the input 19 is connected to the second input of the element 29, the output of which is connected to the asynchronous inverse input of the recording of the counter 36, the high-level outputs of which are connected to the inputs of the element 31, the output of which connected to the first inputs of the elements 32 and 33, the code input 14 is connected to the information parallel input of the counter 32, the low-order output of which is connected to the second input of the element 32, the output of which is connected to the first input of the element 30 and the second input ele ment 37, the output of which is connected to the subtractive counting input of the counter 36 and the second input of the element 33, the output of which is connected to the first input of the element 34 and the clock input of the trigger 35, the information input of which is connected to the LOGIC 1 bus, the direct and inverse outputs of the trigger 35 are connected respectively to the second inputs of the elements 30 and 34, the outputs of which are outputs 26 and 27, respectively.

 The Converter 7 serial binary code in parallel-serial code (figure 3) contains information input 18, clock input 19, code output 20, five outputs from the first 21 to the fifth 25, potential 26 and pulse 27 control inputs, reset input, second 38 and the third 39 elements are NOT, the fifth element 40 OR, the shift byte register 41 with parallel-serial input and parallel output, triggers from the second 42 to the fifth 45, the second 46, the third 47 and the fourth 48 elements NAND, the fifth 49 element AND control element 50 modulo two, code input cat It is connected to a code output 20, the outputs of the least significant bits of which are connected to the high-order outputs of the register 41, the output of the highest bit of the code output 20 is connected to the serial information input of the register 41 and the output of the trigger 42, the information input of which is connected to the input 18, and the input 19 is connected to the input element 38 and the clock inputs of the trigger 42 and the register 41, the input 26 is connected to the asynchronous inverse inputs of the installation of the trigger 42 and reset the register 41, the information parallel input of which is connected to the input of the constant code, whose highest bit is one and the remaining bits are zeros.

 The output of element 46 is connected to the clock input of the trigger 43 and the output 21, the output 22 is connected to the output of the trigger 44 and the bit input of the element 50, the output of which is connected to the information input of the trigger 43, the output of the element 49 is connected to the asynchronous inverse inputs of the installation of the triggers 43 and 44, the output 23 is the output of the trigger 44, the asynchronous inverse reset input of which is connected to the output of the element 40, the first input of which is connected to the output of the element 39, the input 27 is connected to the second input of the element 40, the first input of the element 46 and the asynchronous inverse input trigger 45, the information input of which is connected to the LOGIC 0 bus, the reset input of the converter is connected to the first input of element 49 and the asynchronous inverse input of reset of trigger 45, the clock input of which is connected to the second input of element 49 and the output of element 47, output 24 is connected to the input of the element 39, the parallel write / right shift control input and the low-order zero output of the register 41 and the first input of the element 48, the output of which is connected to the second input of the element 46, the output 25 is connected to the output of the trigger 45 and the first input th element 47, the output of the first register of the younger discharge 41 is connected with the second input member 47, whose third input is connected to the second input element 48 and output element 38.

 As switch 1, you can use, for example, an eight-channel digital differential signal switch [11] with a noise immunity factor Kh = 5 with a margin satisfying restriction (12), containing two comparators, two demultiplexer multiplexers (two 590KN6 microcircuits), two attenuators, a shaper a positive threshold voltage, the output of which is connected to the inverting input of the first comparator, a driver of a negative threshold voltage, the output of which is connected to a non-inverting input of the second a comparator, a differential amplifier, the output of which is connected to the non-inverting and inverting inputs of the first and second comparators, respectively, the outputs 16 and 17 of receiving a "1" and "0" digital differential signal, which are the outputs of the first and second comparators, respectively, an address code three-digit input connected with address inputs of the first and second multiplexer-demultiplexers, information outputs of which are connected respectively to direct and inverse inputs of a differential amplifier, and inputs 11 and 12 p RO and second digital differential signal component associated through the channels of the first and second attenuators to data inputs of the first and second multiplexers-demultiplexers respectively.

 Decoder 3 is made using the principle of decoding the RZ code, implemented in the example of the RZ code decoder circuit [4, p.102, Fig. 2.25] and contains an OR-NOT element, a trigger with asynchronous direct installation and reset inputs, receiving inputs 16 and 17 " 1 "and" 0 "of the RZ code, connected to the inputs of the OR-NOT element and the inputs of setting and resetting the trigger, respectively, the output 18 of the serial binary code of the received information, which is the output of the trigger, and the output of 19 pulses of bit synchronization, which is the output of the OR-NOT element.

 When implementing the device (Fig. 1-3) using the library of elements of the 533 series, the digital components of the device can be performed as follows: register 2 - on the IE IE7 so that the output of the element 4 is connected to the asynchronous inverse input of the download of the IE IE7 used as a register through which the data input 13 is connected to the address input of the switch 1, moreover, for the IS IE7, the reset input and the counting inputs are connected to the LOGIC 0 and LOGIC 1 buses, respectively; counter 36 — on two IE IE7 constituting a byte subtracting counter with asynchronous loading from a parallel information input, operating along the edges of the pulses acting on its subtracting counting input, each IE7 is a 4-bit reversible counter with an asynchronous reset input (connected to by the LOGIC 0 bus), by the asynchronous inverse input of the code entry from the information parallel input and adding (+1) (connected to the LOGIC 1 bus) and subtracting (-1) counting inputs, which ensure operation edges of the pulse counter operating at the counting inputs; register 41 - on two IR11A ICs, forming a byte register with asynchronous inverse reset and synchronous operation along the edges of the pulses at the clock input in the parallel code recording mode (10 ... 0) of the constant at W = 1 or in the mode of receiving an input serial code from the output flip-flop 42 with the least significant bits forward (i.e., with a shift to the right) at W = 0, where W is the signal of the operating mode of register 41 at the corresponding input of each ИР11А IC, which is a 4-bit reverse shift register with parallel output, synchronous to-parallel input and asynchronous reset inverse; flip-flops 31, 42, 43 and 45 on two TM2 ICs; moreover, on flip-flops 42 and 43, asynchronous inverse reset inputs are connected to the LOGIC 1 bus (this is not shown in Fig. 3); element 50 - on IP IP5 - a nine-digit parity and oddity control scheme; the remaining digital components of the device are on the combinational elements of the corresponding ICs, in particular trigger 44 on the two elements 2I-NOT IC LA3, and the trigger of the decoder 3 is on the two elements 2OR-NOT IC LE1.

 A description of the operation of the device is then carried out using the system of positions and designations defined in the following paragraphs.

 1. The input and output (or intermediate variables generated at the outputs of the component parts of the device) direct or inverse variables are denoted by Xi and Yk or NXi and NYk, respectively, where i is the input number and a k is the output number or component number. For example, NX8, NX9, NX10 are inverse signals at inputs 8, 9, 10, respectively, X15 is a direct signal at device input 15, NY4 and NY5 are inverse signals at outputs 4 and 5. In addition, codes at inputs 13 and 14 , output 20, outputs of register 2 and counter 3 are denoted by ID (2: 0), P (7: 0), G (7: 0), A (2: 0) and C (7: 0), respectively, where ID2 , P7, G7, A2, and C7 are the highest, and ID0, P0, G0, A0, and C0 are the least significant digits (i.e., zeros or ones) of these codes.

 The input channel of the device is changed during the exchange in the main asynchronous mode according to the recording signal NY8 = 0 at any moment of time, and in the non-main mode according to the recording signal NY9 = 0, taking into account the time the PQ request or RDY readiness of the selected channel appears in the CLC, moreover, by signal NY8 = 0 (or NY9 = 0), trigger 35 is reset (or set), and code C [7: 0] = P [7: 0] is written to counter 36 (or counter 36 is reset by signal Y28 = X9 = 1 to state C [7: 0] = 0 ... 0).

2. A modified logic function description language ABEL is used, in which the AND, OR, NOT, and EXCLUSIVE OR operators have the designations "&", "#", "!" And "$", respectively. For example, elements 4 and 5 form variables NY4 and NY5 according to the expressions
NY4 = NX8 & NX9, (17)
NY5 = NY4 & NX10, (18)
that is, the sign "N" on the left side of any expression, for example (18), is equivalent to the sign "!" on the right side since
Y5 = (Y4 # X10). (19)
3. The front or the fall of any signal (direct or inverse) is understood as the change in the logical value of this signal from "0" to "1" or from "1" to "0", respectively.

 4. By reset (or setting), for example, trigger 45 means switching this trigger to the state "0" (or "1").

5. During the operation of the device, a direct signal Y25 of the readiness of the result of the operation and an inverse potential signal NY26 of a pause are generated so that the following four modes of its operation can be distinguished:
PP0 standby (idle) when
Y25 NY26 = 0 0, (20)
PP1 conversion when
Y25 NY26 = 0 1, (21)
PP2 readiness when
Y25 NY26 = 1 0, (22)
PP3 readiness and conversion when
Y25 NY26 = 1 1. (23)
In view of the foregoing, we first describe the operation of the component parts of the device, and then its functioning as a whole as a state machine with memory.

 The functioning of the individual components of the device is as follows.

 Register 2 by signal NY4 and code ID (2: 0) works so that for each signal NY4 = 0, ID (2: 0) is asynchronously loaded into register 2 and in the form of code A (2: 0) is sent to the address input of the switch 1.

Switch 1 on signals Ua (7: 0) and Ub (7: 0) the first and second component of the digital differential signals of the eight input information channels of the code RZ and the address code A (2: 0) allocates for the addressed channel
j = A0 + (A1 • 2) + (A2 • 4), (24)
the weakened part of the digital differential signal Uj, described in time by the set (13), and for the selected jth channel in the steady state generates digital signals Y16 and Y17 at the outputs 16 and 17, respectively, of receiving the “1” and “0” RZ codes according to the expressions
Y16 = 1, Y17 = 0 with Uj = Uj (9), (25)
Y16 = 0, Y17 = 1 with Uj = Uj (10), (26)
Y16 = 0, Y17 = 0 with Uj = Uj (11). (27)
Decoder 3, containing a trigger and an OR-NOT element, from digital signals Y16 and Y17 generates at the trigger output 18 a signal Y18 of a serial binary code of information received via channel j (24), and at the output 19 of the OR-NOT element generates NY19 inverse pulses of bit synchronization according to the expression
NY19 =! (Y16 # Y17), (28)
moreover, the trigger of decoder 3 by the signal Y16 = 1 (or Y17 = 1) is asynchronously set (or reset), and when (Y16 # Y17) = 0, this trigger is in a state due to the history of the device.

 Elements 4 and 5 function according to expressions (17) and (18), respectively.

The detector 6 (figure 2) on the signals NX8 and NX9 recording, clock pulses X15, signal NY19 (28) and code P (7: 0) generates an inverse potential NY26 pause signal and pulse NY27 pause start signal according to the expressions
NY26 = Y35 & Y32 = Y35 & [C0 # C1 # ... # C6 # C7], (29)
NY27 = NY35 # NY33 = NY35 # [NY37 # C1 # C2 # ... # C7] (30)
using direct Y35 and inverse MY35 trigger signals 35, as well as signal Y32 and inverse pulses NY33 and MY37, formed by elements 33, 34 and 37 according to the expressions
Y32 = С0 # С1 # ... С6 # С7, (31)
NY33 = N37 # C1 # C2 # ... # C7, (32)
NY 37 =! (X15 & Y32). (33)
During operation, detector 6 for each signal NX8 = 0 is set to the first pause state (trigger 35 is reset, it is loaded into the counter by code P [7: 0] by signal NY29 = NX8 = 0) when operating in the main exchange mode, and by NX9 = 0 is set to the second pause state (trigger 35 is set, counter 36 is reset by signal Y28 = X9 = 1). In addition, with NY4 = 1 and Y35 = 0, trigger 35 at the edge of the pulse NY33 switches to a single state and generates signals Y35 = 1 and NY35 = 0. In this regard, for each inverse signal NY29 = NX8 & NY19 = 0, the counter 36 is fixed in the state C (7: 0) = P (7: 0), which determines the pause detection threshold according to the expression
P = P0 + (P1 • 2) + (P2 • 4) + ... + (P7 • 128), (34)
and at NY4 = 1, NY29 = 1, and Y32 = 1, element 37 generates exactly P (34) pulses NY37 (33) (counted from the last signal NY29 = 0), along the front of each of which the contents of counter 36 decreases by one, and by Pulse P of the NY37 pulse train generates pulse NY33, which at NY35 = 0 passes to the output of element 34 as pulse NY27, and at NY35 = 1, pulse NY33 sets the trigger 35 on the front. At the end of pulse NY33, counter 36 goes into state C (7: 0) = (0 ... 0), element 32 generates a signal Y32 = 0 and prevents the passage of pulses X15 through element 37. Thus, it is detected Part 6 generates a potential inverse pause signal NY26 = 0 at Y35 = 0 or at Y32 = 0 and an inverse pulse signal NY27 starts pause at Y35 = 1 from pulse NY33, which is generated from pulse NY37 at C (7: 0) = (0. ..01) and NY26 = 1. In this regard, after setting the NY8 = 0 signal to the first pause state, detector 6 exits this state (sets signal NY26 = 1) exactly at the beginning of the NY19 = 0 pulse synchronization of the least significant bit of the next n-bit code (n belongs to the set (1) ) of the jth channel. The choice of the frequency f of clock pulses X15 and the programmable code P (7: 0) corresponding to each element F of the set (3) provides multichannel reception of information by the device during the exchange both in the main asynchronous way and non-main (upon request or upon availability). A channel change during an asynchronous exchange can be performed using a signal NX8 = 0 at any moment of time, and when exchanging a non-mainstream method, it must be made according to a signal NX9 = 0, taking into account the time of appearance of a single PQ or RDY signal of the corresponding j-th channel in the CLC. The choice of the threshold P (34) for detecting a pause depending on the bit rate F = 1 / T and the clock frequency f of the pulses X15 at input 15 for any exchange should be carried out from the condition
(T • 1.5) ≥P / f> T, (35)
which transforms into a formula
P = ent (f / F) + C, (36)
where ent is the operator of extracting the integer part of the number (f / F);
C is an integer not less than "1", selected taking into account the fulfillment of the constraint (35).

By the formula (36) for the selected frequency, for example, f = 3 MHz, for C = 1 we obtain many thresholds
{P} = {241, 64, 31, 13, 7, 4}, (37)
each element of which is defined by an element of the set (3) and defines a programmable code P (7: 0) based on (34).

 If for all channels of the device the frequency F belonging to the set (3) is the same, then the corresponding constant code P (7: 0) is connected to code input 14, otherwise the code memory register P (7: 0) should be contained in the CID CLC , loaded software from the computer when changing the frequency F.

 Converter 7 (Fig. 3) yields a serial binary code signal, inverse pulses NY19 (28) bit synchronization, inverse potential signal NY26 (29) pause, inverse pulse signal NY27 (30) start pause and inverse reset signal NY5 (18) generates fragments G (7: 0) of the parallel-serial code of the received information, synchronization pulses Y21 of the fragment G (7: 0), information error signal Y22 with an even number of units in the received code, bit synchronization failure signal Y23 with the length of the received code, not a multiple of a byte signal Y24 readiness of fragment G (7: 0) and signal Y25 of readiness of the result of the operation. During the operation of the converter 7 (as well as the entire device), four operating modes can be distinguished, which are defined by expressions (20) - (23).

 In the initial PP0 mode (20), triggers 43 and 44 are set, trigger 45 is reset, signal NY26 = 0, register 41 is reset, and trigger 42 is set. The converter 7 is set to its initial state by the signal NY5 = NY4 = (NX8 # NX9) = 0 in any mode or by the signal NY5 = NX10 = 0 when switching from PP2 mode (22) to PP0 mode (20).

The transition from PP0 mode to PP1 mode is marked by the appearance of signal NY26 = 1, a sequence of П pulses of NY19 bit synchronization and signal Y18 of a serial binary code, the length of which must belong to series (1), i.e., for the correct functioning of the device, the number П must also belong row (1). At the edge of each NY19 pulse, trigger 42 is set to
G7 = Y18 (at the moment of front NY19), (38)
and the contents of register 41 with Y24 = 0 are shifted to the right with the reception of the G7 bit G7 (at the time of NY19 front), and with Y24 = 1, the highest bit G6 of register 41 is set, and the lower bits are reset, i.e. G (6: 0) = (1,000,000), Y24 = 0. Therefore, for example, at P = 32 after the end of the 8th, 16th, 24th, 32nd pulse of NY19, register 41 will set the ready signal Y24 to 0- 1st, 2nd, 3rd, parallel-serial code fragment
G (7: 0) = D (7: 0), D (15: 8), D (23:16), D (31:24), (39)
and then form an impulse
Y21 = (Y19 & Y24) # Y27 (40)
synchronization of fragment (39) by the 9th, 17th, 25th pulses NY19 and pulse NY27. On the edge of each pulse Y21, the trigger 43 is set to
Y22 = Y50 (at the moment of front Y21), (41)
signal defined
Y50 = (G7 $ G6 $ G5 $ G4 $ G3 $ G2 $ G1 $ G0) $ Y22, (42)
which forms the element 50 according to the principles of control modulo two [5, p.67-77: "2.2. Control schemes"], for example, the received code D (31: 0) containing four fragments of a parallel-serial code (39). For each NY27 = 0 pulse, trigger 45 is set and sets the signal Y25 = 1 for the result to be ready, and element 40 only with NY39 =! Y24 = 0 generates a NY40 = (! Y24) # NY27 = 0 pulse to reset trigger 44. In this regard, in the mode PP2 (22) or PP3 (23) signals Y22 and Y23 are generated so that when (Y22 # Y23) = 0, no failures were detected, when Y22 = 1 an information error was detected (an even number of units in the received code, for example, code D (31: 0)), when Y23 = 1, a bit synchronization failure was detected, i.e. it is determined that in the completed conversion operation, the number of NY19 pulses is not a multiple of eight.

At the end of the NY27 pulse, the detector 6 sets the NY26 = 0 pause signal and the device switches to PP2 mode (22), in which the computer interrupts the signal Y25 = 1 to signal the completion of the next conversion operation. During the execution of the interrupt program, the computer can generate a signal NX10 = 0 for resetting the result, which, through element 5, resets the trigger 45, and through elements 5 and 49 sets the triggers 43 and 44. If the computer does not generate signal NX10, then j device information signal Uj code RZ decoder 3 generates the next sequence of P pulses NY19 bit synchronization. By the first pulse of this sequence, the device switches to PP3 mode (23), and by the eighth pulse NY19, element 47 forms a pulse
NY47 =! (Y19 & G0 & Y25), (43)
which through element 49 establishes the triggers 43 and 44 and immediately flips the trigger 45, thereby switching the device to PP1 mode (21).

 The functioning of the device as a finite state machine with memory consists in alternating modes of its operation, for example, PP0, PP1, PP2, PP3, PP1, etc., so that: transition to PP0 can be carried out from any mode by signal NY4 = (NX8 # NX9) = 0 entries or from PP2 mode by the signal NX10 = 0 result ready reset; transition to PP1 - from PP0 directly by the first pulse NY19 of the sequence of P pulses of bit synchronization, as well as from the PP3 mode by the signal NX10 = 0 or the end of the NY47 pulse; transition to PP2 - from PP3 at the end of the NY27 impulse; transition to PP3 - from the PP1 mode during the action of the NY27 pulse or from the PP2 mode directly by the first pulse NY19 of the sequence of P pulses of bit synchronization.

The presence at the outputs of the device of synchronization signals Y21 and Y24 of the readiness of each fragment G (7: 0) of a parallel-serial code (its recording at n = 32 is given in (39)) and Y25 of the result readiness provides many options for transmitting the result of the operation to the computer via the УУО
{D ((nl): 0), Y22, Y23}, (44)
where n - belongs to the set (1).

 Let us describe two possible options for entering the result (44) by the pulses Y21 of synchronization and Y24 of the readiness of the fragment.

 In the first case, in the CID, on the edge of each pulse Y21, the current fragment G (7: 0) is loaded into the register of type IR23 and causes an interruption of the computer of the first type. When executing the first interrupt program, the computer generates code D ((n-1): 0) in its internal RAM. At the end of each operation, the device sets the signal Y25 = 1, causing the interruption of a second type of computer. When executing the second interrupt program, the computer reads the remaining part {Y22, Y23} of the result (44), generates a signal NX10 = 0 to reset the result, then when (Y22 # Y23) = 0 it sends the information part of the code D ((n-1): 0) to the subscriber (receiver), and with (Y22 # Y23) = 1, the result (44) is ignored, since an information error was detected with Y22 = 1 or / and a bit synchronization failure with Y23 = 1.

 In the second case, the CID for each signal Y24 = 1 writes each fragment G (7: 0) to its RAM cell (RAM or DOS, or the hardware stack or register). At the end of each operation, the device sets a computer interrupt signal Y25 = 1, which executes an interrupt program similar to the second interrupt program described for the first case.

 The description shows that the proposed device due to its essential features is simpler than the prototype [1] and compared with it has a wider field of use, as it has the required noise immunity with advanced functionality. In this regard, this device can be used to build onboard hardware-based simple CLSs that support, with high reliability, in a local area network with a radial topology a multi-channel exchange of self-synchronizing sequential binary codes with different lengths and speeds, belonging, for example, to series (1) and (3), respectively.

Literature
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 2. Organization of serial multiplex channels of automatic control systems. S.T. Horsetail, V.V. Doroshenko, Leningrad. Branch, 1989 .-- 271 p.

 3. "2.2. Methods for transmitting discrete data at the physical level" - p. 132-149 in the book: Computer Networks. Principles, technologies, protocols. V.G. Olifer, N.A. Olifer - St. Petersburg. Peter. 2001 .-- 672 p.

 4. Yu.V. Novikov, D.G. Karpenko. The equipment of local area networks: functions, selection, development. Edited by Yu.V. Novikov. M .: Publishing house ECOM, 1998. - 288 p.

 5. Ugryumov E.P. Digital circuitry. St. Petersburg: BHV - Petersburg, 2001 .-- 528 s.

 6. Scherbakov N.S. The reliability of digital devices. - M.: Mechanical Engineering, 1989 .-- 224 p.

 7. Monitoring the functioning of large systems. G.P. Shibanov, E.A. Artemenko, A.A. Mateshkin, N.I. Tsiklinsky. Ed. Honored Inventor of the RSFSR Doctor of Technical Sciences G.P. Shibanova. M .: Engineering, 1977, 360 pp.

 8. A.S. 1068927, G 06 F 3/04, A device for entering information. L.P. Gorokhov, R.Yu. Halfan and V.A. Genin. Publ. 01/23/1984. Bull. 3.

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Claims (1)

A device for inputting information, comprising a switch, a register, a decoder, inputs of the first and second component of digital differential signals of self-synchronizing binary binary codes of input information channels, which are information inputs of the switch, a data code input connected through the register to the address of the switch, reception outputs "1" and "0" of the self-synchronizing code of the selected channel of which are connected to the inputs of the decoder, two recording inputs, the input for resetting the readiness of the result of the operation, clock input, inf ramational code output and readiness output of the result of the operation, characterized in that it additionally contains two AND elements, a pause detector, the clock input of which is connected to the clock input of the device, the serial binary code to parallel-serial code converter, the output of the parallel-serial code fragment of which is connected with information code output, programmable code input of the pause detection threshold connected to the code input of the pause detector, and fragment synchronization outputs and a parallel-serial code, information error, bit synchronization failure, and fragment readiness, respectively connected to the first, second, third, and fourth outputs of the converter, the fifth output of which is connected to the readiness output of the operation result, the first and second inputs of the recording device are connected respectively to the inputs of the installation to the first and second states of the detector pause and the inputs of the first AND element, the output of which is connected to the asynchronous inverse input of the register record and the first input of the second element nta And, the second input of which is connected to the readiness reset input of the device operation result, and the output is connected to the converter reset input, the decoder serial code output is connected to the converter information input, whose clock input is connected to the decoder bit synchronization pulse output and the pause detector recording input, which contains two setup inputs to the first and second pause states, respectively, code input, clock input, recording input, outputs of the potential pause signal and pulse signal start of pause, the first element is NOT, the third and fourth elements AND, from the first to fourth elements OR, the first trigger, counter and the first element AND, the first input of which is connected to the clock input of the detector, the code input of which is connected to the information parallel input of the counter, the high-level outputs of which are connected to the inputs of the first OR element, the output of which is connected to the first inputs of the second and third OR elements, the installation input to the first detector pause state is connected to the first input of the third AND element and AC a chronic inverse reset input of the first trigger, the asynchronous inverse input of the installation of which is connected to the installation input in the second state of the detector pause and connected through the first element NOT to the counter reset input, the detector recording input is connected to the second input of the third element And, the output of which is connected to the asynchronous inverse input counter recording, the low-order output of the counter is connected to the second input of the second OR element, the output of which is connected to the first input of the fourth AND element and the second input of the first element AND-NOT, the output of which is connected to the subtracting counter input of the counter and the second input of the third OR element, the output of which is connected to the first input of the fourth OR element and the clock input of the first trigger, the information input of which is connected to the LOGIC 1 bus, the direct and inverse outputs of the first trigger are connected respectively, with the second inputs of the fourth AND element and the fourth OR element, the outputs of which are respectively the outputs of the potential pause signal and the pulse signal of the beginning of the detector pause, which respectively, with the potential and pulse control inputs of the converter, which contains information, clock, potential control, pulse control, reset, parallel-serial code fragment outputs, five outputs, the second and third elements NOT, the fifth OR element, shift register with sequential parallel input and parallel output, triggers from the second to the fifth, second, third and fourth elements AND NOT, the fifth element AND and the control element modulo two, the code input of which is connected to the output of a fragment of a parallel-serial code, the outputs of the least significant bits of which are connected to the outputs of the highest bits of the shift register, and the output of the highest bits of the fragment is connected to the information serial input of the shift register and the output of the second trigger, the information input of which is the information input of the converter, the clock input of which is connected to the input the second element NOT and the clock inputs of the second trigger and the shift register, the parallel information input of which is connected to the input of the cons code Anty, in which the highest bit is one, and the remaining bits are zeros, the first output of the converter is connected to the output of the second AND-NOT element and the clock input of the third trigger, the output of which is connected to the second output of the converter and the bit input of the control element modulo two, the output of which is connected to the information input of the third trigger, the output of the fifth element And is connected to the asynchronous inverse inputs of the installation of the third and fourth triggers, the third output of the converter is connected to the output of the fourth trigger, asynchronous inverse the reset input of which is connected to the output of the fifth OR element, the first input of which is connected to the output of the third element NOT, asynchronous inverse inputs of the shift register reset and the second trigger setting are connected to the potential control input of the converter, the pulse control input of the converter is connected to the second input of the fifth OR element, the first input of the second AND-NOT element and the asynchronous inverse input of the fifth trigger installation, the asynchronous inverse reset input of which is connected to the reset input of the converter and the first input of the fifth AND element, the second input of which is connected to the output of the third AND element and the fifth input of the fifth trigger, the information input of which is connected to the LOGIC 0 bus, the fourth output of the converter is connected to the low-order zero output and the Parallel Recording / Shift input to the right "of the shift register, the input of the third element NOT and the first input of the fourth element AND, the output of which is connected to the second input of the second element AND, the fifth output of the converter is connected to the output of the fifth trigger and by the first input of the third AND-NOT element, the output of the first least significant bit of the shift register is connected to the second input of the third AND-NOT element, the third input of which is connected to the second input of the fourth AND-NOT element and the output of the second NOT element.

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