RU2208907C2 - Error correction device with extended set of decision rules and erase signal inclusion - Google Patents

Abstract

FIELD: telemechanics and computer engineering. SUBSTANCE: error correction device that may be used in digital data transmission and processing systems for error correction in case of five-fold message transmission has decision unit, four selector switches, four shift registers, and synchronizer; novelty is introduction of quality detector for analyzing each word character received and for generating erase signal, as well as erasure correction unit including erase signal for most reliable similar-name characters of message repeated many times. EFFECT: enhanced noise immunity including erase signal. 1 cl, 5 dwg

Description

 The invention relates to telemechanics and computer engineering and can be used in systems for transmitting and processing discrete information for error correction during five-fold repetition of messages.

 Known devices for majority decoding of triplicate messages during serial reception (see USSR AS 206634, 207247, 31a 7/01, 1968, 387521, H 03 K 13/32, 1975), containing two shift registers and logical elements .

 The disadvantage of these devices is the limited functionality, which does not allow their use in adaptive systems for a wide class of codes with repetition.

 In addition, devices are known for majority decoding (see USSR AS 884263, H 04 L 1/10, H 03 K 13/32, 1981, 677123, H 04 L 1/10, 1979, 944129, H 04 L 1/08, 1982, 980114, G 08 C 19/28, 1982, 1005151, G 08 C 25/00, 1982, RF patent 1439750, H 03 M 13/00, 1988, 2023348, Н 03 М 13/02, 2012134, Н 03 М 5/00, 1994), which contains shift registers and logic elements with corresponding relationships that allow majority, three, five or more repetitions of a message to be processed without loss of intermediate results.

 The disadvantage of these devices is the limited functionality, which is manifested in the fact that not all possible combinations of message repetitions are analyzed.

 Of the known devices, the closest in technical essence is an error correction device with an expanded set of decision rules described in patent 2152129, H 03 M 13/43, 2000

 This device contains four shift registers, four switches, a decision block, a synchronizer, and corresponding communications.

 The disadvantage of this device is its low noise immunity, since, implementing a complete set of decision rules, the erase (Θ) signal is not taken into account for the most reliable symbols of the same name of a repeated message, which reduces the noise immunity of the device.

 The aim of the present invention is to increase the noise immunity of the device, which takes into account the signal "erase" (Θ) for the most reliable characters of the same name repeatedly message.

 This goal is achieved by the fact that in the device containing the decision block, the outputs of which are the outputs of the device, four switches, the outputs of which are connected to the information inputs of the same shift registers, a synchronizer, the clock input of which is the clock input of the device, the first and third outputs of the synchronizer are connected respectively to the combined first control inputs of the first switch and the first shift register, the combined first control inputs of the second switch and the second shift register, combined by the first control inputs of the third switch, third shift register, decision block, second control inputs of the first and second switches, first and second shift registers, while the first information input of the decision block is combined with the first information inputs of the switches, the second information inputs of which are simultaneously connected with the corresponding inputs of the decisive block and the outputs of the shift registers, the installation inputs of which are combined with the installation inputs of the device and the installation input of the synchronizer, the fourth output of which is respectively connected to the combined third control inputs of the second switch, the second shift register, the second control inputs of the third switch, the third shift register, the decision block and the first control inputs of the fourth switch and the fourth shift register, while the fifth output synchronizer is simultaneously connected to the second control inputs of the fourth switch and the fourth shift register, the third control input The erasure correction unit and the quality detector, the first and second outputs of which are respectively connected to the first and second inputs of the erase correction unit, the output of which is erased, are output to the third, first switches, third, first shift register, decision block and fourth control inputs of the second switch and second shift register combined with the first information inputs of the switches and the deciding unit, the third and sixth inputs of the erasure correction unit are connected respectively to the outputs of the first and fourth registers strov shift, and the seventh, ninth, eleventh inputs of the block erasure correction, respectively, are connected with the first, third, fifth outputs of the synchronizer, while the eighth, ninth inputs of the block erasure correction are connected to the second and fourth inputs of the synchronizer and the corresponding control inputs of the first switch and the first shift register , and the input of the quality detector is the information input of the device.

 The device comprises switches 1-4, registers 5-8, a synchronizer 9, a decision unit 10, an erasure correction unit 11, and a quality detector 12.

 In FIG. 1 shows a block diagram of a device; figure 2 - timing diagrams explaining the operation of the device; figure 3 is a functional diagram of a crucial unit; figure 4 is a functional diagram of a block for erasure correction; in FIG. 5 is a timing chart explaining the principle of error correction in the second message retry when the erase signal is taken into account.

 The device comprises (Fig. 1) a first to fourth switch 1-4, a first to a fourth shift register 5-8, a synchronizer 9, a deciding unit 10, an erasure correction unit 11, and a quality detector 12.

 Switches 1-4 are intended for switching information inputs of the corresponding shift registers 5-8. The outputs of the switches are register inputs.

 Shift registers 5-8 are standard elements of memory and are used to store, overwrite, issue information circulating in the device. The distribution of stored information in registers 5-8 is presented in table. 1.

 The outputs of the registers 5-8 are simultaneously connected to the second information inputs of the switches 1-4, the corresponding inputs of the decision block 10 and the third to the sixth input, respectively, of the block 11 of the erasure correction.

 The synchronizer 9 ensures the normal functioning of all elements of the device. Figure 2 presents the timing diagram of the synchronizer. After highlighting the cyclic synchronization marker, which determines the beginning of the frame of a repeatedly repeated message, an impulse to set the device’s memory elements to the zero state is allocated (see FIG. 2 SIO). After that, block 9 provides a packetization of SI clock pulses arriving at its input in the sequence SI1 ÷ SI5. The number of pulses in the packet corresponds to the number of n characters in one message retry. To perform the functions of such a unit, there are already a large number of technical solutions described in the technical literature. For example, in the book Gurov B.C., Emelyanov A.E., Etrukhin N.N., Osipov V.G. "Discrete Information Transmission and Telegraphy". - M .: Communication, 1974. - C. 135.

 Clock input SI synchronizer 9 is the clock input of the device. The first and third outputs of the synchronizer 9 are connected respectively to the combined first control inputs of the first switch 1 and register 5, the combined first control inputs of the second switch 2 and the second register 6, the combined first control inputs of the switch 3, register 7, decision block 10, second control inputs 1 and 2 switches 5 and 6 registers. The fourth output of the synchronizer 9 is respectively connected to the combined third control inputs of switch 2, register 6, second control inputs of switch 3, register 7, decision block 10 and first control inputs of switch 4, register 8. The fifth output of block 9 is simultaneously connected to the second control inputs of switch 4, register 8, the third control inputs of switches 1-3, registers 5, 7, decision block 10 and the fourth control inputs of switch 2 and register 6.

The decisive block 10 is designed to form an extended set of decisive majority (maj) rules. At the first output of block 10, the results of majority processing of the first three repetitions of maj (X ₁ , G ₂ , G ₃ ) messages at the time of receiving the third X ₃ repetition and the last three maj (G ₃ , G ₄ , G ₅ ) at the time receiving the fifth X ₅ repetition. The result maj (G ₂ , G ₃ , G ₄ ) of the processing of the second, third, fourth repetitions is output to the second output of block 10 at the time of receiving the symbols of the fourth repeat X ₄ . The output maj (X ₁ , G ₄ , G ₅ ) of processing the same characters of the first, fourth, fifth repetitions at the time of receiving the characters of the fifth repetition of X ₅ is output to the same output. The third output of block 10 receives the result of majority processing maj (G ₂ , G ₄ , G ₅ ) upon the arrival of the symbols of the fifth repetition X ₅ . The fourth output gives the result of majority processing in total for five repetitions of the message maj (X ₁ , G ₂ , G ₃ , G ₄ , G ₅ ).

 A possible variant of the functional block 10 is shown in figure 3, which contains the logical elements in the basis of AND-NOT 10-1 ÷ 10-53.

On logical elements 10-1 ÷ 10-3, 10-16, the first decision rule is implemented
maj (X ₁ , G ₂ , G ₃ ) = X ₁ G ₂ + X ₁ G ₃ + G ₂ G ₃ . (1)
Elements 10-4 ÷ 10-6, 10-17 form the second rule
maj (G ₂ , G ₃ , G ₄ ) = G ₂ G ₃ + G ₂ G ₄ + G ₃ G ₄ . (2)
Elements 10-7 ÷ 10-9, 10-18 determine the majority result of the last three repetitions of five, the third rule
maj (G ₃ , G ₄ , G ₅ ) = G ₃ G ₄ + G ₃ G ₅ + G ₄ G ₅ . (3)
Elements 10-10 ÷ 10-12, 10-19 implement the fourth rule
maj (X ₁ , G ₄ , G ₅ ) = X ₁ G ₄ + X ₁ G ₅ + G ₄ G ₅ . (4)
Elements 10-13 ÷ 10-15, 10-20 form the fifth rule
maj (G ₂ , G ₄ , G ₅ ) = G ₂ G ₄ + G ₂ G ₅ + G ₄ G ₅ . (5)
The group of elements 10-26 ÷ 10-35, 10-41, 10-42 allows majority processing in total for five repetitions of the message, the sixth rule:
maj (X ₁ , G ₂ , G ₃ , G ₄ , G ₅ ) = G ₂ G3G ₄ + G ₃ G ₄ G ₅ + G ₂ G ₃ G ₅ + G ₂ G ₄ G ₅ + X ₁ G ₂ G ₃ + X ₁ G ₃ G ₄ + X ₁ G ₄ G ₅ + X ₁ G ₂ G ₅ + X ₁ G ₂ G ₄ + X ₁ G ₃ G ₅ .

(6)
The remaining elements of block 10 perform the functions of logical elements AND, OR.

 Block 11 correction erasures contains (figure 4) elements AND 11-1 ÷ 11-8, 11-12 ÷ 11-23, 11-36 ÷ 11-38, elements OR NOT 11-9 ÷ 11-11, Prohibition 11 -27 ÷ 11-32, OR 11-24 ÷ 11-26, 11-33 ÷ 11-35, 11-39.

 The erasure correction unit 11 carries out error correction by the erasure vector, i.e., the vector marking unreliable characters of the received code combinations, and performs the following functions.

Upon receipt of the symbols of the second X ₂ repetition of the message, the block 11 performs element-by-element comparison with the symbols of the first X ₁ repetition, taking into account the erase signal (Θ) for the corresponding symbol of the second repetition. In case of mismatch of the same names of the compared repeats, the symbol of the second repetition of the message marked with the signal Θ is inverted. This process is reflected in the timing diagram of FIG. 5 and is implemented on the elements 11-2, 11-12, 11-20, 11-13, 11-39.

In the third step N = 3 of the operation of the device, when the characters of the third repeat X ₃ are received, block 11 corrects the unreliable symbol of the third repeat, different from the unambiguous symbols of the same name in the first X ₁ and the second corrected G ₂ repetitions, in the presence of the erase signal Θ, marking an unreliable symbol of the third repetition.

где N=3, 4, 5.In the subsequent steps of the operation of the device N≥4, i.e. when receiving symbols of the fourth X ₄ and fifth X ₅ repetitions, block 11 makes a similar correction of those symbols marked with a signal Θ for which the previous symbols of the same name satisfy the uniqueness condition (R)

where N = 3, 4, 5.

Работа блока 11 задана табл. 2.

The operation of block 11 is given in table. 2.

 The output of the erasure correction unit 11 is combined with the first information inputs 1–4 of the switches and the deciding unit 10. The first – second inputs of the block 10 are outputs of the quality detector 12. The third – sixth inputs of the block 10 are connected respectively to the outputs of 5–8 registers. The seventh, ninth, eleventh inputs of block 11 are respectively connected to the first, third, fifth outputs of synchronizer 9, and the eighth, tenth inputs of block 11 are connected to the second and fourth outputs of synchronizer 9 and the corresponding control inputs of switch 1 and register 5.

The quality detector 12 is designed to analyze each received symbol of the code combination X _i and generate a “erase” signal Θ if the received symbol cannot be identified with either “1” or “0”. The input of the quality detector 12 is the information input of the device.

 Examples of technical implementation of quality detectors are given in the book: L.P. Purtov et al. Theory and technique of data transmission and telegraphy. - L .: YOU, 1973.

 The device operates as follows.

The initial state of the memory elements of the device is zero, which is provided by the installation clock of the SIO (figure 2). The symbols of the first repetition X _{1 of the} message from the communication channel are sent to the quality detector 12, where they are identified with "0" or "1", after which they pass to the first input of block 11, where through the AND 11-1 element, open by the SI1 clock pulses, the OR element 11 -39 go to the output of block 11. From the output of block 11, the characters of the first repetition of the message through switch 1, opened by clock pulses SI1, are written into register 5 with a repetition rate of SI1.

 Thus, at the end of the reception of the first repetition of the message, it appears in the shift register 5.

Synchronizer 9, having counted n clock pulses, will give out a pack of SI2 clock pulses at the second output, which controls the operation of the device blocks. The symbols of the first repeat ejected by SI2 clock pulses from register 5 go to the third input of block 11. At the same time, information from the communication channel is received to the first input of block 11 through the quality detector 12, and the signal Θ generated by the quality detector 12 is received to the second input of block 11. In block 11 elements And 11-2, 11-20, the adder modulo two 11-12, 11-3 implement the correction algorithm (see Fig.5) unreliable symbol of the second repeat. The adjusted second repeat G ₂ through open SI2, switch 2 is recorded in register 6. And the characters of the first repeat through switch 1 are written into register 5. The status of registers 7, 8 is zero.

Upon receipt of the third repetition of the message, the information of the first X ₁ and second G ₂ repeats, stored respectively in registers 5 and 6, is read to the third and fourth inputs of block 11, the first input of which receives the characters of the third X ₃ repeat. Further, the latter are processed by block 11, taking into account the “erase” signal supplied to the second input of block 11, according to the described algorithm of condition (7), (8). Moreover, in the operation of block 11 of all possible states of the same symbols of two repetitions, only coincident symbols X ₁ = G ₂ are involved.

In the event that X ₁ = G ₂ = 1 (N = 3 of Table 2) and the signal “erase” Θ = 1 is present, which corresponds to the unreliable symbol of the third repetition, then the elements And 11-3, 11-15 are triggered. The signal from the output of AND 11-15 through OR 11-24 will prohibit the passage of the X ₃ symbol through Prohibition 11-28 and will go through Prohibition 11-27, OR 11-33, 11-36, 11-39 to the output of block 11.

In the case when X ₁ = G ₂ = 0 and Θ = 1, then the chain of elements 11-9, 11-14, 11-21, 11-24, 11-28, 11-33, 11-36, 11 -39, preventing the passage of the corresponding symbol X ₃ through Prohibition 11-28. As a result, the symbol of the third repeat marked by erasing Θ becomes zero.

The corrected characters of the third repeat G ₃ through the switch 3 are recorded in register 7, simultaneously entering the first input of block 10, the second and third inputs of which are read from the registers 5, 6 characters of the first X ₁ and second G ₂ repetition, simultaneously overwriting in their registers through switches 1, 2.

 The symbols of the first three repetitions in block 10 pass through a majority element that implements a 2x3 criterion, from the output of which the generated result of majority processing of the first decision rule (1) is issued to the first output of the device. The operation of all blocks of the device upon receipt of the symbols of the third repetition is controlled by SI3 clock pulses (figure 2).

When the fourth repetition is received, the characters of the first three repetitions are read from registers 5–7 (see Table 1) using SI4 clock pulses. The readable characters go to the corresponding inputs of block 11, the first input of which receives the characters of the fourth X ₄ repeat. In block 11, taking into account the signal Θ according to the most reliable preceding symbols of the same name (see table 2, condition 7), error correction is performed in the symbols of the fourth repetition of G ₄ .

The corrected symbols of the fourth repetition of G ₄ through the switch 4 are recorded in register 8, simultaneously entering the first input of the decision block 10, the third and fourth inputs of which are read from registers 6, 7, the symbols of the second G ₂ and third G ₃ repetitions, corrected by the signal Θ, simultaneously overwriting through switches 2, 3 in their registers.

 The symbols of the second, third, fourth repetitions in block 10 pass through the majority element that implements the 2x3 criterion, which forms the second (2) decision rule. This result is output to the device. Management of the blocks is carried out by SI4 clock pulses (figure 2).

When receiving the fifth repetition X ₅ , the SI3 clock pulses generated by block 9 push the result X ₁ , G ₂ , G ₃ , G ₄ stored in registers 5-8 to the corresponding inputs of the erasure correction block 11. The symbols X _{5 of the} fifth repetition arrive at the first input of block 11. In block 11, taking into account the signal Θ arriving at the second input from the output of the quality detector 12, according to the most reliable previous symbols (see table 2, condition (7)), error correction is performed in the symbols of the fifth repetition.

The corrected characters of the fifth repetition of G ₅ through switch 1 are recorded in register 5, for possible processing in the next cycle, if the message frame has a larger N> 5 number of repetitions. At the same time, G ₅ together with X ₁ , G ₂ , G ₃ , G ₄ enter the decision block 10, where an expanded set of decision rules (3) ÷ (6) is implemented and issued to the corresponding outputs of the device. SI5 clocks control the operation of the device, at this step N = 5.

The reliability of achieving the objectives of the invention is confirmed by the following data. If in the known device the probability of distortion of a single symbol in the final code combination is estimated by the value of P _e1 = mP ₀ ^m , where m is an indicator of an odd number of repetitions N = 2m-1, m = 3; P ₀ - the probability of distortion of a single character code combination, then in the proposed device:
P _e2 ≅ (2m-1) • P $\genfrac{}{}{0ex}{}{\text{m + 1}}{\text{0}}$ • P _T ,
where P _T is the probability of symbol transformation in the absence of Θ.
In this case, information loss can be estimated by the expression (V.I. Klyuchko. Methods and means of protecting information from errors in ACS. Ministry of Defense of the USSR, 1980. - 255 p.):
P _P = 1- (1-P _e ) ⁿ ≅ n • P _e .
Then, if P ₀ = 10 ^-2 (low quality channel), P _t = 2 • 10 ^-2 , m = 3, then
P _n1 = n • (2m-l) • P ₀ ^{m + 1} , and P _n2 = n • (2m-1) • P ₀ ^{m + 1} • P _T.

Таким образом, при приеме пяти повторений сообщения устройство реализует расширенный набор решающих правил. При этом учет сигнала "стирание" Θ позволяет исправить определенную долю ошибок в повторе по наиболее надежным предшествующим символам, что снижает общее число ошибок в принимаемом сообщении. Это облегчает коррекцию ошибок расширенным набором решающих правил, тем самым повышается помехоустойчивость.Consequently, information loss is reduced in

Thus, when receiving five repetitions of a message, the device implements an extended set of decision rules. At the same time, accounting for the “erase” signal Θ allows you to correct a certain proportion of errors in the repeat using the most reliable previous characters, which reduces the total number of errors in the received message. This facilitates error correction with an expanded set of decision rules, thereby improving noise immunity.

Claims (1)

 An error correction device with an expanded set of decision rules and taking into account the erase signal, which contains a decision block whose outputs are the device outputs, four switches whose outputs are connected to the information inputs of the shift registers of the same name, a synchronizer, whose clock input is the device’s clock input, the first and third outputs synchronizer connected respectively to the combined first control inputs of the first switch and the first shift register, the combined first control the moves of the second switch and the second shift register, combined by the first control inputs of the third switch, the third shift register, the decision block, the second control inputs of the first and second switches, the first and second shift registers, while the first information input of the decision block is combined with the first information inputs of the switches, the second information inputs of which are simultaneously connected with the corresponding inputs of the decision block and the outputs of the shift registers, the installation inputs of which are combined with the installation inputs of the device and the installation input of the synchronizer, the fourth output of which is respectively connected to the combined third control inputs of the second switch, the second shift register, the second control inputs of the third switch, the third shift register, the decision block and the first control inputs of the fourth switch and the fourth shift register, the fifth synchronizer output is simultaneously connected to the second control inputs of the fourth switch and the fourth the shift register, the third control inputs of the third, first switches, the third, first shift registers, the decision block and the fourth control inputs of the second switch and the second shift register, characterized in that an erasure correction unit and a quality detector are introduced into it, the first and second outputs of which are connected respectively, with the first and second inputs of the erasure correction unit, the output of which is combined with the first information inputs of the switches and the deciding unit, the third and sixth inputs of the correction unit with tyrannies are connected respectively to the outputs of the first to fourth registers, the seventh, ninth, eleventh inputs of the erasure correction unit are respectively connected to the first, third, fifth outputs of the synchronizer, and the eighth, tenth inputs of the erasure correction unit are connected to the second and fourth outputs of the synchronizer and the corresponding control inputs of the first switch and first register, the input of the quality detector is the information input of the device.

Images