RU2803318C1 - Synchronization device based on matrix processing of recurrent sequence - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: devices for synchronizing a receiver with a transmitter using received code signals intended for transmitting digital information. The technical result is achieved through the use of a matrix processing mechanism with the selection of a test segment on a recurrent sequence, which makes it possible to detect errors in all cells of the shift register in one clock cycle of the reception frequency. For this purpose, the synchronization device additionally contains the first and second single-channel delay lines of k - 1 bit (symbol), a counter with a threshold for m consecutive incoming logical 1, the first and second accompanying matrices.

EFFECT: increasing the probability of correct synchronization when the quality of the communication channel decreases, simultaneously with low probabilities of false synchronization and missing an initialization vector.

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Description

Technical field

The invention relates to radio engineering, namely to devices for synchronizing a receiver with a transmitter using received code signals and is intended for transmitting digital information.

In the field of digital information transmission, there is a problem associated with the operation of cyclic synchronization devices (cyclic phasing) of the receiver and transmitter with a high probability of missing a synchronization signal (sync message) when the quality of the communication channel decreases, namely, when the probability of errors in the communication channel increases [Kognovitsky O.S. . Theory, methods and algorithms for solving problems in telecommunications based on a dual basis and recurrent sequences: dis. Dr. Tech. Sciences: 05.12.13. - SPbSUT, 2011. - 427 p. , pp. 253-256].

The receiver frame synchronization process can be represented as the following complete group of events:

,

Where - probability of correct synchronization;

- probability of correct allocation of the test segment (ZOT);

- probability of lack of synchronization;

- the probability of incorrect synchronization using a synchronization signal with errors.

Taking into account the peculiarities of the search for a recurrent sequence (RP) with a solution based on a “sliding” CTS, it is possible to reduce the probability of incorrect synchronization using a synchronizing signal with errors by increasing the length of the reference segment. In this case, the probability of incorrect synchronization is determined by the expression [Skvortsov V.S. On the issue of calculating the probability of non-reception of recurrent phase start signals // Collection of scientific papers 16 Central Research Institute of the USSR Ministry of Defense, 1965. - No. 5]:

,

Where - number of weight codewords (code spectrum);

- length of synchronization message;

- code base;

- length of the ZOT (error-free part)

- the threshold value of the coincidence counter of the TSA allocation scheme.

- size of the RP generator (number of registers);

- probability of error in a binary symmetric channel without memory.

is determined by the following expression [Zyuko A.G., Klovsky D.D., Korzhik V.I., Nazarov M.V. Theory of electrical communication //Ed. Klovsky D.D. - M.: Radio and Communications, 1998. - 432 pp.]:

Where - the largest integer not exceeding .

State of the art

The invention “Device for synchronizing a recurrent sequence with an error correction function” is known under patent RU No. 2486682, H04L 7/02, H04W 8/20, published on June 27, 2013, containing a connected first key, a comparison unit, a second key, a decoder, and two single-channel delay lines (OLZ) by one bit, the input signal is applied to the input of the first key. The disadvantage of this analogue is the relatively high probability of missing a synchronization message when the quality of the communication channel decreases.

The invention is known: “Synchronization device based on the combined use of the dual basis of the field GF(2 ^k ) and the selection of a “sliding window” with errors” according to patent RU No. 2580806, H04W 8/20, published 04/10/2016, connected to the output of the communication channel and containing connected first OLZ for one bit, first key, second OLZ for one bit, second key, decoder, comparison block. The disadvantage of this analogue is the structural complexity and the high probability of missing a synchronization message when the quality of the communication channel decreases.

The closest to the invention is the “Recurrent sequence synchronization device with the function of separating reference pulses in a sliding window” according to patent RU No. 2553089, H04L 7/02, published 06/10/2015, containing a connected first single-channel delay line for one bit, a first key, a comparison block , second key, second single-channel delay line for one bit, decoder.

The operating principle of the prototype device is as follows. The formation of a local RP based on the received one is carried out by passing the RP from the communication channel through the first key in the LRR with feedback, where the local RP is formed, which then enters the comparison block. At the same time, the other input of the comparison block receives RP from the communication channel. In the comparison block, the received and local RP are compared, if they coincide, zeros are output to the counter “0” for c coincidences and after the matches in the comparison block, the signal of the counter “0” for c coincidences, closing the third switch, turns on the controlled inverter, which is a modulo 2 adder, one input of which receives input signal pulses, and the other receives the result of the addition in the comparison block of the input signal pulse and the pulse in the feedback circuit of a linear recurrent register (LRR) with feedback connections. The flow of pulses from the comparison block through the third key enters the memory device at ( m - c ), the counter at each clock cycle calculates the number of logical “1s” in the memory device (memory) at ( m - c ) and the resulting number is transmitted to the comparison circuit, which compares it with the number contained in the memory for selecting the number of errors to be corrected. If the number of errors in the “sliding window” (test segment), corresponding to the value at the counter output, turns out to be less than the threshold, the comparison circuit generates a signal that, through the fourth key, is fed to the control inputs of the first and second keys, disconnecting the LRR with feedback from the communication channel and turning it into offline mode, in addition, this signal is supplied to the second control input of the third key, opening the connection between the input of the controlled inverter and the comparison unit, the same signal resets the counter “0” to c coincidences. In this case, the fourth key is closed by a control signal generated by the counter “0” for c matches, delayed in the LZ by ( m - c ) bits. The same control signal from the output of the LZ on ( m - c ) bits arrives at the input of the LZ on 2 ( m - c ), which determines the maximum length of the RP analysis band at which the test pulses are allocated in the “sliding window”. Appearing at the output of the LZ at 2( m - c ), the control signal resets the counter “0” to c coincidences and turns off the third switch, opening the connection between the input of the controlled inverter and the comparison unit. When the signal decoder selects the desired combination in the LRR with feedback, a command is generated at its output that opens the fourth switch. Provided that up to this point the comparison circuit has isolated the signal that transfers the LRR with feedback to the offline mode, a decision is made about the successful completion of the synchronization process.

A significant disadvantage of the prototype device, despite the low probability of false phasing, is the relatively high probability of missing a synchronization message on a communication channel with noise due to the need to use a relatively long reference segment and the lack of a mechanism that ensures a complete search of reference segments.

A technical problem is the high probability of missing a synchronization message on a communication channel with noise due to the fact that existing frame synchronization devices use long test segments in the absence of a mechanism for completely enumerating test segments at reception.

The technical result is to increase the probability of correct synchronization (reducing the probability of missing a synchronization message) by reducing the length of the test segment and using a mechanism that ensures a more complete search of test segments.

The technical problem is solved by introducing two OLZs of k - 1 bits (symbol), two accompanying matrices, a counter with a threshold for m consecutive incoming logical “1s”, connecting the output of the second key with the input of the first OLZ and the input of the decoder, the output of the decoder with the first control the input of the second key and the control input of the first key, the input of the first accompanying matrix with the output of the first OLZ, the output of the first accompanying matrix with the information input of the second key and the first information input of the comparison block, the input of the second accompanying matrix with the output of the first accompanying matrix, the output of the second accompanying matrix with the second OLZ, the output of the second OLZ with the second information input of the comparison block, the counter input with a threshold for m consecutive incoming logical “1s” with the output of the comparison block, the counter output with a threshold for m consecutive incoming logical “1s” with the control input of the first key and the second control input second key.

Disclosure of the Invention

The objective of the invention is to create a synchronization device based on matrix processing of a recurrent sequence, expanding the possibility of using communication channels with a relatively high probability of errors, while maintaining synchronization accuracy, protection against false synchronization and missed synchronization messages.

This problem is solved by the fact that “A recurrent sequence synchronization device with a function for isolating test pulses in a sliding window” containing connected the first key, the first OLZ for 1 bit (symbol), the second key, a comparison block, the second OLZ for 1 bit (symbol) and the decoder is supplemented with the first OLZ for k - 1 bit (symbol), which together with the first OLZ for 1 bit (symbol) constitutes the first OLZ, the second OLZ for k - 1 bit (symbol), which together with the second OLZ for 1 bit (symbol) make up the second OLZ, the first and second accompanying matrices, a counter with a threshold for m consecutive incoming logical “1s”. In this case, connections are made between the output of the second key and the input of the first OLZ and the input of the decoder, the output of the decoder with the first control input of the second key and the control input of the first key, the input of the first accompanying matrix with the output of the first OLZ, the output of the first accompanying matrix with the information input of the second key and the first information the input of the comparison block, the input of the second accompanying matrix with the output of the first accompanying matrix, the output of the second accompanying matrix from the second OLZ, the output of the second ULZ with the second information input of the comparison block, the input of a counter with a threshold for m consecutive incoming logical “1” with the output of the comparison block, the output a counter with a threshold for m consecutive incoming logical “1s” with the control input of the first key and the second control input of the second key.

The first switch is a two-input bidirectional switch, made on p -type MOS transistors, controlled by signals arriving at the input C of the switch ( ¹ Digital and analogue integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova and others; Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1990. - 496 pp.: ill.) (IC type: 564KT3).

The first and second delay lines of 1 bit are made on a universal shift register with serial input with serial or parallel writing and serial or parallel reading output, the first bit of which is a JK flip-flop, and the remaining bits are built on D flip-flops equal to the transit time of 1 bit s synchronous frequency ¹ (IC type: 564ИР9).

The first and second delay lines of k -1 bits are made on a universal shift register with serial input with serial or parallel writing and serial or parallel reading output, the first bit of which is a JK flip-flop, and the remaining bits are built on D flip-flops, equal to the transit time k -1 bit with synchronous frequency ¹ (IC type: 564ИР9).

The second key is k two-input bidirectional switches, made on p -type MOS transistors, controlled by signals arriving at input C ¹ (IC type: 564KT3).

The signal decoder consists of logical two-input elements that implement the "OR-NOT" function (IC type 564LE5), logical two-input elements that implement the "AND-NOT" function (IC type 564LA7) and a two-stage synchronous D -trigger ¹ (IC type 564TM2).

A counter with a threshold for m consecutive incoming logical "1" is a logical two-input elements that implement the function "OR-NOT" ¹ (IC type 564LE5), logical two-input elements that implement the function "AND-NOT" ¹ (IC type 564LA7) and a four-bit binary counter ¹ (IC type 564IE10).

The first and second accompanying matrices are sets of two-input mod 2 ¹ addition circuits (type 564LP2) in accordance with a given characteristic polynomial.

The comparison block consists of k two-input addition circuits mod 2 ¹ (type 564LP2) and two-input logical elements that implement the "OR-NOT" function ¹ (type IC 564LE5).

The listed new set of essential features ensures a reduction in the probability of missing a synchronization message on communication channels with interference and, as a consequence, an increase in the probability of correct synchronization due to a significant reduction in the length of the test segment and the use of a mechanism that ensures a more complete search of the test segments.

The analysis of the level of technology allowed us to establish that there are no analogues characterized by a set of features identical to all the features of the claimed technical solution, which indicates compliance with the patentability condition “novelty”.

The results of a search for known solutions in this and related fields of technology in order to identify features that coincide with the features of the claimed object that are distinctive from the prototype, showed that they do not follow explicitly from the prior art. The prior art also does not reveal the impact of the transformations provided for by the essential features of the claimed invention on achieving the specified technical result. Therefore, the claimed invention meets the patentability requirement of “inventive step”.

Description of drawings

The claimed device is illustrated by drawings:

fig. 1 is a block diagram of the receiving side of a synchronization device based on matrix processing of a recurrent sequence.

fig. 2 - obtained on the basis of the formula for the dependence of the probability of correct allocation of a credit segment on the value of the credit segment with a RP generator size of 5 bits and a code base of 2.

fig. 3 - obtained on the basis of the formula of the dependence of the probability of incorrect synchronization on a synchronization signal with errors on the value of the test segment with a RF generator size of 5 bits and a code base of 2.

fig. 4 - experimental dependences of the probability of correct selection of a credit segment on the value of a credit segment with a RP generator size of 5 bits and a code base of 2.

The proposed device contains: the first key (1), the first OLZ (2), the first OLZ for 1 bit (symbol) (3), the first OLZ for k - 1 bit (symbol) (4), the second key (5), decoder ( 6), a counter with a threshold for m consecutive incoming logical “1s” (7), the first accompanying matrix (8), the second accompanying matrix (9), the second LZ (10), the second LZ for 1 bit (symbol) (11), second OLZ for k - 1 bit (symbol) (12), comparison block (13). The first key (1), the first OLZ (2), consisting of the first 1 bit OLZ (symbol) (3) and the first k - 1 bit OLZ (symbol) (4), the input of which is connected, are connected in series to the output of the communication channel with the output of the second key (5) and the decoder (6), connected with its output to the first control input of the second key (5) and the control input of the first key (1), and also the first accompanying matrix (8), the input of which is connected to the output of the first single-channel delay line (2), and the output is connected to the information input of the second key (5), the first information input of the comparison block (13) and the input of the second accompanying matrix (9), the output of which is connected to the second single-channel delay line (10), consisting of the second single-channel delay line of 1 bit (11) and the introduced second single-channel delay line of k - 1 bit (12), and connected to the second information input of the comparison block (13), a counter with a threshold for m consecutive incoming logical "1" (7 ), the input of which receives a signal from the output of the comparison block (13), and the output is connected to the control input of the first key (1) and the second control input of the second key (5).

The value m of a counter with a threshold for m consecutive incoming logical “1s” is selected in accordance with the requirements for the value in conditions of interference in the communication channel, but not less than 1. In most cases, the value of m is set comparable to the size of the OLZ ( k ).

The size of the OLZ ( k ) is set equal to the size of the LRR that forms the synchronization message in transmission. The size of the LRR is selected based on the requirements for the synchronization device in the data transmission equipment, for example, the time to acquire synchronization.

The industrial application of the invention is due to the fact that it can be implemented using modern components to achieve the purpose specified in the invention.

An experimental test of the characteristics of a synchronization device based on matrix processing of a recurrent sequence was carried out on a computer in the object-oriented programming environment RStudio in the R programming language and gave a positive result. When modeling 10,000 repetitions, it was revealed that the experimental dependences of the probability of correctly selecting a scoring segment on the value of the scoring segment (Fig. 4) correspond to the theoretical ones obtained on the basis of the formula (Fig. 2). Consequently, as the offset distance decreases, the likelihood of correct synchronization increases significantly. At the same time, the probability of incorrect synchronization using a synchronization signal with errors (Fig. 3) does not have a significant impact on the probability of correct synchronization due to its smallness.

The operating principle of the proposed device is to use a shift register operating in serial-parallel mode with a matrix connected to it, which makes it possible to detect errors in a recurrent sequence in one register shift.

The technical result of significantly reducing the length of the test segment was achieved by replacing the sequential element-by-element analysis of a recurrent sequence with errors in the output register, implemented in a shift register with linear feedback according to the law of the characteristic polynomial, with parallel analysis from all register outputs of the first OLZ in one clock cycle of the proposed device .

Initially, the synchronization device operates in serial-parallel mode. The first key (1) is closed, the second (5) is open. The input signal (a combination of binary single symbols) at the current clock cycle of the synchronization device ( t ) sequentially through the first key (1) enters the first OLZ (2) and is written into its registers, then the values from k registers of the first OLZ (2) binary symbols enter the first accompanying matrix (8), where the values of the registers of the first OLZ (2) are calculated at the next operating cycle ( t + 1), which then enter the input of the comparison block (13) and the input of the second accompanying matrix (10), where the value is calculated registers of the first OLZ (2) at ( t + 2) clock cycle of the synchronization device. The values calculated in the second accompanying matrix (9) are supplied to the input of the second LZ (10), where they are stored for one clock cycle. At the next operating cycle ( t + 1), the input of the comparison block (13) will receive digital symbols from the registers of the first OLZ (2) from the output of the second OLZ (10) and the output of the first accompanying matrix (8), which will coincide if in the input there are no errors in the signal. If the input signals coincide, a logical signal “1” will appear at the output of the comparison circuit (13), supplied to the input of the counter with a threshold of m consecutively arriving logical “1s” (7), which, in the event of an accumulation of m consecutive logical “1s”, opens the first switch (1) and closes the second key (5). Thus, the device switches to a parallel-parallel operating mode, namely, digital symbols from the registers of the first OLZ (2) arrive at the first accompanying matrix (8), where the states of the registers of the first OLZ (2) are calculated at the next clock cycle, which are then calculated through the second key ( 5) are written to the corresponding registers of the first OLZ (2) and are also supplied to the input of the decoder (6). If the code combination received at the input of the decoder matches the combination of the decoder (6), a cyclic synchronization signal is released, which is the result of the device’s operation and transfers the device to its initial state (closes the first key (1) and opens the second key (5)).

By reducing the length of the test segment and implementing the function of more complete enumeration of test segments, the invention expands the possibility of using communication channels with different error rates, while maintaining synchronization accuracy, protection against false synchronization and missed synchronization messages. The graphs presented in Fig. 2 and 4, confirm the increase in the probability of correct isolation of OST ( ) with a decrease in the length of the EP and a fixed probability of error in a binary symmetrical communication channel ( p ), and the probability of incorrect synchronization using a synchronization signal with errors ( ) several orders of magnitude lower (Fig. 3).

Claims (1)

A synchronization device containing a connected first single-channel delay line (SDL) for one bit, a first key, a comparison unit, a second key, a second single-channel delay line (SDL) for one bit and a signal decoder for implementing matrix processing of a recurrent sequence, characterized in that supplemented by the introduction of two OLZs of k – 1 bits (symbol), two accompanying matrices, a counter with a threshold for m consecutive incoming logical “1s”, connection of the output of the second key with the input of the first OLZ and the input of the decoder, the output of the decoder with the first control input of the second key and the control input of the first key, the input of the first accompanying matrix with the output of the first OLZ, the output of the first accompanying matrix with the information input of the second key and the first information input of the comparison block, the input of the second accompanying matrix with the output of the first accompanying matrix, the output of the second accompanying matrix with the second OLZ, the output of the second OLZ with the second information input of the comparison block, the counter input with a threshold of m consecutive incoming logical “1s” with the output of the comparison block, the counter output with a threshold of m consecutive incoming logical “1s” with the control input of the first key and the second control input of the second key.