RU2179784C2 - Reversible pulse counter with variable modulus of counting - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: invention can find use in frequency synthesizers and digital devices of phase synchronization. Proposed pulse counter incorporates multiplexer, comparator, register, set of unit addition-subtraction, AND, NOT-OR gates. EFFECT: possibility of count reversing in pulse counter with variable modulus of counting specified by electron way. 3 cl, 4 dwg

Description

 The invention relates to computer technology and can be used in frequency synthesizers and digital phase synchronization devices.

 To change the direction of counting, pulse counters are used based on synchronous triggers with integrated clock inputs, and the outputs of the trigger low bits of the counter are connected to the inputs of the triggers in adjacent lower bits through the combination logic blocks [1]. The direction of the count in such devices is set by the voltage of one or another logical level supplied to the control inputs of the switches. A disadvantage of the known reversible counters is the rigidity of their structure, which excludes the possibility of electronic regulation of the account module.

 There are also known pulse counters with an arbitrary counting module, also consisting of synchronous triggers with controlled combination blocks between them, the total number of states of which, i.e. counting module, may change upon receipt of a control signal [2]. The disadvantage of such devices is the limited set of values of the account module, as well as the impossibility of changing the direction of the account.

 Of the known analogues, the closest in technical essence to the present invention is the well-known accumulating adder [3], operating in the mode of addition-subtraction of one. The prototype device consists of a register input connected to the terminal of the input pulses and a parallel adder. If the input number of the adder is one, and the adder itself works with numbers in the additional code, then it performs the functions of a unit of adding and subtracting units. To control the direction of the account, it is enough to provide the device with a control input connected to the clamp of the signal of the direction of account. The disadvantage of the prototype device is the impossibility of electronic adjustment of the account module.

 An object of the present invention is to enable counting reversal in a pulse counter with a variable electronically controlled counting module. Such a device is necessary, in particular, for frequency synthesis and digital phase synchronization by the method of controlled phase selection of a multiphase reference oscillator (see, for example, [4]).

 This goal is achieved by introducing into the accumulating adder on the basis of the register and the add-subtract unit connected to the terminal input pulse by the clock input the unit connected by the control input to the terminal signal of the counting direction of the additional units: comparator, multiplexer, conjunctors block, OR element, and I. These blocks are responsible for the transition of the device from state (M-1) to state 0 in the pulse summation mode and for the transition from state 0 to state (M-1) in the pulse subtraction mode, where - the value specified by the module from the outside account.

 To do this, the multi-bit output of the unit add-subtract unit is connected to the first multi-bit input of the comparator and through the block of conjunctors, in which the second inputs are connected to the output of the comparator, to the multi-bit input of the register. The multi-bit register output is connected simultaneously with the group of the first inputs of the multiplexer and with the group of inputs of the OR-NOT element. The group of second inputs of the multiplexer and the second multi-bit input of the comparator are connected to the group of terminals of the digital code of the counting module, and the output of the OR-NOT element through the AND element is connected to the address input of the multiplexer. The remaining input of the And element is connected to the clamp of the counting direction signal, and the multi-bit input of the unit add-subtract unit is connected to the group of outputs of the multiplexer.

 The unit add-subtract unit in the preferred embodiment consists of bit logic circuits. The first inputs of the bit logic circuits form a multi-bit input, the first outputs form a multi-bit output, and the combined control inputs form the control input of the unit for adding and subtracting units. In this case, the second output of each bit logic circuit is connected to the second input of the adjacent senior bit logic circuit, and the second input of the lower bit logic circuit is connected to the logical unit bus.

 Each bit logic circuit, depending on the control signal, can operate as a half-adder or as a semi-subtractor. It consists of two EXCLUSIVE OR elements and an AND element, with the combined first inputs of both EXCLUSIVE OR elements serving as the first input of the bit logic circuit, and the combined second inputs of the first EXCLUSIVE OR element and the AND element as the second input of the bit logic circuit. The second input of the second element EXCLUSIVE OR serves as the control input of the bit logic circuit. The output of the first EXCLUSIVE OR element is the first output, and the output of the AND element, in which the remaining input is connected to the output of the second EXCLUSIVE OR element, is the second output of the bit logic circuit.

 The comparator can be constructed as a group of EXCLUSIVE OR elements, the inputs of each of which are the inputs of the first and second compared numbers of the corresponding digits, and the outputs are connected to the corresponding inputs of the output element OR NOT.

 FIG. 1 is an electrical functional diagram of a reversible pulse counter with a variable counting module according to the present invention.

 FIG. 2 is a diagram of a preferred embodiment of a unit for adding / subtracting a unit included in a reverse pulse counter with a variable counting module (FIG. 1).

 FIG. 3 - a variant of constructing a bit logic circuit as part of the unit add-subtract unit shown in figure 2.

 FIG. 4 is a functional diagram of a comparator included in the structure of a reversible pulse counter with a variable counting module (Fig. 1).

 The functional diagram of a reversible pulse counter with a variable counting module shown in Fig. 1 consists of a register 2 connected to a clock input to a terminal of an input pulse 1 and a unit 3 add-subtract unit connected by a control input to the terminal 4 of the count direction signal. In addition, the circuit includes a comparator 5, block 6 conjunctors, element 7 OR NOT, element 8 AND and multiplexer 9.

 The multi-bit output of unit 3 of adding / subtracting unit is connected to the first multi-bit input of the comparator 5 and through the block 6 of conjunctors, in which the second inputs are connected to the output of the comparator 5, to the multi-bit input of the register 2. The multi-bit output of the register 2 is connected simultaneously with the group of the first inputs of the multiplexer 9 and with a group of inputs of an element of type 7 OR-NOT. The group of the second inputs of the multiplexer 9 and the second multi-bit input of the comparator 5 are connected to the terminal group 10 of the digital code of the counting module, and the output of the element 7 is OR NOT connected through the element 8 AND is connected to the address input of the multiplexer 9. The remaining input of the element 8 AND is connected to the terminal 4 of the direction signal accounts, and the multi-bit input of unit 3 of adding-subtracting unit is connected to the group of outputs of multiplexer 9.

 Unit add-subtract unit, the preferred circuit of which is presented in figure 2, consists of identical bit logic circuits 11 ... 14. The first inputs of the bit logic circuits form a multi-bit input 15, the first outputs - a multi-bit output 16, and the combined control inputs - the control input 17 of the unit add-subtract unit. The second output of each bit logic circuit is connected to the second input of the adjacent senior bit logic circuit, and the second input of the lower bit logic circuit is connected to the logical unit bus.

 Each bit logic circuit 11 ... 14 is a universal half-adder-half-subtractor. The structures of a half adder and a half subtractor are synthesized formally and are well known [5]. The bit logic circuit shown in Fig. 3 is obtained by a combination of the above blocks and consists of two elements 18, 19 EXCLUSIVE OR and element 20 I. The combined first inputs of both elements 18 and 19 EXCLUSIVE OR serve as the first input of the bit logic circuit, and the combined second inputs of the first element 18 EXCLUSIVE OR and element 20 AND - by the second input of the bit logic circuit. The second input of the second element 19 EXCLUSIVE OR serves as the control input of the bit logic circuit. The output of the first element 18 EXCLUSIVE OR is the first output, and the output of the element 20 AND, in which the remaining input is connected to the output of the second element 19 EXCLUSIVE OR, is the second output of the bit logic circuit 11 ... 14.

 The comparator circuit shown in FIG. 4, contains a group of elements 21.. . 24 EXCLUSIVE OR, the inputs of each of which are the inputs of the first and second compared numbers of the corresponding digits, and the outputs are connected to the corresponding inputs of the element 25 OR NOT. The first inputs of all elements 21.. . 24 EXCLUSIVE OR serve as the first multi-bit input 26, and their second inputs - the second multi-bit input 27 of the comparator 5. The output of the element 25 OR NOT is the output 28 of the comparator.

 Let us first consider the principles of operation of the main units included in the device.

 The comparator 5, the circuit of which is shown in figure 4, with the equivalence of the compared numbers at its first 26 and second 27 multi-bit inputs generates a logic zero voltage at its output 28, otherwise the level of the logical unit is held at the output 28.

, а на втором выходе (выходе элемента 20) - значение переноса с₁=ab, где а и b - значения входных одноразрядных операндов. Если управляющий сигнал на входе 17 имеет уровень логической единицы, то схема работает как полувычитатель. В данном режиме второй элемент 19 ИСКЛЮЧАЮЩЕЕ ИЛИ инвертирует логический уровень со входа 15 перед его передачей на вход элемента 20 И. За счет этого схема вырабатывает на своем первом выходе 16 значение разности, которое также равно

, а на втором выходе - значение заема, равное

.The bit logic circuit 11 (identical to the rest of the circuits 12 ... 14 - Fig. 2) shown in Fig. 3, depending on the level of the control signal at input 17, either performs the addition of two single-bit binary numbers or subtracts them without taking into account the transfer signal or loan. If the control signal is zero, then the circuit operates as a half-adder. In this case, the second element 19 EXCLUSIVE OR does not invert the logic level at input 15 before it enters the input of element 20 I. Therefore, the value of the sum is generated at the first output 16

, and at the second output (output of element 20) is the transfer value with ₁ = ab, where a and b are the values of the input single-bit operands. If the control signal at input 17 has a logic level, then the circuit operates as a semi-subtractor. In this mode, the second element 19 EXCLUSIVE OR inverts the logic level from input 15 before it is transferred to the input of element 20 I. Due to this, the circuit generates a difference value at its first output 16, which is also equal to

, and on the second output - the value of the loan, equal to

.

 The described bit logic circuits make it possible to construct a simplified structure of the unit 3 of adding / subtracting a unit in which the first operand is a multi-bit binary number and the second is a single-bit unit with one or another sign. In the circuit of FIG. 2, the bit logic circuits are connected in series along the propagation chain of the transfer-loan signal. The number to which the unit is added to or subtracted from is fed to inputs 15, i.e. to the first inputs of all bit logic circuits 11 ... 14. The second input of the bit logic circuit 11 of the least significant bit is connected to the bus of the logical unit. The control inputs of all bit logic circuits 11 ... 14 are connected to the input 17 of the control signal. If at this input 17 there is a logical "0", then the circuit adds one to the input multi-bit binary number, if the logical "1" is subtraction. The result is formed on the group of the first outputs of 16 bit logic circuits 11 ... 14.

 Reversible pulse counter with a variable counting module (figure 1) works in the following order. The counting direction is set by the logic level of the signal on terminal 4 of the counting direction signal: at zero level, the summation mode is performed, with a single level, the subtraction mode. The value of the counting module is set by a binary number M, which arrives at terminal group 10 of the digital code of the counting module.

 In the summing mode, when the logic zero level is present at terminal 4 of the counting signal, the unit 3 of adding / subtracting one adds one to the number supplied to its multi-bit input from the multi-bit output of multiplexer 9. Since the logic level is held at one of the inputs of element 8 AND "0" from terminal 4 of the counting direction signal, then a logical "0" level is also generated at its output. Therefore, the multiplexer at address "0" connects to its multi-bit output the first group of its inputs, i.e. the outputs of register 2, which are the outputs of the device in business. At the output of unit 3 of adding / subtracting unit, the following value of the output number of the device is formed, which at the time of the next input pulse to terminal 1 is written to register 2 through block 6 of conjunctors, which have a logical “1” level from the output of comparator 5 on the second combined inputs This continues until the comparator 5 fixes the equality of the addition-subtraction of the unit of the new number prepared by block 3 to the value of the account module M. Then the comparator 5 will develop a level at its output logical “0”, which causes the occurrence of zero voltage levels at all information inputs of register 2 and writing the number 0 to register 2 at the time of the arrival of the next input pulse to terminal 1. Thus, in the mode of summing input pulses, the output number of the device cyclically takes states from 0 to (M-1).

 In the mode of subtraction, the logic level “1” is present on terminal 4 of the counting direction signal, as a result of which unit 3 of adding / subtracting a unit decreases by 1 the number arriving at its multi-bit input from the output of multiplexer 9. If the output number of the device at the output of register 2 is greater than 0 , then element 7 OR NOT generates a logic level “0”, which through element 8 AND holds the address of multiplexer 9 equal to “0”. Therefore, multiplexer 9 transfers the output number of register 2 to the input of unit 3 of adding / subtracting unit and with each input impulse With ice at clamp 1, this number decreases by 1. When the output number of the device reaches zero in the process of subtraction 1, the element 7 OR NOT generates a logic level “1” at its output, and due to the coincidence of the units at the inputs of the element 8 AND the address of the multiplexer 9 changes from “0” to “1”. The multiplexer 9 connects the number M from the terminals 10 of the digital code of the counting module to the input of unit 3 of adding / subtracting a unit, therefore, at the output of unit 3 of adding / subtracting a unit, a number equal to (M-1) is formed. At the moment the next input pulse arrives at terminal 1, this number (M-1) is written to the register. Thus, in this mode, the device cyclically receives states from (M-1) to 0.

 The reversible pulse counter with a variable counting module is intended for use in the technique of frequency synthesis and digital phase synchronization with an extended frequency range.

Literature
1. Titz U., Schenk K. Semiconductor circuitry: a reference guide. - M .: Mir, 1982, p. 348, Fig. 20.7.

 2. Aleksenko A.G., Shagurin I.I. Microcircuitry. - M.: Radio and Communications, 1990, p. 222, Fig. 5.9.

 3. Ugryumov E. P. Design of computer elements and components. - M.: Higher School, 1987, p. 196, Fig. 11.14.

 4. Phase synchronization device. RF patent 2119717, bull. 1998, 27.

 5. Tokheim R. Fundamentals of Digital Electronics. - M.: Mir, 1988, p. 213, fig. 9.4, p. 219, fig. 9.9.

Claims (4)

 1. Reversible pulse counter with a variable counting module, comprising a register connected to the input pulse terminal and a unit add-subtract unit connected by a control input to the account direction signal clamp, characterized in that the multi-bit output of the unit add-subtract unit is connected to the first multi-bit the input of the comparator and through the block of conjunctors, in which the second inputs are connected to the output of the comparator, to the multi-bit input of the register, the multi-bit output of the register is connected one with the group of the first inputs of the multiplexer and the group of inputs of the OR-NOT element, while the group of the second inputs of the multiplexer and the second multi-bit input of the comparator are connected to the terminal group of the digital code of the counting module, the output of the OR-NOT element through the AND element is connected to the address input of the multiplexer, the remaining the input of the And element is connected to the clamp of the counting direction signal, the multi-bit input of the unit add-subtract unit is connected to the group of outputs of the multiplexer.  2. A reversible pulse counter with a variable counting module according to claim 1, characterized in that the unit adding and subtracting units consists of bit logic circuits, the first inputs of which form a multi-bit input, the first outputs are a multi-bit output, and the combined control inputs are the control input of the block adding-subtracting one, while the second output of each bit logic circuit is connected to the second input of the adjacent senior bit logic circuit, and the second input of the lower bit logic circuit is connected to the logical e bus dynitsy.  3. The reversible pulse counter with a variable counting module according to claim 2, characterized in that each bit logic circuit consists of two EXCLUSIVE OR elements and an AND element, the combined first inputs of both EXCLUSIVE OR elements serving as the first input of the bit logic circuit, the combined second inputs the first EXCLUSIVE OR element and the AND element are the second input of the bit logic circuit, and the second input of the second EXCLUSIVE OR element is its control input, the output of the first EXCLUSIVE OR element is the first output m, and the output of AND, whose input is connected to the remaining output of the second exclusive OR element, - a second output bit logic circuit.  4. A reversible pulse counter with a variable counting module according to claim 1, characterized in that the comparator contains a group of EXCLUSIVE OR elements, the inputs of each of which are the inputs of the first and second compared numbers of the corresponding bits, and the outputs are connected to the corresponding inputs of the output element OR NOT .

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