RU2178894C1 - Satellite radio-navigation receiver - Google Patents

Abstract

FIELD: radio navigation, in particular, satellite radio-navigation receivers of the GPS and GLONASS systems of frequency range L1. SUBSTANCE: the receiver has a radio-frequency converter, N-channel digital correlator, computer, time-mark signal generator, each channel of the digital correlator has a correlation processing module, digital carrier-frequency oscillator and a digital code oscillator. Each digital carrier-frequency and code oscillator has an adder-accumulator and a readout forming unit. Each adder-accumulator of each digital carrier-frequency and code oscillator is made in the form of radio- frequency and audio-frequency accumulating modules, it also contains a series-connected output combination adder and an output phase register. The radio-frequency accumulating module has series-connected first frequency code register, first combination adder and the first phase register, whose output is connected to the second input of the first combination adder and to the first input of the output combination adder. The audio-frequency accumulating module has series-connected second frequency code register, second combination adder and the second phase register, whose output is connected to the second input of the second combination adder, and the output of the respective most significant digit positions are connected to the second input of the output combination adder. The clock input of the output phase register and the clock input of the first phase register of the radio-frequency accumulating module make up a clock input of the accumulating adder - the clock input of the respective digital oscillator, clock input of the second phase register of the audio-frequency accumulating module make up an additional input of the digital oscillator. The information inputs of the frequency code registers of the radio-frequency and audio-frequency accumulating modules make up the control inputs of the accumulating adder. The outputs of the respective digit positions of the output phase register make up the output of the formed reference signals of the digital oscillator. The receiver also uses a driver of additional audio-frequency clock signals for the digital carrier-frequency oscillator and digital code oscillator made in the form of a frequency divider and a phase readout register coupled to it, the first and the second outputs of the audio-frequency clock signals of the frequency divider are connected respectively to the additional inputs of the digital carrier-frequency oscillator and digital code oscillator of each channel of the N-channel correlator. EFFECT: reduced power consumption. 5 dwg

Description

 The invention relates to the field of radio navigation, and in particular to consumer equipment operating on the signals of satellite radio navigation systems (SRNS) GLONASS (Russia) and GPS (USA) in the frequency range L1, which generates signals for determining the location, as well as signals of high-precision time stamps associated with SRNS timeline.

 Consumer equipment based on GLONASS [1] and GPS [2] signals is used to determine the coordinates (latitude, longitude, altitude) and speed of the object, as well as to generate signals of high-precision time stamps. Moreover, the use of signals of the frequency range L1 with code modulation with C / A codes - codes of "standard accuracy" - provides "standard" accuracy of positioning.

The main differences between GLONASS and GPS systems are the use of different, albeit adjacent frequency ranges, the use of different pseudo-random modulating codes, as well as the use, respectively, of frequency and code separation of signals from different satellites. So, in GPS in the frequency range L1, satellites emit signals modulated by various pseudo-random codes on one carrier frequency of 1575, 42 MHz, and GLONASS satellites emit signals modulated by the same pseudorandom code on different carrier (letter) frequencies lying in the adjacent frequency domain. Moreover, for the frequency range L1, the zero letter frequency is f ₀ = 1602 MHz, and the interval between the letter frequencies is Δf = 0.5625 MHz. The distribution of letter frequencies among functioning GLONASS satellites is set by an almanac transmitted in the frame of service information. Letter frequencies are entered in accordance with the “Interface Control Document” [1]. Currently, the letter frequencies "0" - "12" are used, in the future, the transition to the letter frequencies "-7" - "4" is provided.

 Despite the differences that exist between GPS and GLONASS systems, their proximity to the purpose, ballistic construction of the orbital constellation of satellites and the frequency range used allows us to design equipment operating simultaneously from the signals of these two systems. The result achieved in this case is to increase the reliability, reliability and accuracy of determining the location, in particular, due to the possibility of choosing the working constellations of satellites with the best values of geometric factors [3, p. 160].

 Known, see, for example, [3, p. 158-161, fig. 9.8], a receiver of single-channel consumer equipment operating on GPS and GLONASS signals in the frequency range L1. The receiver comprises a radio frequency converter, a reference generator, means for correlation signal processing, and means for calculations. The structure of the radio frequency converter includes a frequency splitter (“diplexer”), which carries out frequency separation of GPS and GLONASS signals, bandpass filters and low-noise amplifiers of GPS and GLONASS channels, a switch that supplies GPS or GLONASS signals to the signal input of the first mixer, a switch that connects to the reference input the first mixer signal of the first local oscillator to convert GPS or GLONASS signals. In this receiver, due to the corresponding formation of the frequency of the first local oscillator, the first intermediate frequency is constant for GPS and GLONASS signals and the entire further path of the receiver, including the second mixer and the analog-to-digital conversion unit, is implemented as common for these signals. The composition of the means for correlation signal processing includes a multiplexer with read-only memory, a digital letter frequency generator, a pseudo-random code generator and a digital correlator. The receiver implements a multiplex (alternate) mode of operation based on the signals of both GPS and GLONASS systems. The receiver does not allow parallel (multichannel) processing of GPS and GLONASS signals, which increases the time taken to obtain navigation information.

 A device is known for receiving SRNS signals [4], which solves the problem of simultaneously receiving and multi-channel (parallel) correlation processing of GPS and GLONASS signals, in particular, the frequency range L1 Functionally complete part of the device that receives and correlates processing GPS and GLONASS signals of the frequency range L1 includes a radio frequency converter, an N channel digital correlator, a calculator, and a time stamp signal generator. The clock input of the time stamp signal generator is associated with the clock output of the RF converter. The output of the measuring gates of the time stamp signal generator is associated with the corresponding inputs of each of the channels N of the channel digital correlator. The time stamp signal generator and the channels N of the channel digital correlator are connected by a data exchange bus with a computer. Each channel N of the channel digital correlator contains a correlation processing module and associated digital carrier and code generators controlled by the computer. Using the correlation processing module, a computer, and digital carriers and code generators, information contained in the received signal is extracted. Information is extracted using closed-loop digital tracking correlation processing systems, the so-called “carrier tracking circuits” and “delay tracking circuits”, during the operation of which copies of the processed signals are formed and then the correlation copies are compared with the signals themselves. At the same time, digital carrier and code generators controlled by the computer generate the necessary reference signals.

 For the purposes of digital correlation processing of signals, including SRNS signals, digital generators controlled by a computer are based on accumulating adders that implement the direct digital frequency synthesis method [5, p. 75-76, fig. 3.12; 6, p. 90-92, fig. 34]. Direct control from the calculator implemented in such generators provides the required accuracy of generating the reference signals used in “carrier tracking circuits” measuring Doppler shift or “delay tracking circuits” measuring the reference code shift relative to the processed signal code [6, p. . 87-90, fig. 33].

 Closest to the claimed receiver is a well-known receiver of SRNS signals [7], which carries out the reception and multichannel correlation processing of GPS and GLONASS signals in the frequency range L1, in which the digital correlator channels are controlled by digital generators based on the accumulating adder . The receiver signals SRNS described in [7], adopted as a prototype.

 The SRNS signal receiver, adopted as a prototype, contains a radio frequency converter, the input of which forms the signal input of the receiver, an N channel digital correlator, the clock and signal inputs of each channel of which are connected to the corresponding outputs of the radio frequency converter, a signal generator of timestamps, the clock input of which is connected to clock output (clock signal output) of the RF converter, and the output of the measuring gates with the corresponding inputs of each of the channels N to tional digital correlator. The prototype receiver also contains a calculator connected by a data bus with a signal driver of labels and channels N of the channel digital correlator.

 Each of the channels N of the channel digital correlator of the prototype receiver contains a correlation processing module, a digital carrier generator, and a digital code generator connected to the computer by the data bus. Each of these generators contains a corresponding accumulating adder and a corresponding block for generating samples connected to the computer via the data exchange bus, and connected to the data output of the accumulating adder. The outputs of the reference signals of digital generators formed by the corresponding outputs of their accumulating adders are connected to the reference inputs of the correlation processing module. The clock inputs of digital generators formed by the clock inputs of their accumulating adders and the inputs of the measuring gates formed by the inputs of the measuring gates of their sampling units are connected respectively to the clock input and the input of the measuring gates of the correlation processing module. The signal inputs, the clock input and the input of the measuring gates of the correlation processing module form the corresponding inputs of channel N of the channel digital correlator.

In the prototype receiver, the radio frequency converter comprises an input unit, a first frequency conversion unit for GPS and GLONASS signals, first and second channels for a second frequency conversion for GPS and GLONASS signals, as well as a clock and local oscillation signal generation unit. The input unit of the RF converter, which performs preliminary filtering of the GPS and GLONASS input signals, is based on a band-pass filter. The unit of the first frequency conversion of the signals of the radio frequency converter, performing the first frequency conversion of the GPS and GLONASS signals, is based on the mixer, while the mixer uses the signal of the first heterodyne frequency (F _r1 ). The first and second channels of the second signal frequency conversion, performing the second signal frequency conversion of GPS and GLONASS, respectively, are performed on the basis of bandpass filters, mixers and analog-to-digital conversion units. The mixers of the first and second channels use the signals of the second (F _r2 ) and third (F _g3 ) heterodyne frequencies, respectively. The output of the clock signal (clock frequency signal Фт) of the clock and heterodyne frequency signal generation unit together with the outputs of the second signal frequency conversion channels form the clock and signal outputs of the RF converter.

 In the prototype receiver, in each channel N of the channel digital correlator, the correlation processing module contains an input signal switcher, digital mixers, digital demodulators, a programmable delay line, a C / A reference code generator, accumulation units, and a control register. The reference inputs of digital mixers and the reference C / A code generator form the reference inputs of the module. The signal inputs of the input signal switch form the signal inputs of the module. The clock inputs of the accumulation units and the programmable delay line form the clock input of the module. The inputs of the measuring gates of the reference C / A code generator form the input of the measuring gates of the module. The outputs of the accumulation units and the inputs and outputs of the data generator of the reference C / A code and the control register, which form the inputs and outputs of the module data, are connected by a data exchange bus with the calculator.

 The prototype receiver operates as follows.

 The GPS and GLONASS signals of the frequency range L1 received by the antenna are fed to the signal input of the RF converter, where they are filtered in the bandpass filter of the input unit, converted by frequency in the mixer of the first signal frequency conversion unit, and then separated by systems (GPS and GLONASS) in the corresponding channels of the second frequency conversion signals are converted in frequency (second frequency conversion) and are subjected to analog-to-digital conversion, for example, two-bit quantization in level.

 From the output of the RF converter, the GPS and GLONASS signals are sent to the corresponding inputs of the channels N of the channel digital correlator, where they are digitally correlated. First, using the input signal switch, the signals of one of the systems — GPS or GLONASS — are selected. Then, using digital mixers, the signals of a particular satellite of the selected system are extracted and the spectrum of these signals is transferred to the main frequency band (to the zero frequency), for which reference signals generated by a digital carrier generator are used.

The reference signals generated by the digital carrier generator are codes of the current values of the phase of the reference frequency. The digital carrier generator is controlled by the signals of the calculator, in particular, the frequency code data coming from the calculator sets the discrete increment of the phase at the output of the accumulating adder. The operation of the accumulating adder is carried out with a sampling frequency determined by the clock frequency Ft. Also, in the digital carrier generator, using the sampling unit, the carrier phase reference data and the carrier cycle data (periods) are generated, which, with the frequency of the measuring gates F _, enter the computer.

 From the outputs of the digital mixers, the processed signals are fed to the signal inputs of the digital demodulators, which correlate them with the exact “P” (punctual) and differential “E-L” (Early-Late) copies of the corresponding C / A reference code (GPS or GLONASS). The indicated copies of the code are generated by a programmable delay line, which, under the control of the calculator (according to the signals generated by the control register), changes the interval between the early "E" and late "L" copies of the C / A code from 0.1 to 1 the duration of the C / A code symbol, thereby forming a “narrow discriminator” (“narrow correlator”) in the code tracking system, as described, in particular, in [8–10].

 A reference C / A code corresponding to the signal being processed is generated in each channel of the N channel digital correlator by a reference C / A code generator, which receives for this a reference clock frequency of 1.023 MHz for GPS or 0.511 MHz for GLONASS. The type of the generated pseudo-random code sequence is selected based on the data received from the calculator through the control register. The reference clock frequency of the code is generated using a digital code generator.

 The digital code generator generates the current phase values of the reference clock frequency of the C / A code (1.023 MHz for GPS, 0.511 MHz for GLONASS). The digital code generator is controlled by the signals of the calculator, in particular, the calculator receives data on the value of the clock frequency of the code, which sets the discrete increment of the phase at the output of the accumulating adder. The operation of the accumulating adder is carried out with a sampling frequency determined by the clock frequency Ft. Also, in the digital code generator, using its sampling unit, the data of the fractions of the code symbol are generated, which with the frequency of the measuring gates F and enter the computer.

 Measuring strobes (signals of the receiver’s own timestamps) are generated in the driver of the timestamp signals under the action of a clock signal coming from the output of the clock and heterodyne frequencies of the RF converter, in accordance with the control signals coming from the calculator, and also, if necessary, under action of external synchronizing signals. In accordance with the measuring gates in the receiver prototype, internal synchronization of the processes of correlation processing and navigation measurements is carried out, in particular, the quasidality, phase of the carrier and the number of cycles of the carrier are counted.

 Correlation comparison results are accumulated in the corresponding accumulation units. The accumulation period is equal to the period of the C / A code, i.e. 1 ms. The accumulated data is periodically read by a calculator, in which all signal processing algorithms are implemented, i.e., signal search algorithms, carrier and code tracking, and service information processing.

 As noted above, in the prototype receiver, the digital generators of the carrier and code are based on an accumulating adder that implements the direct digital frequency synthesis method with accumulation of the current phase. The power consumption characteristics of the accumulating adder of the traditional structure depend on the sampling frequency, the value of which in the prototype receiver is determined by the clock frequency (Ft≈22 MHz), selected on the basis of the spectrum of the processed signals, and also on the bit depth, determined on the basis of the required frequency setting discrete (phase increment) . In practice, in the prototype receiver, to implement the tasks of correlation signal processing, digital generators of the carrier and code should have a high-frequency (approximately 20 MHz) and simultaneously high-bit (tens of bits) accumulating adder. However, digital carrier and code generators using such high-frequency and at the same time high-discharge accumulative combiners consume increased power, which can be a problem, in particular, for portable multi-channel SRNS signal receivers intended for operation from stand-alone battery power.

 The technical problem to be solved by the claimed invention is directed is to reduce the power consumption of the receiver of the SRNS signals. The problem is solved by a new implementation of digital carrier and code generators, namely, by switching to two-frequency digital generators synthesizing their output signals from two components - high-frequency and low-frequency, while high-frequency components are synthesized with a sampling frequency determined by the main clock frequency Ft, and low-frequency - with sampling frequencies determined additionally by low-frequency clock signals generated in the receiver.

 The essence of the invention lies in the fact that the signal receiver of satellite navigation systems containing a radio frequency converter, the input of which forms the signal input of the receiver, N channel digital correlator, the signal and clock inputs of each channel of which are connected to the corresponding outputs of the radio frequency converter, calculator, and also the shaper timestamp signals, the control input of which is connected by the data exchange bus with the computer, the clock input - with the clock output of the radio frequency transducer, and the output of the measuring gates with the inputs of the measuring gates of each channel N of the channel digital correlator, each channel N of the channel digital correlator contains a correlation processing module, a digital carrier generator, and a digital code generator connected to the computer via a data bus, and each of these digital generators contains an accumulating adder and a sample forming unit, the information input of which is connected to the output of data of the accumulating adder, wherein the outputs of the reference signals of these digital generators, formed by the corresponding outputs of their accumulating adders, are connected to the reference inputs of the correlation processing module, the clock inputs of these digital generators, formed by the clock inputs of their accumulating adders, and the inputs of the measuring gates formed by the inputs of the measuring gates their sampling units are connected, respectively, to the clock input and the input of the measuring gates of the correlation module of processing, the clock input, the input of the measuring gates and the signal inputs of which form the corresponding inputs of the channel N of the channel digital correlator, in contrast to the prototype, an additional low-frequency clock signal generator for the digital carrier generator and digital code generator is implemented, made in the form of a frequency divider and associated phase reference register, and the clock input of the frequency divider is connected to the clock output of the RF converter, the input of the measuring gates of the reference register The basics are connected to the output of the measuring gates of the timestamp signal generator, the output of the phase reference register is connected by a data exchange bus with the calculator, and the first and second outputs of the low-frequency clock signals of the frequency divider are connected respectively to the additional inputs of the digital carrier generator and digital code generator of each channel N of the channel correlator , while in each of these digital generators, the accumulating adder is made in the form of high-frequency and low-frequency storage modules, and t also contains a series-connected output combiner and an output phase register, and the high-frequency storage module contains serially connected a first frequency code register, a first combiner and a first phase register, the output of which is connected to the second input of the first combiner and to the first input of the output combiner, low-frequency the storage module contains in series a second frequency code register, a second combiner and a second phase register, the output of which is connected to the second input of the second Raman adder, and the output of the corresponding high order bits - to the second input of the output Raman adder, the clock input of the output phase register and the clock input of the first phase register of the high-frequency storage module connected to it form the clock input of the accumulating adder - the clock input of the digital generator, the clock input of the second phase register of the low-frequency storage module forms an additional input of the digital generator, in the formation inputs of the first and second registers of the frequency code of the high-frequency and low-frequency storage modules form respectively the first and second control inputs of the accumulating adder connected by the data exchange bus with the computer, the outputs of the bits of the output phase register and the outputs of the corresponding lower-order bits of the second phase register of the low-frequency storage module form the data output of the accumulating the adder connected through the block of formation of readings with the calculator, and the outputs of the corresponding bits in the output phase register form the output of the reference signals of a digital generator connected to the corresponding reference input of the correlation processing module of channel N of the channel digital correlator.

The essence of the claimed invention, the possibility of its implementation and industrial application are illustrated by the drawings shown in FIG. 1-5, where:
in FIG. 1 presents a structural diagram of the inventive receiver of the SRNS signals in the considered example of implementation;
in FIG. 2 presents a generalized structural diagram of digital carrier generators and the code of the inventive receiver of the SRNS signals in this example implementation;
in FIG. 3 is a structural diagram of one channel N of a channel digital correlator of the inventive SRNS signal receiver in the present implementation example, illustrating the implementation of the correlation processing module;
in FIG. 4 presents a structural diagram of a radio frequency converter of the inventive receiver of signals of the SRNS in this example implementation;
in FIG. 5 are graphs explaining the principle of operation of dual-frequency digital carrier and code generators in the inventive SRNS signal receiver.

The inventive SRNS signal receiver in this example implementation contains, see FIG. 1-4, the RF converter 1, the input of which forms the signal input of the receiver, N channel digital correlator 2, containing N channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ), the signal and clock inputs of which are connected to the corresponding outputs of the radio frequency converter 1, calculator 4, connected by a data exchange bus with each of N channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ), as well as a time stamp signal generator 5, the control input of which is connected by a data exchange bus with calculator 4, the clock input is connected to the clock output (the output of the clock signal FT) adiochastotnogo converter 1 and the output of measuring strobes (fA) - with the measuring inputs of gates of each of the N channels 3 (3 _1, 3 _2, 3 _N...) of the digital correlator 2.

Each of the N channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of the digital correlator 2 contains a correlation processing module 6, a digital carrier generator 7, and a digital code generator 8 connected to the computer 4 via the communication bus. The output of the reference signals of a digital generator carrier 7 and the reference signal output of the digital code 8 generator is connected to the corresponding reference inputs of module 6. The clock inputs of the digital generators 7 and 8 are connected to the clock input of the module 6. The inputs of the measuring gates of the generators 7 and 8 are connected to the input of the measuring gates of the module 6. The signal inputs of module 6, as well as its clock input and the input of the measuring gates form the corresponding inputs of channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of digital correlator 2.

The inventive signal receiver SRNS contains a shaper 9 additional low-frequency clock signals for a digital generator carrier 7 and a digital code generator 8. Shaper 9 contains a frequency divider 10 and the associated register 11 of the phase reference. The clock input of the frequency divider 10 is connected to the clock output (the output of the clock signal FT) of the RF converter 1. The input of the measuring gates of register 11 is connected to the output of the measuring gates (F) of the driver 5 of the timestamp signals. The output of register 11 is connected by a data exchange bus with a calculator 4. The outputs of the first (F1) and second (F2) additional low-frequency clock signals of the frequency divider 10 are connected to additional inputs of a digital carrier generator 7 and a digital code generator 8 of each channel 3 (3 ₁ , 3 ₂ ,..., 3 _N ) digital correlator 2.

 The digital carrier generator 7 and the digital code generator 8 in a generalized form (FIG. 2) comprise an accumulating adder 12 and a sample generation unit 13. The accumulating adder 12 and the sampling unit 13 are connected by a data exchange bus with the calculator 4, the information input of the sampling unit 13 is connected to the data output of the accumulating adder 12.

 The outputs of the generated reference signals of the digital carrier generator 7 and the digital code generator 8 are formed by the corresponding outputs of their accumulating adders 12. These outputs are connected to the corresponding reference inputs of the module 6. The clock inputs of the digital generators 7 and 8 are formed by the clock inputs of their accumulating adders 12. These inputs are connected to the clock input of module 6. The inputs of the measuring gates of digital generators 7 and 8 are formed by the inputs of the measuring gates of their blocks 13 of the formation of samples. These inputs are connected to the input of the measuring gates of module 6.

 The accumulating adder 12 of each of the generators 7 and 8 is made in the form of a high-frequency 14 and a low-frequency 15 storage modules, and also contains a series-connected output combiner 16 and an output phase register 17. High-frequency 14 and a low-frequency 15 memory modules are made according to the known scheme of a digital synthesizer that implements direct digital frequency synthesis method, see, for example, [5, p. 50-51, fig. 2.13].

 In each of the generators 7 and 8, the high-frequency storage module 14 contains in series the first register of the frequency code 18, the first combiner 19 and the first phase 20 register, the output of which is connected to the second input of the first combiner adder 19 and to the first input of the output combiner 16. Low-frequency the storage module 15 contains series-connected the second register of the frequency code 21, the second combiner adder 22 and the second register of phase 23, the output of which is connected to the second input of the second about the combiner adder 22, and the output of the corresponding high order bits to the second input of the output combiner 16. The clock input of the output register of phase 17 and the clock input of the first register of phase 20 of the high-frequency storage module 14 form the clock input of the accumulator adder 12 - the clock input of the corresponding digital generator 7, 8. The clock input of the second register of phase 23 of the low-frequency storage module 15 forms an additional input of the corresponding digital generator 7, 8. Information the input inputs of the first 18 and second 21 registers of the frequency code of the high-frequency 14 and low-frequency 15 storage modules form the first and second control inputs of the accumulating adder 12, respectively, connected by a data bus with the calculator 4. The outputs of the bits of the output register of phase 17 and the outputs of the corresponding least significant bits of the second phase register 23 of the low-frequency storage module 15 form the data output of the accumulating adder 12, connected to the information input of the block 13 of the formation of samples, the output of which through the data exchange bus is connected to the calculator 4. The outputs of the corresponding bits of the output register of phase 17 form in each of the digital generators 7, 8 the output of the generated reference signals.

 In digital generators 7 and 8, a high-frequency clock signal of frequency FТ is supplied to the clock input of the first register of phase 20 of the high-frequency storage module 14, as well as to the clock input of the output register of phase 17. The low-frequency clock signal is supplied to the clock input of the second register of phase 23 of the low-frequency storage module 15, namely, in the generator 7, a low-frequency clock signal of frequency F1, and in the generator 8, a low-frequency clock signal of frequency F2. The high-frequency FT and low-frequency F1, F2 clock signals are synchronous, which is ensured by the formation of low-frequency clock signals F1 and F2 from the clock signal FT by dividing the frequency FT in the frequency divider 10 of the former 9.

 In practical schemes, combinational combiners 16, 19, 22 can be made according to a combinational combiner with sequential transfer described in, for example, [11, p. 523-536, fig. 6.96, 6.97], which is preferable from the point of view of reducing power consumption, or according to the combination combiner with parallel transfer, described, for example, in [11, p. 523-536, fig. 6.100]. Registers 17, 18, 20, 21, 23 can be made in the form of memory registers based on triggers (for example, D-flip-flops) that provide recording, storage and reading of data in parallel binary code, see, for example, [11, p. 348-354, fig. 5.85]. Also in practical circuits, the frequency code registers 18 and 21, in addition to the indicated information inputs, have recording inputs (not shown in FIG. 2), by which the input data are written to these registers. Also in practical circuits, the registers 17, 18, 20, 21, 23 can have zeroing inputs (not shown in Fig. 2), to which at the initial moment of operation a zeroing signal can be set, which sets the registers to the initial (zero) state.

With the coincidence of their generalized structural diagram (Fig. 2), the digital generators of the carrier 7 and code 8 are distinguished by the specific execution of the blocks 13 for the formation of samples, the bits of high-frequency 14 and low-frequency 15 storage modules, as well as the specific values of the additional clock frequencies F1 and F2 used by low-frequency memory modules 15. So, in the digital carrier generator 7, the block 13 of the formation of samples contains a register that generates, in accordance with the measuring gates, the data of the sample phase carrier taken from Exit accumulator 12, and also comprises a series connected loop counter and register that forms in accordance with the measurement data strobes count the number of cycles (periods) of the carrier. See, e.g., [7, FIG. 5, elements 41, 42, 44]. In the digital code generator 8, the block 13 of the formation of samples contains a register that generates, in accordance with the measuring gates, the sample data of fractions of the code symbol, see, for example, [7, FIG. 5, element 45]. In the digital carrier generator 7, the elements of the high-frequency storage module 14 (the first register of the frequency code 18, the first combiner 19, the first register of phase 20), the output combiner 16 and the output register of phase 17 are made K ₁ bit, and the elements of the low-frequency storage module 15 (second frequency code register 21, second combination adder 22, second phase 23 register) are made K ₂ bit, where K ₂ > K ₁ , for example K ₂ = 25, K ₁ = 5. In the digital code generator 8, similar elements of the high-frequency storage module 14, as well as the output combiner 16 and the output register of phase 17 are made K ₃ bit, and the elements of the low-frequency storage module 15 are made K ₄ bit, where K ₄ > K ₃ , for example, K ₄ = 23, K ₃ = 2. Low-frequency operation the storage module 15 of the digital carrier oscillator 7 is carried out with a sampling frequency determined by the first additional low-frequency clock signal F1. This signal is generated by the shaper 9 of additional low-frequency clock signals by dividing the main clock frequency FT by a factor k ₁ , for example, k ₁ = 10. The low-frequency storage module 15 of the digital code generator 8 operates at a frequency determined by the second additional low-frequency clock signal F2. This signal is generated by the shaper 9 by dividing the main clock frequency FТ by a factor k ₂ , for example, k ₂ = 20. In almost the case under consideration, the second additional clock frequency F2 can be formed from the first F1 by dividing it by two.

In the inventive SRNS signal receiver, the correlation processing module 6 of each of the channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of the digital correlator 2 can be implemented in accordance with the known one, see, for example, [7, FIG. 4], a structural diagram. In accordance with this scheme, the correlation processing module 6 in this example implementation contains (Fig. 3) an input signal switch 24, accumulation units 25, 26, 27 and 28, a control register 29, a generator 30 of the reference C / A code (GPS and GLONASS) , programmable delay line 31, digital mixers 32 and 33, respectively, in-phase and quadrature channels of correlation processing, digital demodulators 34, 35, 36, 37. The outputs of the accumulated data of blocks 25-28 accumulation, the inputs and outputs of the data register 29 of the control and generator 30 reference C / A code linked by by means of a data bus with a calculator 4. The first ("GPS") and second ("GLONASS") signal inputs of the switch 24, which form the signal inputs of module 6 (signal inputs of channel 3), are connected to the corresponding signal outputs of the RF converter 1. Clock inputs of the blocks 25-28 accumulation and programmable delay line 31, forming the clock input of module 6 (clock input of channel 3), are connected to the clock output of the RF Converter 1. The inputs of the measuring gates of the generator 30 reference C / A code, forming the input of the measuring the gates of module 6 (input of the measuring gates of channel 3) are connected to the output of the measuring gates of the shaper 5 of the timestamp signals. The control input of the switch 24 is connected to the first output of the control register 29. The second and third outputs of the control register 29 are connected respectively to the control input of the programmable delay line 31 and the first control input of the generator 30 of the reference C / A code. The output of the switch 24 is connected to the first inputs of the digital mixers 32 and 33, the second inputs of which, forming the first reference input of the module 6, are connected to the output of the reference signals of the digital generator 7. The outputs of the digital mixers 32 and 33 are connected to the first inputs of the digital demodulators 34, 35 and 36, 37, respectively. The second inputs of the digital demodulators 34, 37 and 35, 36 are connected to the corresponding outputs of the programmable delay line 31 - outputs exact "P" (Punctual) and differential "E-L" (Early-Late) copies of the reference C / A code. The signal input of the programmable delay line 31 is connected to the output of the generator 30 of the reference C / A code generating a C / A GPS or GLONASS code depending on the commands received from the calculator 4. The second control input of the generator 30 of the reference C / A code forming a second reference input module 6, is connected to the output of the reference signals of the digital code generator 8. The outputs of the digital demodulators 34-37 are connected respectively to the inputs of the storage units 25-28.

In the inventive receiver of signals SRNS radio frequency Converter 1 can be implemented in accordance with the known, see, for example, [7, Fig. 3], a structural diagram. In accordance with this scheme, the radio frequency converter 1 in the considered implementation example contains (Fig. 4) an input unit 38, a unit 39 for first converting the frequency of GPS and GLONASS signals connected to its output, and first 40 and second 41 channels of the second connected to the output of unit 39 frequency conversion of signals, respectively, GPS and GLONASS. A receiving antenna is connected to the input of block 38 (not shown in FIG. 4). The composition of the radio frequency Converter 1 also includes a block 42 of the formation of signals of the clock and heterodyne frequencies. Channel 40 of the second signal frequency conversion (channel of the second GPS signal frequency conversion) contains a series-connected filter 43, the input of which is the channel input, a mixer 44 and an analog-to-digital conversion unit 45, the output of which forms the output of channel 40 — the output of the converted GPS signals of the RF converter 1 Channel 41 of the second signal frequency conversion (channel of the second GLONASS signal frequency conversion) contains a series-connected filter 46, the input of which is the channel input, see The carrier 47 and the analog-to-digital conversion unit 48, the output of which forms the output of the channel 41 — the output of the converted GLONASS signals of the RF converter 1. In the RF converter 1, the input block 38, which solves the problem of preliminary filtering the GPS and GLONASS input signals of the frequency range L1, contains at least one band-pass filter; block 39, which solves the problem of the first frequency conversion of GPS and GLONASS signals, contains at least one mixer; the mixers 44, 47 of the channels 40, 41 include frequency converters and amplifiers, for example amplifiers with adjustable gain; blocks 45, 48 analog-to-digital conversion can be performed, for example, in the form of threshold devices that implement the function of two-bit quantizers in level. Block 42 generating signals of clock and local oscillation frequencies contains tunable frequency synthesizers made on the basis of voltage-controlled generators (VCO) with phase-locked loop (PLL), operating from one common reference generator. Block 42, if necessary, may include switchable frequency dividers (multipliers), which, together with frequency synthesizers, provide the formation of the required grid of clock and heterodyne frequencies. The signal output of the first heterodyne frequency ("F _r1 ") of block 42 is connected to the reference input of block 39 formed by the reference input of the corresponding mixer, the signal outputs of the second ("F _r2 ") and third ("F _r3 ") heterodyne frequencies of block 42 are connected with the reference inputs of the mixers 44, 47 of the channels 40, 41. The outputs of the channels 40 and 41, which are the signal outputs of the radio frequency converter 1 ("GPS", "GLONASS"), are connected to the corresponding signal inputs of the channels 3 (3 ₁ , 3 ₂ ,.. ., 3 _N ) of the digital correlator 2. The output of the clock signal ("FT") of block 42, which is the clock the output of the RF converter 1, is connected with the corresponding clock inputs of the channels 3 (31, 3 ₂ ,..., 3 _N ) of the digital correlator 2, the clock input of the shaper 5 of the time stamp signals and the clock input of the unit 9 for generating additional low-frequency clock signals for the digital generator carrier 7 and a digital code generator 8 (Fig. 1). The input of the control signal ("Uyp") of block 42 is intended for a signal that, if necessary, realizes the restructuring of the elements of block 42 — synthesizers and frequency dividers (multipliers). The control signal input is connected, for example, to the calculator 4 via a data bus (not shown).

 Shaper 5 signals of time stamps, forming measuring strobes (signals of own time stamps of the receiver) in the inventive receiver, according to which the internal synchronization of the processes of correlation processing and navigation measurements is carried out, in the simplest case, can be performed, for example, according to the well-known scheme [7, FIG. . 1, blocks 5-8] in the form of a counter, a period register, and a period load signal shaper. In this case, the first counter input, which is the input of the clock signal Фт, is connected to the first input of the period load signal shaper, the counter output, which is the output of the measuring gates Fi (the output of the receiver’s own timestamps), is connected to the second input of the period load signal shaper, the output of the load signal shaper period is connected to the second input of the counter, the third input of the counter is connected to the output of the period register, the input of the period register is the control input of the shaper 5. In the period register by signal m, formed by the calculator 4, a number is recorded that determines the value of the period of the generated signals of the time stamps - measuring gates Fи. This number at a point in time, set by the counter overflow signal, is loaded into the counter using a period load signal shaper. The load moment is synchronized by the clock signal FT arriving at the first input of the driver 5 from the clock output of the RF converter 1. After loading, the counter is filled with pulses of the clock signal until overflow occurs. When overflowing at the counter output, a new timestamp signal is generated - a new measuring strobe Fand, after which the process is repeated.

 The constituent elements of the RF converter 1, the nodes and blocks are known elements, nodes and blocks used in the technique of reception and correlation processing of SRNS signals. So, the input unit 38 of the RF Converter 1 can be implemented as a band-pass ceramic filter; block 39 of the first signal frequency conversion can be implemented on the basis of a standard mixer, for example, microcircuit type MC13142 from MOTOROLA; filters 43, 46 can be implemented as band-pass filters on surface acoustic waves (SAWs); mixers 44, 47 and their amplifiers with adjustable gain can be implemented, for example, using NEC type UPC2753 microcircuits; the analog-to-digital conversion units 45, 48 can be implemented using dual comparators, for example, MAXIM type microcircuits MAX MAX. The clock and heterodyne frequency signal generating unit 42 can be implemented using standard elements, for example, TEMPUS-LVA type chips from MOTOROLA (reference generator), type MC13142 chips from MOTOROLA (VCO) and type LMX2330 chips from NATIONAL SEMICONDUCTOR (PLL) for implementation controlled frequency synthesizers, microcircuits of type MC12095, MC12093 of MOTOROLA company for the implementation of frequency dividers.

 Calculator 4 is implemented as a microcomputer of a standard configuration, containing standard elements - a processor, controller, operational, permanent, reprogrammable read-only memory devices, interfaces, data input-output ports. The functioning of the calculator 4 is carried out according to the standard algorithms of the navigation calculator of the multichannel receiver of SRNS signals.

 Digital correlator 2 with the considered structure of channels 3, i.e., with correlation processing modules 6, digital carriers 7 and code 8, as well as a time stamp signal generator 5 and an additional low-frequency clock signal generator 9 can be made in the form of VLSI (specialized large integrated circuit) using libraries of standard elements, for example, SAMSUNG ELECTRONICS or SGS TOMSON.

 The operation of the inventive receiver SRNS consider the example of the reception and processing of GPS and GLONASS signals, modulated with standard accuracy codes (C / A codes) in the frequency range L1, for the case when the GLONASS signals are signals with letter frequencies "0" - "12" or " -7 "-" 4 ", installed in accordance with [1].

 The inventive signal receiver SRNS works as follows.

The GPS and GLONASS signals of the frequency range L1 received by the antenna are fed to the signal input of the RF converter 1, i.e., to the input of input unit 38 (Figs. 1 and 4). GPS signals of the L1 band occupy frequency bands (1571, 328 - 1579, 512) MHz with a width of ΔF = 8.184 MHz (four lobes in the signal spectrum on both sides of the carrier to implement a “narrow correlator”), and GLONASS signals of the L1 band occupy frequency bands (1599, 956 - 1610, 794) MHz ΔF = 10.838 MHz wide (case of letter frequencies "0" - "12") and (1596, 019 - 1606, 294) MHz ΔF = 10.2755 MHz width (case of letter frequencies " -7 "-" 4 "). The input unit 38 transmits to its output GPS and GLONASS signals of the indicated frequencies, i.e., the frequency range (1571, 328 - 1610, 794) MHz. From the output of block 38, the GPS and GLONASS signals are fed to the input of block 39 of the first signal frequency conversion, where they are frequency-converted using a mixer, the reference input of which receives the first heterodyne frequency signal (F _r1 ) generated in block 42. When receiving GLONASS signals with with the letter frequencies “0” - “12” the value of the first heterodyne frequency F _r1 (l) = 1412 MHz, when receiving GLONASS signals with the letter frequencies “-7” - “4” the value of the first heterodyne frequency F _r1 (2) = 1408 MHz. The values of the heterodyne frequencies generated in block 42 are changed by the control signal ("Uyп"), received, for example, from the calculator 4. As a result of the first frequency conversion, GPS signals occupy the frequency band (159, 328 - 167, 512) MHz in the case of the letter frequencies "0" - "12" and the frequency band (163, 328 - 171, 512) MHz in the case of the letter frequencies "-7" - "4". In this case, the GLONASS signals occupy the frequency bands (187, 956 - 198, 794) MHz respectively for the first case and the frequency band (188, 019 - 198, 294) MHz for the second case. The GPS and GLONASS signals converted to the first intermediate frequency are fed to the inputs of the first 40 and second 41 channels of the second signal frequency conversion, i.e., to the inputs of the filters 43 and 46 (Fig. 4). Each of these filters performs band-pass filtering of the signals of the corresponding system, namely, filter 43 filters GPS signals in the frequency range (159, 328 - 171, 512) MHz, and filter 46 filters the GLONASS signals in the frequency range (187.956 - 198.794) MHz. From the output of the filters 43 and 46, the GPS and GLONASS signals are fed to the signal inputs of the mixers 44 and 46, where the second frequency conversion is performed. For the second frequency conversion of GPS signals, a second heterodyne frequency signal (F _r2 ) is used, which is generated in block 42. In the first case, the case of receiving the letter frequencies "0" - "12", this frequency is F _r2 (l) = 179 MHz, and in the second case - the case of receiving the letter frequencies "-7" - "4") - this frequency is equal to F _r2 (2) = 183 MHz. For the second frequency conversion of the GLONASS signals, the third heterodyne frequency signal (F _r3 ) is used, which is generated in block 42, for example, by dividing the signal of the first heterodyne frequency by eight frequencies. Thus, in the first case, F _r3 (1) = 1/8 • F _r1 (l) = 176.5 MHz, and in the second case, F _r3 (2) = 1/8 • F _r1 (2) = 176 MHz . As a result of the second frequency conversion, GPS signals occupy the frequency band (13.99 - 22.17) MHz for the first case and the frequency band (10.99 - 19.17) MHz for the second case, and GLONASS signals occupy the frequency band (11.46 - 22.29) MHz for the first case and the frequency band (12.02 - 22.29) MHz for the second case. Then the GPS and GLONASS signals are amplified using amplifiers with adjustable gains, which are part of the mixers 44 and 47, after which they undergo analog-to-digital conversion in blocks 45 and 48. The analog-to-digital conversion can consist in two-bit level quantization using the corresponding threshold devices - for example, MAXIM dual comparators of type MAX 962. With this analog-to-digital conversion, the signals generated by blocks 45 and 48 are characterized by the presence of a carrier, which is “removed” further in channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of digital correlator 2, namely, digital mixers 32 and 33 module 6 correlation processing (Fig. 3).

From the outputs of channels 40 and 41, GPS and GLONASS signals are sent to the first ("GPS") and second ("GLONASS") signal inputs of each of the channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of digital correlator 2 (FIG. . 1 and 3), i.e., to the corresponding signal inputs of the correlation processing modules 6. The clock inputs of channels 3 (clock inputs of modules 6, digital generators of the carrier 7 and code 8) receive the signal of the main clock frequency Fт. This clock frequency determines the frequency of time sampling during digital correlation signal processing.

The generation of a clock frequency signal Фт is carried out in block 42 of the RF converter 1, for example, from a signal of the third heterodyne frequency by dividing this frequency by eight (FT = F _r3 / 8≈22 MHz) with the subsequent generation of a meander signal. The value of the clock frequency Ft and the value of the frequency bands of the converted GPS and GLONASS signals are in an approximate ratio of 2: 1, which allows digital correlation processing of signals without loss of navigation information.

In channels 3 (3 ₁ , 3 ₂ ,..., 3 _N ) of digital correlator 2, digital correlation processing of the signals of N visible satellites of GPS and GLONASS systems is carried out in a combination determined by commands coming from calculator 4. During the correlation processing, the temporary position is determined peaks of the correlation functions of the signals of the corresponding N satellites, the radio navigation parameters used in the location calculations are determined. In this case, the readings of quasidality, phase of the carrier and the number of cycles of the carrier are made in accordance with the measuring gates (Fi) coming from the output of the shaper 5 signals of time stamps. The frequency of the measuring gates (1 - 10 Hz) is set by the signal supplied to the control input of the shaper 5 from the calculator 4. The correlation processing of the signals in channel 3 of the digital correlator 2 is carried out using the correlation processing module 6 under the influence of the reference signals generated by the digital generators of the carrier 7 and the code 8. The correlation signal processing is carried out under the control of the calculator 4. The following operations are performed.

 The switch 24 by the command generated by the control register 29 under the influence of control signals coming from the calculator 4, selects which of the two signals (GPS or GLONASS) will be processed in this module 6. The digital carrier generator 7 digitally generates the values of the phase of the reference carrier frequency the signal used in the process of quadrature "multiplication" with the input signal in digital mixers 32 and 33. Digital mixers 32 and 33 provide the allocation of the signal of this letter (GLONASS) or the signal of this traveler (GPS) and the transfer of the spectrum of this signal to the main frequency band (to zero frequency). Thus, as a result of the multiplication of signals in digital mixers 32 and 33, the carrier is removed from the in-phase and quadrature components of the signal and the spectrum of the signal is transferred to zero frequency.

 The digital carrier generator 7 is controlled by the signals of the calculator 4, in particular, the code of the carrier frequency of the signal is received from the calculator 4. Based on these data, the accumulating adder 12 (Fig. 2) generates the output signal of the digital carrier generator 7 in the form of the current values of the frequency phase of the reference signal. In addition, using the block 13 of the formation of samples in the generator of the carrier 7, the sample data of the carrier phase and the sample data of the number of cycles (periods) of the carrier are used, used by the calculator 4 in the process of tracking the frequency and phase of the carrier of the input signal. The work of the accumulating adder 12 of the digital generator of the carrier 7 is carried out with sampling frequencies determined by the main clock frequency Ft and the first clock frequency F1, and the formation of samples in block 13 of the formation of samples with the frequency of the measuring gates Fи. The reference signals generated by the digital generator of the carrier 7 (in the form of current phase values) are supplied to the reference inputs of the digital mixers 32 and 33. In the digital mixers 32 and 33, using code converters implementing the "sine-cosine tables", the phase values of the reference signal are converted to the corresponding amplitude values used in digital mixers 32, 33 for digital quadrature "multiplication" of the processed and reference signals.

 After "removing" the carrier in-phase and quadrature components of the processed signal and transferring the signal spectrum to zero frequency, digital demodulators 34-37 carry out a correlation comparison of the processed signal with the reference C / A codes generated using the programmable delay line 31 and the generator 30 of the reference C / A code .

 The reference clock frequency for the generator 30 of the reference C / A code (1.023 MHz for GPS and 0.511 MHz for GLONASS) is determined by the reference signal generated by the digital generator of code 8. In the digital generator of code 8, the output of the reference signal is generated using its accumulating adder 12, when in this case, the output signal is removed, for example, from the high-order bit of the output register of phase 17. In addition, in the digital code generator 8, the block 13 for generating samples connected to the adder 12 generates sample data for fractions of the code symbol, which, as e feedback signal is supplied to the calculator 4. The values of the reference clock frequency of the C / A code generated in the generator 8 are supplied to the accumulating adder 12 from the calculator 4. The accumulating adder 12 of the digital code 8 generator is operated with sampling frequencies determined by the main clock frequency FТ and the second clock frequency F2, and the formation of samples of the fractions of the symbol in block 13 of the formation of samples with the frequency of the measuring gates Fи.

 Based on the output signal of the digital code generator 8, which sets the clock frequency of the C / A code, the reference C / A code generator 30 generates a reference C / A code for processing the signal of the corresponding satellite of the corresponding system. The reference C / A code generated by the generator 30 is unique for each of the GPS satellites using code division of signals, and the same for all GLONASS satellites using frequency division of signals. The formation of a certain type of code, that is, a certain type of pseudo-random code sequence, is carried out in the generator 30 using the included pseudo-random code generator controlled by the calculator 4 (not shown). Feedback signals for calculator 4 (counts of the number of code symbols and the number of millisecond epochs) are generated using the counter of the number of code symbols and the register of the number of code symbols included in the generator 30 and the counter of the number of millisecond eras and the register of the number of millisecond eras (not shown ) Information is removed from the registers of the number of code symbols and the number of millisecond epochs with the frequency of the measuring gates Fi.

 The reference C / A code generated by the generator 30 enters the programmable delay line 31, which generates at its outputs an exact "P" (punctual) and differential "E-L" (early-minus-late) copy of the reference C / A code. An exact "P" copy of the reference C / A code is supplied to the second inputs of the digital demodulators 34 and 37, and the differential "EL" is fed to the second inputs of the digital demodulators 35 and 36. The programmable delay line 31 is operated by control signals generated by the control register 29 controlled by the calculator 4. In this case, the interval between the early and late copies of the C / A code is changed from 0.1 to 1 of the C / A code symbol duration, thereby forming a "narrow discriminator" ("narrow correlator") in the code tracking system [8 - 10].

 The results of correlation comparison carried out in digital demodulators 34-37 are accumulated in accumulation blocks 25-28 over a time interval equal to the duration of the code era (1 ms), and then are read by calculator 4 and used to close the tracking loops of the code and the carrier of the processed signal.

 In the considered general form, the operation of the inventive SRNS signal receiver is similar to that of the prototype receiver. The difference lies in the features of the formation of reference signals by digital generators of the carrier 7 and code 8. These features are as follows.

In contrast to the prototype receiver, the accumulating adder 12 of each of the generators 7 and 8 contains high-frequency and low-frequency parts, respectively
high-frequency 14 and low-frequency 15 storage modules, while the current output phase values generated by the accumulating adder 12 are the sum of the phase values generated by modules 14 and 15. The high-frequency storage modules 14 of both generators 7 and 8 operate with a sampling frequency determined by the main clock frequency F , the low-frequency storage module 15 of the digital carrier generator 7 operates with a sampling frequency determined by the first additional clock frequency F1, and the low-frequency storage tion unit 15 of the digital code generator 8 operates with a sampling frequency determined by the second additional clock frequency F2.

 The work of the accumulating adders 12 in the digital generators of the carrier 7 and code 8 is carried out according to the same algorithm, the difference lies in the bit depths of the storage modules 14 and 15, the sampling frequencies at which the low-frequency storage modules 15 operate, as well as in the frequencies of the generated output signals.

 As an example, consider the operation of the accumulating adder 12 of a digital generator of a carrier 7.

The first control input of the accumulating adder 12 of the digital generator of the carrier 7, i.e., the information input of the first register of the frequency code 18 of the high-frequency storage module 14, receives a K ₁ -bit number N ₁ proportional to the specified increment Δφ of the _RF current phase generated in each cycle frequency sampling signal FT. The number N _{1 is} set by the calculator 4, for example, based on the operating conditions of the "carrier tracking scheme". The number N _{1 is} written in the register 18 according to the corresponding recording signal generated by the calculator 4. From the output of the register 18, the number N ₁ goes to the first input of the first combiner adder 19. The K ₁ -bit number defining the value the current phase, accumulated in the first register of phase 20 to this measure. The result of summing these numbers is sent back to the phase register 20. Thus, at the output of the high-frequency storage module 14 with a frequency of Fm, the current values of the _{high-frequency} phase φ are generated, which is geometrically interpreted (in the phase-time coordinate system) by the step function shown in FIG. 5 curve "I". The slope of the “I” curve determines the phase increment rate and, therefore, the frequency fsint, rf of the signal synthesized by the high-frequency storage module 14. This slope, and hence the frequency fsint, rf of the synthesized signal, can be rapidly changed by changing the number N ₁ . The phase value φ of the _HF , taken at a frequency Ft from the output of the phase 20 register (Fig. 5, curve "I"), is fed to the first input of the output combiner 16.

To the second control input of the accumulating adder 12 of the digital generator of the carrier 7, i.e., to the information input of the second register of the frequency code 21 of the low-frequency storage module 15, a K ₂ -digit number N ₂ is proportional to the specified increment Δφ of the _{LF of the} current phase generated in each cycle frequency sampling signal F1. The number N _{2 is} recorded in the register 21 according to the corresponding recording signal generated by the calculator 4. From the output of the register 21, the number N _{2 is} supplied to the first input of the second combination adder 22. A K _2- bit number is received at the second input of this combination adder 22 with a frequency of F1, which determines the value of the current phase accumulated in the second register of phase 23 to this clock cycle. The result of summing these numbers is sent back to the phase 23 register. Thus, at the output of the low-frequency storage module 15 with the frequency F1, the current values of the _{low-frequency} phase φ are generated, which is geometrically interpreted (in the phase-time coordinate system) by the step function shown in FIG. 5 curve "II". The slope of the curve "II" determines the phase increment rate and, consequently, the frequency f synth, low frequency signal synthesized by the low-frequency storage module 15. This slope, and hence the frequency f synth, low frequency synthesized signal, can be changed by changing the number N ₂ .

The phase value φ of the _LF (accurate to K ₁ high order bits), taken from the output of K ₁ high order bits of the register phase 23 of the low-frequency storage module 15 (Fig. 5, curve "II"), arrives with a frequency F1 to the second input of the output combiner 16 , where it is added to the phase value φ of the _HF , arriving at a frequency Ft from the output of the phase register 26 of the high-frequency storage module 14 (Fig. 5, step curve “I”).

The result of the summation of the phases φ _HF + φ _LF = φ _SYNT. shown in FIG. 5 step curve "III". This result is recorded in the output register of phase 17, from where it is fed to the output of accumulating adder 12 with a frequency Ft. The slope of the step curve "III" determines the increment rate of the total phase φ _SYNT. and, therefore, the frequency fsint of the output signal synthesized by the accumulating adder 12. The slope of this curve, and hence the synthesized frequency fsint, in the general case can be set due to any of its components - curves "I" and / or "II" (frequencies fsint, tweeter and / or sync. woofer). In practice, the difference in the synthesized frequencies of the considered digital generators of different channels 3 of the digital correlator 2, due to the different letters for the GLONASS signals and the different clock frequencies C / A of the GLONASS and GPS codes, is provided by the difference in the low-frequency components fsint, woof.

Since the formation of the output values of the phase φ _{SINT, woofer} in the accumulating adder 12 is carried out by summing the two components (high-frequency φ _HF and low-frequency φ _LF ), there is an objective restriction imposed on the value of each of these components. The essence of this limitation is that in order to ensure uniqueness within the phase cycles of the generated values of the phase φ _SINT. the increment of the total phase at each sampling cycle should not be less than zero and more than 180 ^o (π). With this limitation in mind, specific relations are selected between the bits of the high-frequency 14 and low-frequency 15 storage modules and the values of the numbers recorded in them, and a certain cyclicity of operation (overflow periods) of the modules 14, 15 is also established.

Analyzing the characteristic of the phase accumulation in the accumulating adder 12 (Fig. 5, the step curve "III") and comparing it with the reference characteristic (Fig. 5, the straight line "IV"), it can be seen that the values of the total phase φ _SYNT formed by the accumulating adder 12 _. taken from the output register of phase 17, coincide with the reference values at the moments corresponding to the clocks of the sampling signal frequency Fт. At other moments, the values of the total phase differ from the reference ones, and this difference is systematic and is determined in time by the phase phase frequency F1 y of the digital generator of carrier 7 and F2 of the digital code generator 8. This systematic error, if necessary, is calculated by calculator 4 and taken into account in the form of corrective corrections during the operation of digital tracking systems of correlation signal processing. In particular, the systematic error for the digital generator of the carrier 7 is taken into account when performing absolute phase measurements, for example, at the moments of measuring the pseudorange and Doppler frequency shift along the phase of the carrier. In cases where absolute phase measurements are not performed, the values of the total phase generated by the digital generator of the carrier 7 are applied without correcting the systematic error.

где Δ- значение поправки (в долях фазового цикла);
fcинт. нч - частота, синтезируемая низкочастотным накопительным модулем 15 соответствующего цифрового генератора 7 (8) соответствующего канала 3 цифрового коррелятора 2;
Fт - тактовая частота (частота дискретизации);
k₁₍₂₎ - отношение частоты Fт к частоте F1(F2);
φ₁₍₂₎- фаза опорной частоты F1(F2) в момент измерения (значение счетчиков делителя частоты 10, формирующих соответствующую опорную частоту F1(F2) в момент измерения).In the inventive receiver, to ensure that this systematic error is taken into account, the phase reference register 11 is used, which is part of the shaper 9 of additional low-frequency clock signals (see Fig. 1). The register 11 fixes at the moments of arrival of the measuring gates F and the values of the counters included in the frequency divider 10. These values determine the phases φ ₁ and φ ₂ formed by the divider 10 additional clock frequencies F1 and F2. These values are read by calculator 4 and used to calculate corrections to the phase samples of the low-frequency components of the signals synthesized by digital generators of the carrier 7 or code 8, by the shift of the moment of measurement relative to the moment of the last correction according to the formula

where Δ is the correction value (in fractions of the phase cycle);
fint. LF is the frequency synthesized by the low-frequency storage module 15 of the corresponding digital generator 7 (8) of the corresponding channel 3 of the digital correlator 2;
FT - clock frequency (sampling frequency);
k _{1 (2)} is the ratio of the frequency FT to the frequency F1 (F2);
φ _{1 (2)} is the phase of the reference frequency F1 (F2) at the time of measurement (the value of the counters of the frequency divider 10, forming the corresponding reference frequency F1 (F2) at the time of measurement).

 The availability of technical means to determine and take into account the systematic error associated with the features of the dual-frequency accumulating adders 12 digital generators 7 and 8, makes it possible in the inventive receiver to carry out navigation measurements with the required accuracy. In this case, unlike the prototype receiver, a reduction in power consumption is provided.

 The decrease in power consumption, achieved due to the new (dual-frequency) design of digital generators of the carrier 7 and code 8, is due to the fact that the high-frequency storage module 14 of the accumulating adder 12 is low-discharge, and the high-discharge storage module 15 is low-frequency. This combination of high-frequency low-discharge and low-frequency high-discharge storage modules provides a reduction in energy consumption compared to the traditional solution based on the use of high-frequency and high-discharge storage adders in digital carrier generators and code.

 The estimate of the gain in power consumption can clearly be illustrated by the example of a digital code generator 8.

For evaluation purposes, we assume that the digital code 8 generator must generate a frequency five times higher than the C / A frequency of the GPS code (1.023 MHz), that is, the frequency f sync = 5 • 1.023 MHz = 5.115 MHz = (5 + 0.115) MHz, while the sampling frequency is Ft≈20 MHz, and the frequency setting discrete is Δf = 1 Hz.
For these conditions, the bit capacity K of the digital code generator of the traditional structure, determined from the formula Δf = Ft / 2 ^k , is K = 25, and the digital code generator 8 of the claimed receiver has the following parameters: the high-frequency storage module 14 is two-bit (K ₃ = 2) , operates with a sampling frequency of F≈20 MHz and synthesizes the frequency fint. high frequency = 5 MHz; low-frequency storage module 15 is 23-bit (K ₄ = 23), operates with a sampling rate of F2 = Ft / 20≈1 MHz and synthesizes the frequency f synth. woofer = 0.115 MHz.

An approximate estimate of the energy consumption P of a digital generator with an accumulating adder can be carried out, for example, using the empirical formula
P = F • Pg • Kg,
where F is the sampling frequency, MHz;
Pg - energy consumption per element (depends on the element base);
Kg is the number of digits.

 Under the conditions of the same element base, for example, when using the same D-flip-flops, the energy consumption of Pg per element in a digital generator of a traditional structure and in a two-frequency digital generator of the claimed receiver can be considered equal and not taken into account in the comparative evaluation.

Given this assumption, the consumption P _{0 of a} digital code generator of a traditional structure can be estimated as
P ₀ = F • Kg = Ft • (Ks ₀ + Kr ₀ ),
where Ks ₀ is the bit depth of the combination adder (K = 25);
Kr ₀ - bit phase register (K = 25).

Consumption P _{1 of a} two-frequency code generator can be estimated as
p ₁ = Ft • (Ks ₁ + Kr ₁ ) • 2 + F2 • (Ks ₂ + Kr ₂ ),
where Ks ₁ - the capacity of high-frequency combiners 16, 19 (K ₃ );
Kr ₁ - the resolution of high-frequency registers of phase 17, 20 (K ₃ );
Ks ₂ - bit capacity of the low-frequency combination adder 22 (K ₄ );
Kr ₂ - the resolution of the low-frequency register phase 23 (K ₄ ).

Considering that the consumption per one bit of the combinational adder and one bit of the phase register is approximately the same [12], the consumption P _{0 of a} digital code generator of a traditional structure and the consumption P _{1 of a} two-frequency digital code generator of the claimed receiver can be written as
P ₀ = Ft • K • 2≈20 • 25 • 2≈1000;
P ₁ = (FT • K ₃ • 4) + (F2 • K ₄ • 2) ≈ (20 • 2 • 4) + (1 • 23 • 2) ≈206.

Comparing the values of P ₀ and P ₁ , it can be seen that the gain in power consumption with respect to only one digital code generator 8 in the conditions of this example is more than 4.8 times. Actually, the gain in power consumption is higher, since in a generator of a traditional structure, a high-frequency high-discharge combiner must contain additional parallel transfer chains that are not taken into account in the considered example, which leads to an increase in the volume of this adder and, accordingly, its power consumption by several times. In the combinational adders of the inventive receiver, there are no such circuits, since the combiners 19, 16 are low-bit, and the combiner 22 operates at a sufficiently low frequency, which allows the use of adders with sequential transfer.

 The gain in power consumption in relation to the carrier generator 7, estimated by the above method, is at least 2.4 times.

 Given that the digital carrier and code generators are contained in all channels N of the channel digital correlator 2, and the number of channels can reach 12-24, the overall gain in energy consumption in the claimed receiver is significant.

 Thus, it can be seen from the above that the inventive receiver of the SRNS signals is technically feasible, industrially feasible and solves the stated technical problem of reducing the level of energy consumption. At the same time, the implemented positive features of the inventive SRNS signal receiver determine the prospects for its widespread use, especially in portable radio-navigation equipment with battery power.

Sources of information
1. "Global Navigation Satellite System - GLONASS. Interface control document. KNITS VKS Russia", 1995.

 2. "Global Position System. Standard Positioning Service. Signal Specification." USA, 1993.

 3. Network satellite radio navigation systems / V. S. Shebshaevich, P. P. Dmitriev, N. V. Ivantsevich and others // M., Radio and communication, 1993.

 4. Riley S., Howard N., Aardoom E., Daly P., Silvestrin P. "A Combined GPS / GLONASS High Precision Receiver for Spase Applications" / Proc. jf ION GPS-95, Palm Springs, CA, US, Sept. 12-15, 1995, p. 835-844.

 5. Digital radio receiving systems: Reference book / M. I. Zhodzishsky, R. B. Mazepa, E. P. Ovsyannikov et al. / Ed. M.I. Zhodzishsky, M., Radio and Communications, 1990.

 6. On-board devices of satellite radio navigation / I. V. Kudryavtsev, I. N. Mishchenko, A. I. Volynkin and others; under the editorship of B. C. Shebshaevich, M., Transport, 1988.

 7. RF patent 2146378 (C1), cl. G 01 S 5/14, publ. 04/10/2000.

 8. A. J. Van Dierendonck. Pat. Fenton and Tom Ford. Theory and Performance of Narrow Correlator Spacing in a GPS Reciever. Navigation: Jornal of The Institute of Navigation, Vol. 39, N 3, 1982.

 9. US patent 5390207, CL G 01 S 5/02, H 04 V 7/185, publ. 02/14/95. (Fenton, A. J. Van Dierendonck, "Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlators").

 10. US patent 5495499, CL. H 04 L 9/00, publ. 02/27/96. (Fenton, A. J. Van Dierendonck, "Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlators").

 11. G. I. Pukhalsky, T. Ya. Novoseltseva. Digital devices. - Polytechnic. St. Petersburg, 1996.

 12. Samsung's catalog of components - "STD 80 / STDM80 0.5 m 5V / 3 / 3V Standard Cell Library Data Book, 1996, Samsung Electronics Co., Ltd.".

Claims (1)

 A signal receiver of satellite radio navigation systems containing a radio frequency converter, the input of which forms the signal input of the receiver, an N channel digital correlator, the signal and clock inputs of each channel of which are connected to the corresponding outputs of the radio frequency converter, a calculator, as well as a signal generator of time stamps, the control input of which is connected bus data exchange with the computer, the clock input - with the clock output of the RF Converter, and the output of the measuring strobe c - with the inputs of the measuring gates of each channel N of the channel digital correlator, each channel N of the channel digital correlator contains a correlation processing module, a digital carrier generator and a digital code generator connected to the data bus, and each of these digital generators contains associated an accumulator and a sampling unit, the information input of which is connected to the data output of the accumulating adder by the bus of data exchange, the output the odes of the reference signals of these digital generators, formed by the corresponding outputs of their accumulating adders, are connected to the reference inputs of the correlation processing module, the clock inputs of these digital generators, formed by the clock inputs of their accumulating adders, and the inputs of the measuring gates formed by the inputs of the measuring gates of their readout units are connected , respectively, with the clock input and the input of the measuring gates of the correlation processing module, measure the clock input, input gates and the signal inputs of which form the corresponding inputs of channel N of the channel digital correlator, characterized in that the receiver has an additional low-frequency clock signal generator for the digital carrier generator and digital code generator, made in the form of a frequency divider and a phase register associated with it, the clock input of the frequency divider is connected to the clock output of the RF converter, the input of the measuring gates of the phase reference register is connected to the output of the meter of the strobes of the time stamp signal generator, the output of the phase count register is connected by a data exchange bus with the calculator, and the first and second outputs of the low-frequency clock signals of the frequency divider are connected respectively to the additional inputs of the digital carrier generator and digital code generator of each channel N of the channel correlator, while each of these digital generators, the accumulating adder is made in the form of high-frequency and low-frequency storage modules, and also contains connected the output combinational combiner and the output phase register, moreover, the high-frequency storage module contains serially connected the first register of the frequency code, the first combinational combiner and the first phase register, the output of which is connected to the second input of the first combiner and to the first input of the output combiner, the low-frequency storage module contains serially connected to the second register of the frequency code, the second combinational adder and the second phase register, the output of which is connected to the second input of the second combinational adder, and the output of the corresponding senior bits is to the second input of the output combinational adder, the clock input of the output phase register and the clock input of the first phase register of the high-frequency storage module connected to it form the clock input of the accumulating adder - clock input of a digital generator, clock the input of the second phase register of the low-frequency storage module forms an additional input of a digital generator, information inputs of the first and second of the frequency code registers of the high-frequency and low-frequency storage modules, respectively, form the first and second control inputs of the accumulating adder connected by the data exchange bus with the computer, the outputs of the bits of the output phase register and the outputs of the corresponding lower bits of the second phase register of the low-frequency storage module form the data output of the accumulating adder, connected through block of formation of readings with a calculator, and the outputs of the corresponding bits of the output phase register form the reference signal path of the digital generator connected to the corresponding reference input of the correlation processing module of channel N of the channel digital correlator.

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