RU2106759C1 - High definition tv receiver with low resolution - Google Patents

Abstract

FIELD: TV equipment, in particular, receivers of high definition compressed video signals with block encoding. SUBSTANCE: device thins out data in each block in order to generate images which resolution is typical for NTSC. EFFECT: simplified design. 20 cl, 11 dwg

Description

 The invention relates to high-definition television receivers and, in particular, to television receivers that receive high-definition television signals, but have a reduced cost and are comparable in quality to NTSC receivers.

 The systems proposed for the future United States of America high-definition television system that are currently being evaluated are mainly digital and provide relatively high resolution images. Since the signals are digital and due to the relatively high resolution, receivers designed to process such signals will require a significant amount of modern hardware, including significant amounts of video memory (television random access memory). Until the equipment reaches a sufficient level of development, which may take from ten to fifteen years, these hardware will make high-definition television receivers expensive, perhaps so much so that it will prevent middle-class families from buying more than one receiver in each home. However, most middle-class families are accustomed to having several receivers in their homes. Thus, in the near future there will be a need for high-definition television receivers with lower cost.

 According to the invention, a lower cost high-definition television signal receiver can be realized by sacrificing to some extent the clarity of the image. Such receivers will retain the advantages over NTSC receivers in that they will not have the usual NTSC system drawbacks such as cross distortion of brightness and color and, being digital, will be compatible with other digital equipment such as home computers.

 A typical high-definition television signal can represent 1050 lines of images with 1440 image elements on each line. A typical high-definition television receiver may require, for example, four video memory blocks for processing a decoded signal and additional storage devices for buffering several fields of compressed data. If you use 8-bit samples, then four blocks of video memory will require 48.38 Mbit of memory with very high speed. In contrast, if high-definition television signals are decoded to obtain a normal NTSC resolution of 525 lines with 910 picture elements per line, then only 15.29 Mbps of slower video memory is needed, or about one third of the amount required for a high-resolution image. Reducing the requirements for memory size and its speed can result in significant cost savings for a receiver with a lower resolution.

 According to the present invention, there is provided a device for receiving a high-definition television signal having a relatively high resolution, and in order to reduce the amount of hardware required to reproduce the image, this device uses only part of the information contained in the signal to generate a lower resolution image signal.

 In FIG. 1 is a graphical representation of a signal with a hierarchical structure used to describe the invention; figure 2 is a block diagram of a typical television receiver designed to process compressed digital television signals; figure 3 is a block diagram of a decompression device, which can be included in the block 14 shown in figure 2 as part of a high-definition television receiver; 4, 5, 7 and 8 are block diagrams of various forms of implementation of the decompression scheme according to the invention; FIG. 6 is a graphical representation of a typical sampling structure provided by the interpolator 319 shown in FIG. 5; in Fig.9 - typical alternative masking functions that can be implemented in the block shown in Fig.88 308; in FIG. 10 - an additional element 301; 11 is a block diagram of the algorithm of operation of part of the device shown in Fig.7.

 The invention is explained below in relation to a compressed digital television signal in the format proposed by the Advanced Television System Consortium (NBC, Thomson Consumer Electronics, North American Philips Corporation and SRI / DSRC). This format is similar to the standard proposed by the Group of Experts on Moving Image Coding (MPEG) and detailed in the document "International Organization for Standartization", ISO-IEC JT (1 / SC2 / WG1). Coding of Moving Pictures and Associated Audio, MPEG 90/176 Rev. 2, Dec. 18, 1990. This signal has a hierarchical multi-level structure and its shape is shown in FIG. It should be borne in mind that the invention is not limited to the use of such a signal, but is applicable at least to signals having similar formats.

 In FIG. 1 is a graphical representation of the general form of a television signal compressed according to the MPEG standard. The signal is arranged in the form of consecutive groups of GOPi images, each of which contains compressed data from the same number of image frames. Groups of images are shown in the top row of rectangles, labeled L1. Each group of images (L22) contains a header, followed by segments of image data (P1-Pn). The header of the image group contains data regarding the image size horizontally and vertically, frame format, field / frame rate, bit rate, etc.

 The image data (L3) for the respective fields / frames contains the image header, followed by the clipping data (L4). The corresponding clippings, GOBi, contain video information for adjacent areas of the image, for example, each clipping may contain data representing 16 lines of the image in order. The image header contains the field / frame number and type of image code. Each notch (L4) consists of a heading identifying its position in the image, and the following macroblocks of data MBi following this heading. The clipping header may also contain a group number and a quantization parameter.

 Macroblocks contain image data for clipping areas. A typical macroblock in MPEG format represents an image area spanning an array of 16x16 image elements. In fact, the macroblock contains 6 blocks, four of which carry information about the brightness, and two - information about the color. Each of the four brightness blocks represents a matrix of 8x8 pixels or one quarter of a matrix of 16x16 pixels. The blocks contain discrete cosine transform coefficients formed from the corresponding image element matrices. For example, each brightness unit formed from a matrix consisting of 8x8 pixels may contain up to 8x8, i.e. 64 discrete cosine transform coefficients. One of the coefficients (DC) transmits information about the constant component or average brightness, and each of the other coefficients (AC) transmits information related to different spectra of spatial frequencies of the image. The coefficients are arranged in a certain order: the coefficient (DC) of the constant component is located first, and the remaining coefficients - in the order of their spectral importance. Many images may contain little detail, as a result of which the values of many coefficients of the discrete cosine transform are zero. In the coefficient hierarchy in the respective blocks, all coefficients with a zero value following the last coefficient with a non-zero value are deleted from the block data and the block end code (EOB) is entered after the last coefficient with a non-zero value. In addition, coefficients with a zero value, which are located up to the last coefficient with a non-zero value, are encoded by the encoding method of series lengths. Therefore, in the data block there can be less than 64 coefficients.

 Each macroblock MBi (L5) contains a header, followed by motion vectors and coded coefficients. MVi headers contain the macroblock address, macroblock view, and quantization parameter. Coded coefficients are shown at level L6. Most of the data, including discrete cosine transform coefficients and header data, is variable-length encoded. In addition, some data, such as discrete cosine transform coefficients corresponding to a constant component, and motion vectors, are encoded using differential pulse code modulation.

 The data shown in FIG. 1 is typically interleaved to reduce the impact of errors in the block, and reformatted into transport packets with a fixed number of bytes to facilitate synchronization at the receiver. In addition, transport packets for error protection are encoded, for example, by a Reed-Solomon encoder, and parity bits are added to them.

 Figure 2 shows the overall structure of a high-definition television receiver. The radio signals of high-definition television broadcasting are received by the antenna 9 and supplied to the tuner demodulator 10. The output signal of the tuner demodulator is a digital stream of binary characters, which is fed to the device 11 direct error correction and elimination of alternation. The device 11 direct error correction and elimination of interleaving contains a circuit for correcting errors, for example, for the Reed-Solomon code, designed to detect and correct errors that occur during signal transmission, and a device for performing the operation, reverse interleaving data. Data with the corrected errors and the eliminated interleaving is served on the block 12, which disassembles the format of the packet used for transmission, and places the data in the usual sequence shown in figure 1. The functions of error correction, elimination of interleaving, and packet disassembly can be carried out in a different sequence, the reverse sequence of the inverse functions performed in the transmitter.

 The data with the changed format is supplied to the decoder 13 with a variable word length, where data encoded with a variable word length is decoded, and all data encoded by a series length encoding method is decoded. The decoded data is fed to a decompressor 14, which converts the compressed video data into raster element data and supplies the image element data to a video memory unit 15 (a television memory with random sampling), the image element data stored in the storage device is then fed to an image reproducing device, VCR, or other equipment 16 using the video signal.

 In FIG. Figure 3 shows an example of a decompression device suitable for processing video data in a format similar to MPE5. The device shown in FIG. 3 is similar to many known video decoders with prediction and motion compensation and does not require a detailed description. In the device shown in FIG. 3, data obtained using a variable-length decoder 300 is provided to a decompression controller 302. Differential pulse code modulation decoders 306A and 306B are integrated into the controller. Controller 302 extracts header data from the compressed video data to program a decompression sequence. Typically, a controller is a state machine programmed to run some special programs that depend on certain variables that are part of the header data.

 The controller 302 passes the coefficient data through a differential pulse code modulation decoder 306A, which passes the corresponding codewords unchanged or, if necessary, decodes them. The motion vector data is passed through a differential pulse code modulation decoder 306B, where these vectors are decoded. The decoded motion vectors are supplied to the predictor 304 with motion compensation, and the coefficients to block 310 of the inverse discrete cosine transform. Block 310, responding to blocks of coefficients, forms 8x8 matrices with information about image elements that are supplied in a predetermined order to adder 312. Data output from adder 312 corresponds to decompressed values of image elements. These values are entered into a display memory unit 318 (random access television memory) from which they can be displayed. The values output from the adder 312 are also provided to a pair of buffer memory devices (television random access memory devices) 314 and 316. Each of the buffer memory devices has a capacity sufficient to store one image frame. Storage devices 314 and 316 are connected to the predictor 304. In response to motion vectors, the predictor 304 reads blocks of 8x8 image elements from one or both of the storage devices 314 and 316 and feeds them to the adder 312.

 Typically, in a system like MPEG, data representing predetermined frames is encoded using the intraframe coding method, and data representing the remaining frames is encoded with the interframe encoding method. Data representing frames encoded by the intraframe method is formed by dividing the values of image elements into corresponding 8x8 blocks and discrete cosine transform of the image data. On the other hand, data representing frames encoded by the inter-frame method is generated by predicting image frames from the previous or subsequent, or from both frames, determining the differences (residuals) between the predicted and actual frames, and performing a discrete cosine transform of 8x8 blocks consisting of from the remnants. Thus, the discrete cosine transform coefficients in intraframe coding represent image data, and the discrete cosine transform coefficients in interframe coding represent frame difference data. For frames encoded in an intraframe manner, motion vectors are not generated. Motion vectors for frames encoded by the inter-frame method are code words that identify blocks of 8x8 picture elements in frames from which the predicted frames are formed, and these blocks most closely correspond to the current block being processed in the frame currently being encoded. For a more detailed explanation of the encoding / decoding process similar to MPEG, see US Pat. No. 5,222,875.

 In the device shown in FIG. 3, when processing the “I” frames encoded by the intraframe method, the predictor 304 is put into the mode of supplying zero values to the adder 312. The data obtained as a result of processing using the inverse discrete cosine transformation provided by the inverse discrete block 310 cosine transforms correspond to blocks of values of image elements. These values are passed through without adder 312 and entered into the memory unit 318 for visualization, as well as in one of the storage devices 314 or 316 for use in predicting subsequent frames. Immediately after the “I” frame is decoded, a “P” frame, encoded in an inter-frame manner and corresponding to a frame located a predetermined number of frames after the “I” frame, is provided from the variable-length decoder. This frame "P" was predicted in the encoder from the previous frame "I". Therefore, the discrete cosine transform coefficients for the frame "P" represent residuals that, when added to the values of the image elements of the decoded frame "I", will form the values of the image elements for the current frame "P". When decoding this “P” frame, the inverse discrete cosine transform unit 310 supplies the residual values to the adder 312, and the predictor 304, in response to the motion vectors, reads the corresponding blocks of image element values of the “I” frame from a random-access memory and provides them in the corresponding order to the adder 312. The sums issued by the adder are the values of the image elements for this frame "P". These image element values are loaded into the display memory unit 318 and to that of the storage devices 314 or 316, which does not store the decoded image element values of the “I” frame.

 Following the decoding of frame "P", encoded frames (frames "B") are provided, which are usually located between frames "I" and "P". These frames are inter-frame encoded and therefore decoded similarly to frame "P". However, the decoded frame “B” data is not stored in memory devices 314 and 316, since this frame “B” data is not used to predict other frames.

 FIG. 4 illustrates one embodiment of the invention. It shows, in simplified form, part of the device shown in FIG. 3, and the blocks in FIG. 4, denoted by the same positions as in FIG. 3, are the same blocks. 4, a two-dimensional decimator (decimator) 311 is introduced between the inverse discrete cosine transform unit 310 and the adder 312. The decimator 311 includes a downsampling device to exclude, for example, every second row of values and every second value (values of image elements or residual image elements) in the remaining rows of image element matrices formed by the inverse discrete cosine transform block, to reduce by four times the number of samples of image elements. Sub-sampling can be adapted to exclude image elements that are on the same vertical line, or in a checkerboard pattern, to provide higher effective resolution for a reduced amount of data. The decimator may also comprise a low pass filter to prevent spectra from overlapping during the downsampling process. Other downsampling formats may also be used. However, if the downsampling is performed by simply dropping the values of the image elements, then the downsampling coefficients are limited to powers of 2. On the contrary, if the downsampling is done by interpolation, a wide selection of decimation (decimation) coefficients can be provided.

 Since the amount of data has been reduced by four times, the capacity of a buffer or random access television memory is reduced by four times compared with the device shown in FIG. 3. The random access television storage device 315 shown in FIG. 4 is generally a variation of the storage devices 314 and 316 shown in FIG. However, note that in FIG. 3, two storage devices 314 and 316 can be implemented as either a single memory unit or as several memory units.

 Similarly, the performance requirements of circuits following decimator 311 are reduced. The predictor 304 'is different from the predictor 304 in FIG. 3 by the fact that, in response to motion vectors, it reads the matrix of values of image elements in size, for example, 4x4, and not 8x8 matrixes. An additional difference is the addressing structure. Nominally, the predictor generates addresses or at least starting addresses for reading matrixes of image elements identified by motion vectors. Video memory of reduced size will not have addressable cells (and therefore addresses) corresponding to all possible addresses represented by motion vectors. However, this difficulty can be overcome by generating addresses in the predictor in the same way as for a larger memory structure, but using only the most significant bits of the generated addresses. Thinning with a coefficient of 2 both in the vertical and horizontal directions entails the submission of all bits of the values of the vertical and horizontal addresses to the video memory address buses, with the exception of the least significant bit. Alternatively, motion vectors may be truncated using truncation block 307 before being fed to the predictor, as shown in FIG. 4.

 FIG. 5 shows yet another embodiment of the invention which provides improved images compared to that shown in FIG. 4 form of the invention. The improvement is achieved due to the advantage of using full motion vectors rather than truncated motion vectors or truncated memory addresses acting on the storage device 315. In FIG. 5, an interpolator 319 is inserted between the storage device 315 and the predictor 304 ". In addition, a two-dimensional decimator 313 similar to the decimator 311 is inserted between the predictor 304" and the adder 312. The interpolator 319 receives data blocks from the storage device 315 and forms 8x8 blocks which are supplied to predictor. The predictor submits 8x8 data blocks to decimator 313, which downsamples the data, converting it again into 4x4 data blocks in accordance with the format of the data supplied to the adder from decimator 311.

 To understand how this process improves the accuracy of image restoration, we turn to FIGS. 5 and 6. FIG. 6 shows the operation of the interpolator 319. For this illustrative algorithm, it is assumed that 5x5 data blocks are read from memory 315, and not blocks of size 4x4. A 4x4 block of data that would be read using a truncated address is located in the upper left corner of a 5x4 block that is read from the storage device. The 5x5 data block read from the storage device is represented in FIG. 6 by open circles. Black rhombuses are interpolated values. The interpolated values can be calculated by any of the known two-dimensional interpolation methods. For example, the interpolated values in rows with even numbers R0, R2, R6 and R8 can be formed by averaging two values between which the interpolated values are located. Interpolated values in odd-numbered lines can be calculated by averaging the values above and below the corresponding interpolated values. The value matrix shown in FIG. 6 consists of 9 rows and 9 columns. The interpolator feeds to the predictor 304 a matrix of 8 rows and 8 columns. Therefore, it is possible to select data. In this example, the selection is determined by the low-order bit of the address of the starting point formed by the predictor to read the data block from memory 315. If the low-order bit of the vertical address is an even number or a logical zero, then the matrix output by the interpolator contains the rows R0 - R7. If the least significant bit of the vertical address is an odd or logical unit, then the matrix output signal contains the rows R1 - R8. Similarly, if the least significant bit of a horizontal or column address is even (odd), the matrix generated by the interpolator contains columns C0 - C7 (C1 - C8). In the thinned region, the choice of alternating matrices that are shifted one relative to the other by a row and / or column provides an improvement (in comparison with sub-sampled images) of the accuracy of the reconstructed image with a reduced resolution by half the size of the image element.

 As the interpolator 319, other interpolation devices can also be used that will determine the size (for example, 4x4, 5x5, 6x6) of the matrices read from the storage device 315.

 Shown in FIG. 5, an embodiment of the invention has such advantages as reduced memory, slightly improved resolution, and lower performance requirements for circuit elements following decimator 311.

 FIG. 7 illustrates yet another embodiment of the invention that is similar to the embodiment shown in FIG. 5 in that it provides an improvement in resolution equal to half an image element. Shown in Fig.7, the device contains a decimator 311 connected between the output of the adder 312 and the inputs of the memory blocks. This eliminates the need for a decimator between the predictor 304 and the adder 312, and therefore requires slightly less hardware than the device shown in FIG. 5. However, in this embodiment, the adder needs to perform 8x4 or 64 totalizations per block, rather than 4x4 or 16 totalizations per block. The rest of the circuit works in the same way as shown in FIG.

 A variation of FIG. 7, the circuit can be implemented by connecting the storage device 315 directly to the predictor 304 "and turning on the interpolator 319 between the predictor 304" and the adder 312.

 FIG. 8 serves to explain a preferred embodiment of the invention, which provides not only a reduction in the volume of storage devices, but also a decrease in the complexity of the inverse discrete cosine transform unit 320. In the device shown in Fig. 8, thinning of the matrix of image elements is carried out directly in block 320, i.e. the inverse discrete cosine transform block supplies thinned blocks of pixel values to the adder 312, as a result of this, the rest of the circuit is implemented and works similarly to the device shown in FIG. 5. The data supplied to the inverse discrete cosine transform block 320 is a sequence of coefficients that represent the spatial frequency spectra of the image areas represented by 8x8 matrices. In this example, the corresponding frequency spectra for the corresponding image areas are represented by coefficients, the number of which, depending on the image content, can be up to 64. If the number of coefficients supplied to the inverse discrete cosine transform unit decreases, then the spatial resolution of the image areas decreases along with it. represented by matrices of image elements at the output of the inverse discrete cosine transform block. As spatial resolution decreases, image areas can be represented by fewer image elements without further degradation of image quality. If the image area can be represented by fewer image elements, then the inverse discrete cosine transform block can be constructed to calculate fewer output values.

 Assume that the device shown in Fig. 8 is designed to receive images corresponding to thinning out transmitted information with a coefficient of 2 in the vertical and horizontal directions, and that the inverse discrete cosine transform block 320 is adapted to calculate 4x4 matrices of output values from 4x4 matrices input coefficients. This leads to significant hardware savings in the inverse discrete cosine transform block, as well as to a decrease in the required speed of this block. Matrix of 4x4 coefficients extracted from matrices of 8x8 transmitted coefficients is supplied to block 320 of the inverse discrete cosine transform. This selection of matrices consisting of 4x4 coefficients performs the coefficient masking unit 308 shown in FIG. Block 308 is depicted as a square with a matrix of 8x8 pixels. Each of the points represents a coefficient. The points in the shaded part of the square are used to indicate the coefficients that are discarded or not supplied to the inverse discrete cosine transform block. The significance of each of the coefficients for image restoration is known a priori. Therefore, the developer can choose for processing those coefficients that he believes will be most useful for image restoration. In the nominal format of the MPEG signal, the coefficients are arranged in increasing order in the frequency spectra, and in relation to the matrix shown, in a zigzag pattern. Therefore, in the simplest case, it is only necessary to select the first 16 coefficients transmitted for each image area.

 Thinning in the device shown in FIG. 8 is efficiently performed in the frequency domain, therefore, filters that eliminate spectral overlapping effects are not needed in the processing path, with the exception of decimator 313, in which they may be desirable.

 The masking function can be performed in the decompression controller 302 (Fig. 3), which is shown in Fig. 10 by an additional element 301. Note that the element 301 can be a separate hardware device, or its functions can be programmed in the controller 302. The masking process is explained below. using the flowchart shown in FIG. 11.

 The masking function is a function of monitoring the available data and highlighting a given part of it. If the data is presented in MPEG format, then they are divided by hierarchical levels, as shown in figure 1. This data contains header data down to the block level. All header data is needed by the decompression controller, and therefore, element 301 is put into header data transmission mode. At the block level, the data contains discrete cosine transform coefficients or block end codes (EOBs). Depending on the content of the image, each block can contain from 1 to 64 coefficients with the last non-zero coefficient, followed by the end code of the EOB block. If the block contains more than 16 coefficients, element 301 skips the first 16 coefficients, then the EOB code of the end of the block and discards all subsequent coefficients that make up the block. The end of the block is recognized by the appearance of a special EOB code for the end of the block. At this point, data for the next block starts, its first 16 coefficients are highlighted, etc.

 According to FIG. 11, data from the decoder 300 is received (80) and checked (81). If the data is header data, it is passed to the controller 302, and the count value (84) is set to zero. If the data is not header data, it is checked (83) to determine if it is coefficient data. If they are not coefficient data (for example, they can be motion vector data, etc.), then they are passed to controller 302. If they are coefficient data, the count value increases (84). The count value is checked and the (85) data is checked to determine if it is a block end code. If the count value is greater than N (in this example, N = 16), the data is discarded (86) until a block end code appears, which is also discarded, since it is redundant data. If the count value is less than N, the data is checked (88) to determine if it is a block end code. If they are not a block end code, then they are passed (87) to the controller and the following data word is checked (81). If they are a block end code (EOB) indicating that all other coefficients in a block have zero values, the block end code is passed to the controller 302, and the count is set to zero (89) in order to prepare the next next block for the beginning of data. If at step 85 the counting value is N, then the data word that caused the counting value to increase to N is replaced by the block end code.

 9, a, b, c show possible alternative masking functions for the coefficients. The masking function shown in FIG. 9c causes the spatial frequency response of the vertical and horizontal to be different. This masking function can be applied when an image, for example, with a 4: 3 aspect ratio is converted to an image with a 16: 9 aspect ratio.

 In the description of the invention, a decimation factor of two is used, vertically and horizontally, but the invention is not limited to factors of two. In general, any thinning factors from 1 to 8 can be used, although the two extremes have little practical value.

Claims (20)

 1. A device for decompressing video data compressed by digital conversion and placed in blocks representing the corresponding image areas of successive frames with the first spatial resolution, each of which consists of many separate image areas, characterized in that it contains a predictor memory unit for storage decompressed video data, decompression means of respective data blocks, including inverse transform means and configured to receive decompressed video signal representing corresponding image areas with a second spatial resolution lower than said first spatial resolution, and decompressed video signal supplying means into the memory unit.  2. The device according to claim 1, characterized in that the compressed video data is placed in blocks of code words representing M x M image elements, and decompression means are configured to form blocks of N x N image elements representing image areas, where M and N are integers, and M is greater than N.  3. The device according to claim 1 or 2, characterized in that the blocks of compressed video data consist of coefficients formed by the transformation of matrices from M x M values of image elements, and the decompression means comprise means for the inverse transformation of matrices consisting of N x N conversion coefficients, and means for responding to said coefficients formed by converting matrices consisting of M x M values of image elements to form matrices consisting of N x N coefficients and supplying them to said reverse conversion means conditions for performing inverse transformations for the corresponding image regions, where M and N are integers, and M is greater than N.  4. The device according to claim 1 or 2, characterized in that the blocks of compressed video data consist of coefficients formed by a discrete cosine transform of matrices consisting of M x M values of image elements, and decompression means comprise means of inverse discrete cosine transform of matrices consisting of N x N coefficients of the discrete cosine transform, and means that respond to these coefficients formed by a discrete cosine transform of matrices consisting of M x M pixel values, for forming matrix consisting of N x N coefficients, and supply them to said means for inverse discrete cosine transform for performing inverse discrete cosine transforms for respective image areas, where M and N - integers with M greater than N.  5. The device according to claim 3, characterized in that it further comprises an adder, the first input of which is connected to the inverse conversion means and the output of which is connected to the memory unit, and a motion compensated video predictor included between the memory unit and the second adder input.  6. The device according to claim 5, characterized in that it further comprises an interpolator included between the memory unit and the motion-compensated video signal predictor for generating matrices consisting of M x M values of image elements from matrices consisting of N x N values image elements read from the memory unit and a decimator included between the motion compensated video predictor and the second input of the adder to form matrices consisting of N x N values of image elements from matrices consisting of M x M pixel values obtained from the motion compensated video predictor.  7. The device according to claim 6, characterized in that the compressed video data contains motion vectors that are transmitted to the predictor of the video signal with motion compensation and set its mode so that it generates addresses for reading the corresponding matrix of image element values from the memory block, the least significant bit These addresses are supplied to control the interpolator.  8. The device according to claim 1 or 2, characterized in that the decompression means of the respective data blocks comprise a first decimator having an input for receiving blocks of compressed video data for generating matrices consisting of N x N values of the compressed video signal from matrices consisting of M x M values of the compressed video signal, an adder whose first input is connected to the output of the first decimator and whose output is connected to the memory unit, an interpolator, whose input is connected to the memory unit, to form matrices consisting of M x M element values image, from matrices consisting of N x N values of image elements read from the memory block, a motion compensated video signal predictor, the input of which is connected to the output of the interpolator, and a second decimator, connected between the motion compensated video signal predictor and the second adder input, to form matrices consisting of N x N pixel values, of matrices consisting of M x M pixel values coming from a motion compensated video signal predictor.  9. The device according to claim 8, characterized in that the compressed video data contains motion vectors that are transmitted to the predictor of the video signal with motion compensation and set its mode so that it generates addresses for reading the corresponding matrix of image element values from the memory block, the least significant bit These addresses are supplied to control the interpolator.  10. The device according to claim 1 or 2, characterized in that the decompression means of the respective video data blocks comprise an adder having a first input for receiving compressed video data blocks, a decimator, the input of which is connected to the output of the adder and the output is connected to the input of the memory block, for forming matrices consisting of N x N values, from matrices consisting of M x M values coming from the adder, an interpolator, the input of which is connected to the memory unit, to form matrices consisting of M x M values of image elements, from matrices consisting of and h N x N values of image elements read from the memory unit, and a motion compensated video signal predictor whose input is connected to the output of the interpolator and whose output is connected to the second input of the adder.  11. The device according to claim 10, characterized in that the compressed video data contains motion vectors that are transmitted to the predictor of the video signal with motion compensation and set its mode so that it generates addresses for reading the corresponding matrix of image element values from the memory block, the least significant bit These addresses are supplied to control the interpolator.  12. The device according to claim 1 or 2, characterized in that the decompression means of the respective video data blocks comprise an adder having a first input for receiving compressed video data blocks, a decimator, the input of which is connected to the output of the adder and the output of which is connected to the input of the memory unit, to form matrices consisting of N x N values from matrices consisting of M x M values coming from the adder, a motion compensated video signal predictor whose input is connected to the memory unit and an interpolator whose input is connected to the output to a predictor of a video signal with motion compensation and the output of which is connected to the second input of the adder, to form matrices consisting of M x M values of image elements from matrices consisting of N x N values of image elements generated by the predictor of a video signal with motion compensation.  13. The device according to p. 12, characterized in that the compressed video data contains motion vectors that are transmitted to the predictor of the video signal with motion compensation and set its mode so that it generates addresses for reading the corresponding matrix of values of image elements from the memory block, the least significant bit These addresses are supplied to control the interpolator.  14. A device for decompressing video data placed in blocks representing the corresponding image areas of successive frames with the first spatial resolution and including matrices of M x N transform coefficients representing matrices of M x N values of image elements and motion vectors, having a spatial resolution of at least equal to the first spatial resolution of the image elements, characterized in that it is configured to receive decompressed a video signal representing the corresponding image areas with a second spatial resolution lower than the first spatial resolution and contains a source of matrix blocks of M x N transform coefficients, means including inverse transform means and responsive to said blocks of M x N transform coefficients to form corresponding matrices from S x R values, where M, N, S, R are integers, with M x N> S x R, means including a motion compensated predictor that respond to the indicated m trices from S x R values and to said motion vectors for forming matrices from S x R values of image elements representing the corresponding image areas with a second spatial resolution, the motion compensated predictor comprising means for essentially matching the spatial resolutions of motion vectors and matrices from S x R values, and a memory unit for storing respective matrices of S x R image element values.  15. The device according to p. 14, characterized in that the means, including the predictor with motion compensation, further comprise an adder, the first input of which is connected to the inverse transform means, the second input of which is connected to the output of the predictor with motion compensation and the output of which is connected to the memory unit .  16. The device according to any one of paragraphs. 14 or 15, characterized in that the means comprising a motion compensated predictor further comprises an interpolator coupled to the predictor to form matrices consisting of M x N pixel values from matrices consisting of S x R pixel values read from the memory block.  17. The device according to any one of paragraphs.14 to 16, characterized in that the means, including the predictor with motion compensation, further comprise a decimator included between the predictor with motion compensation and the second input of the adder to form matrices from S x R values of the image elements and feed them to the adder.  18. The device according to any one of paragraphs. 14 to 17, characterized in that motion vectors are supplied to the predictor with motion compensation, which set its mode so that it generates addresses for reading the corresponding matrix of image element values from the memory unit, the least significant bit of these addresses being supplied for controlling the interpolator.  19. The device according to any one of paragraphs.14 to 18, characterized in that the means including the inverse transform means further comprise masking means connected to the source of matrix blocks of M x N transform coefficients to provide the inverse transform means only S x R coefficients, wherein the inverse transform means are configured to process S x R coefficients to obtain S x R converted values.  20. The device according to any one of paragraphs.14 to 18, characterized in that the means including the inverse transform means further comprise means for supplying matrix blocks of M x N transform coefficients to inverse transform means connected to the source of matrix blocks from M x N coefficients, wherein the inverse transform means form matrices of M x N converted values for the corresponding blocks of M x N coefficients, and a decimator connected to the inverse transform means for thinning the matrices of M x N transformed values to obtain a matrix of values S x R.

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