JPH0923425A - Picture compression device for picture stamp - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a picture stamp at high speed by collectively recording picture compression data required for constituting the slave screen of low resolution. SOLUTION: A blocking circuit 14 dividing input picture data constituting a master screen into respective blocks of prescribed size, a DCT conversion circuit 16 which DCT-converts blocked input picture data, a quantization circuit 18 quantizing a DCT coefficient which is DCT-converted and a variable length encoding circuit 20 which variable length-encodes a quantized level are provided. A pair of memories 52 and 54 which separately store a variable length encoding level equivalent to a DC coefficient and the other variable length encoding level among the quantized levels which are variable-length-encoded and a recording means recording the variable length encoding level equivalent to the DC coefficient in a specified place are provided. At the time of reproduction, the DC coefficient is reproduced to slave screen picture data for picture stamp. Since the DC coefficient can be reproduced at high speed, the picture stamp can be reproduced at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for a picture stamp image suitable for an editing process in which a main screen is compressed and a plurality of low-resolution small screens are simultaneously displayed on the same screen for video editing. It relates to a compression device. Specifically, when recording compressed image data on a medium, by collectively recording the compressed image data required to configure a low-resolution small screen, it is possible to play the small image for a picture stamp at high speed with a small hardware scale. It was done.

[0002]

2. Description of the Related Art An image compression apparatus using bit reduction is known. For example, when performing DCT (discrete cosine transform) method bit reduction without using the time direction, a video encoder 10 as shown in FIG. 10 is used. This process is based on JPEG (Joint Photgraphic Expert)
s Group) is currently used in many reduction methods.

As shown in FIG. 10, input image data in frame units, for example, supplied to a terminal 12 is supplied to a blocking circuit 14 and divided into unit blocks of, for example, 8 pixels × 8 lines. In this example, where the DCT block divided into unit blocks is a type of orthogonal transform, DC
The signal is supplied to a T (discrete cosine transform) conversion circuit 16 and subjected to a discrete cosine (cosine) conversion process.

The DCT transform is a process for transforming image data (sample plane data) into a two-dimensional frequency component, and the lowest component divided into unit blocks is called a DC component (DC coefficient). The data after DCT conversion (DC coefficient) is the total value of the pixel data of the DCT block. High frequency components other than the DC coefficient are called AC coefficients (AC components). In the above example, one of the 8 × 8 = 64 DCT coefficients is DC
The remaining 63 coefficients are AC coefficients.

The DCT coefficient is supplied to the quantizing circuit 18, and the DCT coefficient is supplied so as to satisfy the bit rate after data compression.
The T coefficient is quantized in the quantization step. The quantization level, which is the output data after quantization, is supplied to the variable length coding circuit (VLC circuit) 20 together with the quantization index as index information indicating the quantization step. The quantization level is subjected to variable length coding (VLC conversion) with a code such as Huffman code to obtain a compressed bit stream.

This bit stream is sent out on a communication path or recorded on a storage medium (not shown) such as a tape or a disk. The bitstream also includes a VLC quantization index. This is because the quantization index is necessary on the video decoder side when reproducing the image data.

FIG. 11 shows an example of the video decoder 30.
The compressed bit stream input to the terminal 32 is decoded by the variable length decoding circuit (VLD circuit) 34. The quantization index is also decoded.

The decompressed compressed data is dequantized by the inverse quantization circuit 36.
The quantization step is multiplied by. The data thus obtained is called a "representative value". The typical value is the inverse DCT circuit (ID
In the CT circuit), processing opposite to DCT conversion is performed. By this inverse DCT processing, the frequency plane data is returned to the sample plane data (DCT block). Finally, the data of the DCT block is rearranged into a raster scan by the block / raster conversion circuit 39 to obtain a reproduced image that is similar to the input image.

[0009]

By the way, there is an application for reproducing a sub-screen having a lower resolution than the original output image (main screen). This is called a picture stamp. The main uses of picture stamps are: (1) High-speed retrieval (referred to as browsing) can be performed freely by using images recorded in a storage medium as picture stamps together with time codes. (2) When video editing, cut-in points and cut-out points are cut out and displayed as picture stamps so that the editing points can be determined while watching them, thus improving the efficiency of editing work. There are advantages.

To reproduce the picture stamp from the bit stream transmitted or accumulated by the bit reduction method, the above DCT coefficient may be used. Since the DCT coefficient is converted into VLC, a decoding process is once performed to generate the picture screen child screen data.

To this end, as shown in the picture stamp reproducing apparatus 40 of FIG. 12, the transferred compressed bit stream or the bit stream reproduced from the storage medium is supplied to the terminal 42, and this is supplied to the preamplifier 4.
4 is supplied to the VLD circuit 46 to extract only the quantization level of the DC coefficient, and then the inverse quantization circuit 48 multiplies the quantization step to restore the DCT coefficient. Of the DCT coefficients, only the DC coefficient is used, and the data obtained by dividing the DC coefficient by an appropriate number is supplied to the block / raster conversion circuit 50 to correspond to the raster position on the screen. Since the DC coefficient obtained from each DCT block is the average value of the respective pixel values, a low-resolution child screen (picture stamp child screen) can be reproduced by using the DC coefficients of all DCT blocks.

When one DCT block has a size of 8 × 8, the obtained picture stamp is 1 of the actual reproduced image.
Since the size is / 8, the monitor screen S as shown in FIG.
A plurality of picture stamp sub-screens Si (i is an integer) can be simultaneously displayed on the screen. In FIG.
The screens Sa and Sb show real-time reduced parent screens.

In order to realize this picture stamp method, it is necessary to efficiently extract only the DC coefficient from the bit stream, but since the bit stream is composed of VLC, the VLC circuit 34 is used to input the input bit stream. The DC coefficient cannot be decoded unless it is decoded in order from the start code. Therefore, the decoding of the DC coefficient ends up decoding most of the codes, and in reality, unnecessary AC coefficients must be decoded at the same time. Therefore, there is a practical problem because it is inefficient in terms of hardware and processing time.

There is also a method of recording the picture stamp data separately from the image data (bit stream) for normal reproduction in advance, but in this case, an extra data area is required and the image quality is deteriorated due to deterioration of efficiency. I have a problem to do.

In addition, MPEG (Moving Picture Experts)
Intra-picture (intra-frame processing) can be played back as a picture stamp in compression using the time direction as represented by Group), but inter-picture (inter-frame processing) cannot be played back, so the resolution in the time direction becomes low and it becomes practical. There's a problem.

In consideration of the above, the present invention proposes a picture stamp image compression apparatus capable of reproducing a picture stamp at high speed on a small hardware scale.

[0017]

In order to solve the above-mentioned problems, in the invention described in claim 1, in the image compression apparatus using the bit reduction method, the parent screen is reduced to start from a low-resolution child screen. The image compression data dedicated to the child screen and the quantization index necessary for forming the picture stamp are recorded separately from the image compression data for the parent screen.

Image compression data dedicated to the sub-picture necessary for forming the picture stamp consisting of the low-resolution sub-picture by reducing the main picture, that is, D obtained in each DCT block
The VLC data of the C coefficient and the quantization index at that time are recorded separately from the parent screen image compressed data. If it is a tape medium, it is recorded immediately after the sync code.

It is also possible to combine only the DC components.
For example, tape media are arranged in a specific sink, and disk media are arranged in a specific sector. By doing so, only the DC component can be selectively taken out, and the child screen compressed data for the picture stamp can be easily reproduced. In this case, the hardware required is only the VLD dedicated to the DC coefficient, the inverse quantizer, and the DCT block-raster scan conversion unit.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a case where an embodiment of an image compression apparatus for a picture stamp according to the present invention is applied to the above-described image compression / decompression system will be described in detail with reference to the drawings. Also in this invention, since the image compression is a bit reduction method using DCT conversion, the basic data processing (DCT conversion, quantization, VLC conversion, etc.) is the same as the conventional one, and the detailed description thereof is omitted. .

FIG. 1 shows an embodiment of the present invention relating to a video encoder 10 for a picture stamp by an intra picture. The input image data of the frame structure supplied to the terminal 12 is divided into unit blocks by the blocking circuit 14, and the divided unit block image data is DCT-converted by the DCT circuit 16. DCT transform is a kind of orthogonal transform. DCT coefficient is quantization circuit 1
8 is quantized, and the quantized level is supplied to the VLC circuit 20 together with the quantized index used at that time for variable length coding.

As described above, the DCT coefficient is a DC coefficient (DC component of the DCT block) and an AC coefficient (AC component).
According to the present invention, only the DC coefficient indicating the average pixel value of the DCT block is used as the compressed image data for the child screen which constitutes one pixel of the picture stamp.

Of the VLC-encoded bit stream,
Each of the DC coefficient and the quantization index is temporarily stored in the buffer memory 52, and the AC coefficient is temporarily stored in another buffer memory 54. VL in the VLC circuit 20
Each DCT of the C-converted bit stream data
The data indicating the start of the block is the memory selector 56.
Is detected by the buffer memory 52,
The data writing to 54 is switched.

The DCT coefficients buffered in the buffer memories 52 and 54 are alternately taken out by the switch 58 and obtained at the terminal 10b as bit stream data. The switch 58 is controlled by a switching pulse 59 synchronized with a sync code described later.

This bit stream data is sent to a transmission line or stored in a storage medium. Tapes and disks can be considered as storage media. When recording on tape, a helical track is used.
As shown in A, at least the DC of the DCT block in the VLC-compressed data obtained by compressing one DCT block during the sync code.
The coefficient and the quantization index are collectively recorded in a region different from the AC coefficient. In the figure, after the sync code, the DC coefficient and the quantization index are collectively recorded in units of DCT blocks.

The buffer memories 52 and 54 described above are VL
A RAM for reading data provided in the C circuit 20 can be used. An example thereof will be illustrated together with the VLC processing main body. In general, the VLC conversion process is to read the DC coefficient and the AC coefficient in zigzag from the DC coefficient side and convert the non-zero value and the number of zeros at that time into VLC using a predetermined table (see FIG. 4).

In the VLC circuit 20 shown in FIG. 3, the zero-run counter 62 counts the number of consecutive events in which the input data (quantization level) is zero. When the input data is a non-zero value, the synchronous clear is performed. To be done. Therefore, the input data output from the NOR circuit 61 is counted up, and the input data output from the OR circuit 63 is cleared. As a result, a two-dimensional event is formed by the “zero-run value” output from the zero-run counter 62 and the input data itself.

This two-dimensional event is stored in two ROMs 64 and 65.
The code length of the two-dimensional event is output from the code length ROM 64, and the code word of the two-dimensional event is output from the code word ROM 65 in a bit-filled manner. The code length data is input to the address generation circuit 66.

The address generator circuit 66 outputs the integrated value of the code length data as address data. As the address generation circuit 66, although not shown, an address accumulator circuit composed of an appropriate accumulator and simple logic can be used.

RAM 52, 54 according to address data
Address is controlled and barrel shifter 6
The shift amount of 7 is controlled. The barrel shifter 67 shifts the output codeword from the codeword ROM 65 so that the head of the current codeword is connected to the end of the immediately preceding codeword.

The RAMs 52 and 54 are used for read-modify-write. That is, the cueed current codeword and the RAM data at the address where the immediately preceding codeword is written are fed back and selected bit by bit. Therefore, the bit occupied by the immediately preceding code is switched to the feedback system side, and the other bits are switched to the codeword ROM 65 side. Thus, the current VLC in a form combined with the previous code
The data is written in the RAMs 52 and 54.

This process is repeated up to EOB and RA
The encoded bit stream is stored in the M52 and M54, and the output bit stream is obtained by sequentially reading the contents of the RAMs 52 and 54 later.

Since the code length ROM 64 and the codeword ROM 65 are supplied with a value indicating a DC coefficient and a quantization index in addition to a non-zero value, when the DC coefficient and the quantization index are input, they are set to that value. The switching pulse Pc is supplied to the pair of ROMs 64 and 65 in synchronization with the DC coefficient input timing so that the corresponding code length and code word are selected. A similar switching pulse Pc is also supplied to the address generation circuit 66.

An enable pulse for writing is supplied to the pair of data RAMs 52 and 54, and one of the RAMs 52 has the DC coefficient and the quantization index.
It is controlled so that the VLC data is written only in that area.

FIG. 5 shows a concrete example of the picture stamp video decoder 30 corresponding to FIG. The video decoder 30 is capable of reproducing the bit stream and displaying the main screen.

The reproduced bit stream is the terminal 30a.
Is supplied to the pair of buffer memories 75 and 76 via
The DC coefficient and the quantization index are stored in one buffer memory 75, and the AC coefficient is stored in the other buffer memory 7.
Stored in 6. Therefore, a control pulse related to the reproduced sync code is supplied to the terminal 30b, and the buffer memories 75 and 76 are switched by this.

The buffer memories 75 and 76 are switches 77.
Is supplied to the VLD circuit 34 while being switched by
D conversion (decoding) processing is performed. The quantization level obtained by decoding is returned to the DCT coefficient using the quantization index reproduced in the inverse quantization circuit 36. The DCT coefficient is supplied to the inverse DCT circuit 38 via the switch 78 and is inversely converted into frequency plane data. The inversely converted frequency plane data is returned to the sample plane data by the block / raster conversion circuit 39, and the input image is reproduced by supplying this data to the monitor.

The switches 77 and 78 have different control states when only the main screen is monitored and when the picture stamp is used. When the image is the main screen, the image cannot be reproduced unless the AC coefficient is used. Therefore, when this mode NP is selected, the switch 77 is alternately selected and DC is selected.
The coefficient and the AC coefficient are extracted respectively. DCT
It is necessary to perform the inverse transformation of the coefficient.

On the other hand, in the picture stamp PS mode, the DCT coefficient used is only the DC coefficient. In this case, the value obtained by dividing the inversely quantized DCT coefficient by an appropriate value is the DCT block. Since it is the average value of the pixel values, the block data may be returned to the raster data without performing the inverse DCT conversion process. D
A divider 79 is provided after the switch 78 to divide the CT coefficient by an appropriate value.

In this way, the picture stamp mode PS
Then, the switch 77 is switched to the position indicated by the solid line by the mode switching pulse supplied to the terminal 77a, and the switch 78
Is switched to the position shown by the broken line by a similar mode switching pulse supplied to the terminal 78a.

As described above, in the picture stamp mode, only the VLC-converted DC coefficient is taken out, so that high speed reproduction is possible. Since the picture stamp process can be realized by using the normal reproduction processing hardware, the hardware scale can be simplified.

FIG. 6 and subsequent figures are for explaining another embodiment of the present invention, and in the present example, they are applied to a bit reduction system which also performs motion compensation MC using the time axis direction. .

For intra pictures, compressed data can be formed by the same processing as in FIG. When a picture stamp is formed by using an inter picture, in addition to the motion vector and the DC coefficient, the bit stream of the current frame including the motion vector and the reproduced image processed previously are required. The child screen image is composed of only DC coefficients, whereas the motion vector is generated based on the image of the parent screen. Therefore, if this motion vector is used as it is for inter-picture composition, the resolution is It will deteriorate.

This will be described with reference to FIG. FIG.
The dots shown in are the sample points of the original pixel. In this example, the macroblock is the same as the DCT block,
Sample x 8 lines. Dotted lines indicate boundaries of macroblocks.

When the macroblock of the current frame is B3, it is assumed that this macroblock B3 is decoded.
It is assumed that a motion vector as shown is given.
In normal reproduction (parent screen), motion compensation is performed using reference pixels of a block (reference block) surrounded by a chain line centered at the start point of the vector shown in the figure.

In the case of a picture stamp, the DCT shown in the figure
Since the block is composed of one pixel (only DC coefficient), there is no pixel to be referenced and motion compensation cannot be performed.

Therefore, in this example, it is assumed that the picture of the picture stamp is arranged in the center of each DCT block (like "★" in the figure), and the motion compensation is performed using the assumed pixel closest to the motion vector. Should be done. For example, in the case of FIG. 5, the picture stamp pixel value of the macro block C2 including the assumed pixel included in the reference block may be used as the assumed pixel.

For that purpose, the coordinate value (x, y) of the vector starting point given as the motion vector information for the macroblock B3 is set to the reduction ratio (= 8) of the DCT block.
It can be corrected by As shown in the figure, the origin coordinate (x, y) of the motion vector is (10, 6) above and to the right of the coordinates of the end point of the motion vector, so (x, y) = (10/8, 6/8) The coordinate value corrected as = (1,1) is used as the motion vector for the picture stamp. By doing so, an inter-picture for a picture stamp can be configured by the motion vector corresponding to the reduced child screen. Such processing is performed by the picture stamp reproducing device (decoder side).

FIG. 7 is a system diagram showing one form of the video encoder 10 for realizing the above-mentioned (MC + DCT) processing.
Although the basic configuration shown in FIG. 1 is followed as it is, a motion compensation circuit 80, a motion vector detection circuit 86, and a changeover switch 82 are added to this basic configuration as shown in FIG. When the image to be compressed is an intra picture processed in a frame, the switch 82 is switched by the motion detection output as shown by the broken line, and the blocked block data is directly D
It is supplied to the CT conversion circuit 16.

On the other hand, in the case of inter picture, the switch 82 is switched to the solid line side. Then, a previously processed image is used as a reference image to obtain a motion vector for a macroblock composed of a plurality of DCT blocks of the current frame, and motion compensation is performed using this motion vector. The motion-compensated predicted image of the immediately preceding frame is supplied to the adder 84 to obtain the difference from the current frame, and the inter-frame difference signal is DCT-transformed.

The subsequent processing is the same as that of FIG. 1 and therefore omitted, but the motion vector (vector) detected by the motion vector detection circuit 86 is also supplied to the VLC circuit 20 and converted into VLC like the quantization level. To be done. In order to obtain the code length and the code word corresponding to this vector, the code length and the code word ROMs 64 and 65 shown in FIG.
Etc. are controlled. Therefore, the pulse Pc shown in FIG. 3 is a pulse showing the AC coefficient and the others (DC coefficient, quantization index, and vector).

FIG. 8 shows a concrete example of the video decoder 30. Although this video decoder 30 also has the basic configuration of FIG. 5, a motion compensation circuit 90, an adder 94, a motion vector correction circuit 98, and a pair of switches 92 and 96 are newly provided.

During normal reproduction, the switch 96 is switched to the normal mode NP side and the decoded motion vector is supplied to the motion compensation circuit 90. Motion compensation circuit 90
The reproduced image data whose motion has been compensated by is supplied to the adder 94 via the switch 92 and added to the image data of the inter-frame difference. The switch 92 is switched between inter picture and intra picture.

In the picture stamp mode PS, the motion vector correction circuit 96 operates to perform the above-mentioned correction processing. Since the corrected motion vector is supplied to the motion compensation circuit 90, the immediately preceding reproduced image data (picture stamp child screen image data) is generated using this corrected motion vector.

By the way, in the case of FIG. 6, the picture stamp pixel value itself of the macroblock C2 is used as the representative point pixel value.

However, according to this method, depending on the image, a fold-back may be seen due to the coarse precision of the motion vector. To deal with this, the pixel values of the picture stamps located near the motion vector may be appropriately weighted before use. By doing so, the pixel value C2 can be moved to the center (vector starting point) in the reference block indicated by the chain line, so that the image quality of the picture stamp can be improved accordingly.

For example, in the example of FIG. 6, not only the macroblock C2 but also the picture stamp pixel values present in the four macroblocks D2, C3 and D3 (PC2 in the above example).
PD2, PC3, PD3) are weighted and added according to the distance from the motion vector origin. That is, the closer to the starting point of the motion vector, the larger the weight, and the farther from the starting point, the smaller the weight. Specifically, the number of pixels included in the reference block is used. Therefore, the new pixel value C2 'for the picture stamp existing in the macroblock C2
C2 ′ = k1 × PC2 + k2 × PD2 + k3 × PC3 +, where the corresponding weighting factors are k1 to k4.
k4 × PD3 Here, k1 = (x / 8, y / 8) (36/64) k2 = (x / 8, y / 8) (12/64) k3 = (x / 8, y / 8) ( 12/64) k4 = (x / 8, y / 8) (4/64). The numerical value on the right side of the weighting factors is the weighting value.

A specific example for calculating the new pixel value C2 'is shown in FIG. The video decoder 30 shown in the figure is almost the same as that in FIG. 8, and the motion compensation circuit 90 is improved for weighting correction.

In the figure, there are four motion compensators 100 to 106, to each of which a motion vector before correction is supplied in common. From each of them, picture stamp pixel values (PC2, PD2, PC3, PD3 in the above example) in four macro blocks surrounding the motion vector are output. The pixel value for each picture stamp is a weighting multiplier 110.
Weighted correction is performed at 116. Weighting factor k
1 to k4 take different values depending on the distance between the pixel value and the motion vector starting point as described above.

The weighted pixel values are added in adder 120 and averaged. Averaged pixel value C
2'is added to the inter-frame difference image data via the switch 92.

By performing the decoding process on the basis of the pixel values corrected by using the surrounding pixel values in this way, it is possible to obtain the picture image for the picture stamp sub-screen.

Next, a modification of the present invention will be described.

In the above description, the picture stamp child picture in which the parent picture is compressed to ⅛ is assumed, but upsampling may be performed when a larger picture is desired.

In the above description of FIG. 6, it is assumed that the macroblock is composed of one DCT block.
A macro block composed of CT blocks may be used.

Although the DCT block is 8 pixels × 8 lines in the above description, this size may be larger or smaller than this.

In the above description, the number of picture stamp pixels to be weighted and added is four, but the number may be more or less than this.

In the above description, the image compression data (including the DC coefficient, the quantization index, and the vector) dedicated to the child screen necessary to form the picture stamp and the image compression data for the parent screen are recorded alternately. Only the image compressed data dedicated to the screen may be collectively recorded at a specific location. For example, in the case of tape media, it is recorded immediately after the sync code. If it is a disk medium, it is recorded by concentrating on a specific sector. By doing so, only the DC coefficient can be selectively reproduced, and the picture stamp can be easily reproduced. In this case, the hardware required is only the VLD dedicated to the DC component, the inverse quantizer, and the DCT block-raster scan converter (see FIG. 2). If the VLD has only the DC component, the hardware can be considerably simplified compared to the VLD having all the functions.

In the above description, the data obtained by converting the DC coefficient into VLC is recorded. A for the DCT coefficient
Since there is almost no correlation between the C coefficient and the DC coefficient, and the DC coefficient is statistically less biased, even if the DC coefficient is VLC, the data compression efficiency is not improved so much. Therefore, the quantization level of the DC coefficient may be recorded as it is in a binary form at the above-mentioned specific location without being VLC converted. In this way, the picture stamp can be reproduced more easily, although the efficiency is slightly reduced.

[0069]

As described above, according to the present invention, the compressed image data dedicated to the child screen is recorded in a place different from the other image data, and the image data is reproduced mainly during reproduction. The picture stamp is configured by.

According to this, since the image data dedicated to the small screen can be reproduced at high speed with a small hardware scale, the picture stamp can be easily obtained at high speed.

According to the present invention, the DC coefficient, the motion vector, the quantization index, etc. are used as the image data information dedicated to the child screen even in the compression using the time direction, even in the image in which the inter picture and the intra picture are mixed. By recording separately, high-speed reproduction becomes possible and a picture stamp can be obtained quickly.

Since the compressed image data dedicated to the child screen is also used as the image data for reproducing the parent screen, it is not necessary to secure a special data area.

By appropriately weighting and adding the signals of the reference image based on the motion vector, a high quality image can be obtained even in the small screen. Therefore, the present invention is extremely suitable when applied to an editing apparatus using a picture stamp.

[Brief description of drawings]

FIG. 1 is a system diagram of a main part showing an embodiment of a video encoder for a picture stamp according to the present invention.

FIG. 2 is a diagram showing a recording pattern on a tape.

FIG. 3 is a system diagram of a VLC circuit.

FIG. 4 is a diagram showing an example of a VLC table.

FIG. 5 is a system diagram of essential parts showing one form of a video decoder for picture stamps.

FIG. 6 is an explanatory diagram of motion vectors.

FIG. 7 is a system diagram of essential parts showing another embodiment of the video encoder for picture stamps according to the present invention.

FIG. 8 is a system diagram of an essential part showing another form of a video decoder for picture stamps.

[Fig. 9] Fig. 9 is a system diagram of essential parts showing another form of a video decoder for picture stamps.

FIG. 10 is a system diagram of a video encoder.

FIG. 11 is a system diagram of a video decoder.

FIG. 12 is a system diagram of a conventional picture stamp reproducing device.

FIG. 13 is an explanatory diagram of a picture stamp.

[Explanation of symbols]

 10 Encoder 14 Blocking Circuit 16 DCT Circuit 18 Quantization Circuit 20 VLC Circuit 30 Decoder 34 VLD Circuit 36 Inverse Quantization Circuit 38 Inverse DCT Circuit 39 Block / Raster Conversion Circuit 52, 54 Buffer Memory 90 Motion Vector Compensation Circuit 98 Motion Vector Correction Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 5/765 H04N 5/781 510D 5/781

Claims (5)

[Claims] 1. An image compression apparatus using a bit reduction method, wherein image compression data dedicated to a sub-picture and quantization index necessary for reducing a main picture to form a picture stamp consisting of a low-resolution sub-picture, An image compression apparatus for a picture stamp, which is recorded separately from the compressed image data for the main screen. 2. The image compression apparatus for a picture stamp according to claim 1, wherein the image compression is an image compression using orthogonal transformation such as DCT transformation as a bit reduction method. 3. The compressed image data dedicated to the child screen is used as a bit stream as it is, or a variable length coded version of the quantization level is used as a bit stream. The image compression device for the picture stamp described. 4. A blocking means for dividing input image data constituting a main screen into blocks each having a predetermined size, and D for DCT-transforming the blocked input image data.
CT transforming means, quantizing means for quantizing DCT transformed DCT coefficients, variable length coding means for variable length coding the quantized quantization level, and variable length coding quantization level Of these, a pair of memory means for separately storing a variable length code corresponding to the DC coefficient and another variable length code, and a recording means for recording the variable length code corresponding to the DC coefficient at a specific location An image compression apparatus for a picture stamp according to claim 1, wherein: 5. When the motion vector is compressed together with the compressed data of the input image, the motion vector is recorded together with the compressed image data for the small screen necessary for reproducing the small screen. The image compression device for a picture stamp according to claim 1.