RU2079208C1 - Interface device for connection of user communication line to telephone exchange system - Google Patents

Abstract

FIELD: communication devices. SUBSTANCE: device has first, second and third buffer units 1, 2, 8, first, second, third, fourth and fifth flip-flops 3, 4, 5, 6, 7, inverter 9 and OR gate 10. EFFECT: increased reliability of connection. 4 dwg, 1 tbl

Description

 The invention relates to communication technology, in particular to telephone exchange systems for communicating a subscriber line with a processor.

 A device for interfacing with a subscriber line in telephone communication systems, containing five triggers, elements And and elements AND.

 However, the known device has low reliability of the subscriber line.

 EFFECT: increased reliability of communication between a subscriber line and a processor.

 In FIG. 1 is a block diagram of a subscriber line coupler in telephone exchange systems; in FIG. 2 of the waveform shown in FIG. 1 device; in FIG. 3 is a circuit diagram of a device for interfacing with a subscriber communication line in telephone systems; in FIG. 4 are timing diagrams explaining the operation of the subscriber line coupler of FIG. 3.

 The device of FIG. 1 contains a pairing unit 1, a subscriber line call generator 2, a relay 3, a subscriber's telephone 4, a call on / off unit 5, a voltage reference 6, a subscriber line coupler 7, a resistor R, a capacitor C. Block 1 contains a differential amplifier 8 AND 9 elements, current sensor 10. The subscriber line coupler 7 comprises first and second buffer blocks 1, 2, first, second, third, fourth and fifth triggers 3 7, a third buffer block 8, an inverter 9, an OR element 10 .

от процессора и поступают на блок 1 сопряжения абонентской линии. Сигналы выделения контроля абонента

также поступают на блок 1. Сигнал выделения

получается следующим образом. Переменный сигнал вызова около 110 В (75 В • 2) от генератора 2 вызова добавляется к постоянному напряжению величиной 48 В, уровень фиг. 2А3, как показано на фиг. 2А, в результате чего получается сигнал с формой фиг. 2А1. Таким образом, становится видным, что сигнал вызова имеет форму синуса, меняющуюся от 62 В до 156 В /уровни фиг. 2А, А4/.According to FIG. 1 and FIG. 2-4 C1-C4 data from the processor output is synchronized with the write signal

from the processor and enter block 1 pairing subscriber line. Subscriber control allocation signals

also arrive at block 1. Highlight signal

obtained as follows. An alternating ringing signal of about 110 V (75 V • 2) from the ring generator 2 is added to a constant voltage of 48 V, the level of FIG. 2A3, as shown in FIG. 2A, resulting in a signal with the shape of FIG. 2A1. Thus, it becomes apparent that the call signal has a sine shape, varying from 62 V to 156 V / levels of FIG. 2A, A4 /.

 The call signal is received on the telephone 4 of the subscriber through the power resistor R when the mechanical relay 3 is turned on to connect the contact points under the control of the processor. However, if the call signal of the type of FIG. 2A1 passes through the relay 3 to the subscriber, a high voltage is applied to the two contact points, which leads to the destruction of the relay 3. Therefore, the connection of the contact points of the relay 3 is synchronized with the zero crossing signal ZC, such as the signal of FIG. 2 A5, resulting in a low voltage applied to the contact points.

 The output of the call generator 2 is connected to the call on / off unit 5 to isolate the call signal. Unit 1 usually emits a direct current from a 48 V power supply to the subscriber to control the connection on / off mode, and if a call signal arrives, the current from unit 1 is turned off. Thus, when the call signal is generated, the call on / off unit 5 generates a call signal, the call on / off unit 5 generates a connection on / off signal depending on the position of the lever switching. Namely, when the call signal is generated, the call on / off unit 5 generates a signal of about 20 MV relative to the ground, as shown in FIG. 2B, or a value of 2.3 V, as shown in FIG. 2B, whereby the ringing signal displays the connection on or off mode, respectively.

. Сопряжение между блоком 1 и процессором далее будет описано с использованием сигнала выделения

и сигнала пересечения нуля ZC.Then, the differential amplifier of unit 1 amplifies the difference between the outputs of the call on / off unit 5 and the reference voltage source 6 to determine the state of the lever switch during the call. In this case, if the reference voltage is set to about 1.8 V, the differential amplifier generates a "high" signal when the mode is on and a "low" signal when it is on. The "low" signal passes through the And element to the processor and the interface device 7, as an allocation signal

. The pairing between block 1 and the processor will now be described using an allocation signal

and a zero crossing signal ZC.

, сигнала выделения

, сигнала пересечения нуля ZC и сигнала прерывания

. Четыре триггера 1, 2, 3, 4 F1, F2, F3, F4 запоминают соответственно первый -четвертый потоки данных C2-C4 в ответ на сигнал записи

как сигнал синхронизации и устанавливаются в исходное состояние с помощью сигнала прерывания

.According to FIG. 3, the first buffer block 1 contains four buffers B1-B4 for accumulating four data streams C2-C4 produced by the processor. The second buffer unit 2 also contains four buffers B5-B8 for accumulating the write signal

selection signal

, ZC zero crossing signal and interrupt signal

. Four flip-flops 1, 2, 3, 4 F1, F2, F3, F4 store respectively the first and fourth data streams C2-C4 in response to the write signal

as a synchronization signal and are reset using an interrupt signal

.

. Третий буферный блок 8 содержит четыре буфера B9 B12 для накопления выходов от первого, третьего, четвертого и пятого триггеров 1, 3, 4, 5 FF1, FF3 FF5 для передачи сигналов на блок 1.The highlight signal DET is inverted using an inverter 9NG, whose output and output of the second trigger 2 FF2 are logically combined by the OR 10 OG element to generate a second data stream together with the auto call on / off signal. The fifth trigger 5 FF5 receives the output from the OR 10 OG element to hold the second data stream C2 and the auto-call on / off signal in response to the zero crossing signal as a synchronization signal and is reset by the interrupt signal

. The third buffer block 8 contains four buffers B9 B12 for accumulating outputs from the first, third, fourth and fifth triggers 1, 3, 4, 5 FF1, FF3 FF5 for transmitting signals to block 1.

, как показано на фиг. 4G. Затем первый, третий и четвертый триггеры 1, 3, 4, 5 FF1, FF3 и FF4 соответственно обеспечивают через буферы B9, B11, B12 первый, третий и четвертый выходные потоки данных OC1, OC3 и OC4, как показано на фиг. 4Н, J и K, для снабжения этими данными OC1, OC3 и OC4 блок 1.According to FIG. 4A-K, first to fourth data streams C1 C4 from the processor, as shown in FIG. 4B-E, respectively, through buffers B1 B4 to triggers 1 4 FF1 FF4, to hold the first to fourth data stream C2 C4 in response to the write signal

as shown in FIG. 4G. Then, the first, third and fourth triggers 1, 3, 4, 5 FF1, FF3 and FF4 respectively provide, through buffers B9, B11, B12, the first, third and fourth output data streams OC1, OC3 and OC4, as shown in FIG. 4H, J and K, for supplying this data to OC1, OC3 and OC4 block 1.

, получаемый от блока 1, как показано на фиг. 4, поступает через буфер B6 на инвертор 9NG. В этом случае сигнал выделения

с "низким" уровнем, как показано на фиг. 4, инвертируется инвертором 9NG в сигнал с "высоким" уровнем, приложенный к другому входу элемента ИЛИ 10.The second data stream C2 of the second trigger 2FF2 is fed to one input of the OR 10 OG element. When the connection setup is turned off and a call signal is generated, the highlight signal

obtained from block 1, as shown in FIG. 4, enters through the buffer B6 to the inverter 9NG. In this case, the highlight signal

low level as shown in FIG. 4, is inverted by the 9NG inverter to a “high” level signal applied to another input of the OR element 10.

 The OR 10 OG element logically combines the outputs of the second trigger 2FF2 and the inverter 9NG to obtain a "high" signal if the second data stream C2 is "high" level or an on / off call occurs. The fifth trigger 5 receives the output from the OR element 10 OG to hold the second data stream C2 or the on-off signal of the auto call in response to the zero crossing signal ZC, as a synchronization signal generated as shown in FIG. 4 F, D, whenever it switches relative to earth voltage. FF5 trigger 5 is a level trigger latch that serves to reliably generate an auto-on / off signal even if a zero-crossing signal generation C stops. The output of the fifth FF5 trigger 5 is connected via buffer B10 to block 1, as a second OC2 output stream and how it shown in FIG. 4J.

 The operation of the device is tabulated.

In the table D _cx (x = 1, 2, 3, 4) the output data, Qd _cx (x = 1, 3, 3, 4) the output data, as well as the input data, and Qo _cx (x = 1, 2, 3, 4) the output of the previous state.

Claims (1)

A subscriber line coupler in telephone exchange systems comprising first, second, third, fourth and fifth triggers, the PR inputs of which are connected and are the DC voltage inputs of the device, the reset input CLR of the first trigger connected to the reset inputs CLR of the second, third, fourth and a fifth trigger, characterized in that the first, second and third buffer blocks, an inverter and an OR element are introduced, the output of which is connected to the information D input of the fifth trigger, with the first, second, third and fourth the outputs of the first buffer block are connected to the information D inputs of the first, third, fourth triggers, respectively, with the direct output Q of the second trigger connected to the first input of the OR element, to the second input of which the second output of the second buffer block is connected through the inverter, the third and fourth outputs of which are connected respectively, to the input of the SC record and to the reset input of the CLR of the fifth trigger, whose direct output Q, as well as the direct outputs Q of the first and third triggers and the inverse output

the fourth trigger are connected respectively to the fourth, first, second and third inputs of the third buffer block, the first, second, third and fourth outputs of which are respectively the first OS1, second OS2, third OS3 and fourth OS4 device outputs, first C1, second C2, third C3 and the fourth C4 inputs of which are the first, second, third and fourth inputs of the first buffer block, respectively, and the first, second, third and fourth inputs of the second buffer block are respectively the input

recording, signal isolation input

signal input ZС intersection O and signal input

device interruption.

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