KR890010661A - Current loop interface circuit - Google Patents

Current loop interface circuit Download PDF

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Publication number
KR890010661A
KR890010661A KR870014175A KR870014175A KR890010661A KR 890010661 A KR890010661 A KR 890010661A KR 870014175 A KR870014175 A KR 870014175A KR 870014175 A KR870014175 A KR 870014175A KR 890010661 A KR890010661 A KR 890010661A
Authority
KR
South Korea
Prior art keywords
current loop
signal
time switch
converting
host computer
Prior art date
Application number
KR870014175A
Other languages
Korean (ko)
Other versions
KR910000300B1 (en
Inventor
이동현
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870014175A priority Critical patent/KR910000300B1/en
Publication of KR890010661A publication Critical patent/KR890010661A/en
Application granted granted Critical
Publication of KR910000300B1 publication Critical patent/KR910000300B1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

내용 없음No content

Description

전류 루우프 인터페이스 회로Current loop interface circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 호스트 컴퓨터의 전류 루우프 포트와 전류 루우프 방식 터미날의 접속 구성도.2 is a connection configuration diagram of a current loop port and a current loop terminal of a host computer according to the present invention.

제3도는 본 발명에 따른 제2도의 전류 루우프 호스트 인터페이스 회로의 구체회로도.3 is a concrete circuit diagram of the current loop host interface circuit of FIG. 2 according to the present invention.

제4도는 본 발명에 따른 제2도의 전류 루우프 호스트 인터페이스 회로의 구체회로도.4 is a concrete circuit diagram of the current loop host interface circuit of FIG. 2 according to the present invention.

Claims (1)

호스트 컴퓨터(10) 및 터미날(60-62)와 콘트롤러(30) 및 타임스위치(40)의 교환기(100)을 구비한 시스템의 상기 호스트 컴퓨터(10)의 전류 루우프 호스트 인터페이스와 터미날(60-62)의 전류 루우프 터미날 인터페이스 회로에 있어서,상기 호스트 컴퓨터(10)의 전류 루우프 포트에서 나오는 신호를 TTL레벨의 신호로 변환하여 상기 타임스위치(40)의 하이웨이로 보내주는 제1수단과, 상기 타임스위치(40)의 하이웨이에서 들어오는 TTL레벨의 신호를 소정의 전류 루우프 신호로 변환하여 상기 호스트 컴퓨터(10)의 전류 루우프 포트로 보내주는 제2수단과, 상기 터미날(60-62)의 전류 루우프 터미날에서 나오는 신호를 TTL레벨로 변환하여 타임스위치(40)로 보내주는 제3수단과, 상기 타임스위치(40)의 TTL레벨의 신호를 소정의 전류 루우프신호로 변환하여 전류 루우프 터미날(60-62)로 보내주는 제4수단과, 상기 터미날(60-62)의 전원이 온/오프의 상태를 체크하여 상기 터미날(60-62) 동작 여부 상태를 알 수 있도록 하는 제5수단으로 구성됨을 특징으로 하는 회로.Current loop host interface and terminal (60-62) of the host computer (10) of the system having a host computer (10) and terminals (60-62) and a switch (100) of the controller (30) and the time switch (40). In the current loop terminal interface circuit of the present invention, First means for converting the signal from the current loop port of the host computer 10 to a signal of the TTL level and to send to the highway of the time switch 40, and the time switch Second means for converting a signal of the TTL level coming from the highway of (40) into a predetermined current loop signal and sending it to the current loop port of the host computer (10); Third means for converting the outgoing signal to the TTL level and sending it to the time switch 40, and converting the TTL level signal of the time switch 40 into a predetermined current loop signal to make the current loop terminal. Fourth means for sending to 60-62 and fifth means for checking whether the power of the terminals 60-62 is on / off to determine whether the terminals 60-62 are in operation or not. Circuit configured. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870014175A 1987-12-11 1987-12-11 Current loop interface circuit KR910000300B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870014175A KR910000300B1 (en) 1987-12-11 1987-12-11 Current loop interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870014175A KR910000300B1 (en) 1987-12-11 1987-12-11 Current loop interface circuit

Publications (2)

Publication Number Publication Date
KR890010661A true KR890010661A (en) 1989-08-10
KR910000300B1 KR910000300B1 (en) 1991-01-24

Family

ID=19266870

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870014175A KR910000300B1 (en) 1987-12-11 1987-12-11 Current loop interface circuit

Country Status (1)

Country Link
KR (1) KR910000300B1 (en)

Also Published As

Publication number Publication date
KR910000300B1 (en) 1991-01-24

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