RU2068617C1 - Multilevel binary transversal filter - Google Patents

Abstract

FIELD: communications engineering; television, data processing devices. SUBSTANCE: device has inputs 1₁ ... 1_n, bits 2₁₁ ... 2_nm of shift register, AND gates 3₁₁ ... 3_nm, EXCLUSIVE OR gates 4₁₁ ... 4_nm, shaping buffers 5₁₁ ... 5_nm bits of character registers 6₁ ... 6_n and of factor modules 10₁₁ ... 10_nm, groups of capacitors 7₁₁ ... 7_nm, controlled switches 8₁₁ ... 8_nm and 9. EFFECT: enlarged functional capabilities due to programming weight factors and provision for two-dimensional filtering. 2 cl, 3 dwg

Description

 The invention relates to techniques for communications, can be used in television, in image processing devices.

 The purpose of the invention is the expansion of functionality by programming the values of weights and providing two-dimensional filtering.

 In FIG. 1 is an electrical block diagram of a binary multilevel transverse filter, and FIGS. 2 and 3 are timing diagrams explaining its operation.

The binary multilevel transverse filter contains information inputs 1.1.1.n, bits 2 ₁₁ .2 _{nm of} shift registers, elements of AND 3 ₁₁ .3 _nm groups, elements of EXCLUSIVE OR 4 ₁₁ .4 _nm groups, buffer-shapers 5 ₁₁ .5 _nm groups, register bits 6 ₁ .6 _m signs of the coefficients, capacitor groups 7 ₁₁ .7 _nm , containing capacitors 7 ₁₁₁ .7 _11n , managed keys 8 ₁₁ .8 _nm groups, managed key 9, register bits 10 ₁₁ .10 _nm of coefficient modules converter November 2 ⁿ -level digital code in the n-bit binary code to an analog repeater 12, an optional controllable key 13, a condenser 14, filter 15 is a lowpass.

 The proposed device can be made in the form of BI according to standard CMOS technology. Typical circuitry solutions based on CMOS transistors can be used as registers, logical elements "AND", "EXCLUSIVE OR", a managed key and a shaper buffer.

 As the dielectrics of capacitors, a gate dielectric of transistors can be used.

As a converter 2 of an ^n- level digital code to an n-bit binary code, an n-bit analog-to-digital converter can be used.

 Technical implementation of a low-pass filter is possible, for example, based on an operational amplifier. Analog repeaters can be performed, for example, on MOS transistors or on operational amplifiers with MIS transistors at the input.

The operation of the proposed device is illustrated by diagrams of figure 2, 3. The bits of the binary code of the information signal are fed to the information inputs 1 ₁ -1 _n (Fig. 2A). Along the fronts of the clock pulses, the information signal moves along the bits 2 _{ij of the} shift registers (Fig.2b). From the output of each bit 2 _{ij of the} register, the signal is supplied to the logic element 3 _ij "And", in which it is gated by the clock pulses arriving at Input 1 sync. (figv). Depending on the state of the discharge of register 6 _{j, the} signal from the output of element 3 _ij AND (Fig. 2d) is inverted or passed directly through the logic element 4 _ij EXCLUSIVE OR to the input of the shaper buffer 5 _ij (Fig.2d). The shaper buffer 5 _ij charges the first plates of the group of capacitors 7 _ij to the constant voltage level of the power source with a logical unit at the input of the buffer or discharges to level 0 with a logical zero at the input of the buffer. Depending on the logical states previously set in the bits of the register 10 _ij , the output signal of the shaper buffer 5 _ij through capacitors 7 _ijr and public keys 8 _ij is transmitted to the information output Output 1 inf. At the time of arrival of the clock on Input 2 sync. (figa) opens the key 9 and at the output 1 inf. set the level corresponding to the bias voltage U _cm supplied to the input bias. At time instants corresponding to clock pulses at Input 1, sync. At the exit 1 inf. set the level corresponding to the sum of the weighted signals from the bits of the register 2 _ij (figb).

As an example illustrating the operation of the device, we took the filter weighing coefficients equal to W ₁₁ 1, W ₁₂ -2, W ₁₃ 5, for i> 1, j> 3, W _ij 0. 2 ^n- level signal generated at the Output 1 inf. device with these values of the coefficients shown in figb.

Binary digital signal generated at Outputs 2 ₁ inf. 2 _n inf. at the same values of the coefficients, and the analog signal generated at Output 3 inf. shown in Fig. 3d.

Claims (2)

1. Binary multilevel transverse filter containing n m-bit shift registers, the inputs of which are information inputs of the device, m groups of n elements AND in each group, m groups of n shapers buffers in each group and a managed key, input and output which is the bias input and the output of the binary multilevel transverse filter, respectively, the first and second synchronization inputs of which are the first inputs of AND elements and the control input of the managed key, respectively, the output j- discharge of i-th shift register, wherein

connected to the second input of the i-th element And the j-th group, characterized in that, in order to expand the functionality by providing the possibility of programming the values of the weight coefficients, an m-bit register of signs of the coefficients and n m-bit register of coefficient modules, inputs which are the first and second inputs of programming a binary multilevel transverse filter, respectively, as well as m groups of n EXCLUSIVE OR elements in each, n • m groups of capacitors and m groups of n managed keys in each group, and the output of the i-th element AND of the j-group is connected through the i-th element EXCLUSIVE OR of the j-th group to the input of the i-th shaper buffer of the j-th group, the output of which is connected to the first capacitor plates of the ij-th group, the number of which l _i in the ij-th group, regardless of the value of j, is determined from the relation

and the second lining of the same capacitors of the groups with the same number j is connected to the input of the i-th managed key of the j-th group, the control input of which is connected to the output from the ij-th category of the register of coefficient modules, the outputs of all controlled keys of the groups are connected to the output of the controlled key, and the second inputs of all elements EXCLUSIVE OR of the j-th group are connected to the output of the j-th digit of the register of coefficient signs.  2. The filter according to claim 1, characterized in that, in order to enable two-dimensional filtering in the window of m • k elements, k-1 additional binary-level programmable transverse filters are introduced, the outputs of which are interconnected.

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