RU2060537C1 - Device for calculation of disjunctive logical determinant - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has input and output units, which corresponding inputs and outputs are connected to input and output lines of device. In addition device has adder, units for calculation of disjunction, which number equals to number of lines in logical determinant minus one, and synchronization pulse oscillator 2. Device may be used for calculating schedules of operation in conveyor systems. EFFECT: increased field of application. 2 cl, 8 dwg, 2 tbl

Description

 The invention relates to computer technology and can mainly be used for scheduling deterministic conveyor-type systems.

 Known devices for calculating the disjunctive logical determinant (DLO), used both for multiprogramming computing tools and scheduling in wide areas of the national economy (transport, manufacturing processes, educational process, etc.).

 The device contains RAM, a processor, and external devices for inputting and outputting information. The calculation of DLO occurs according to a program compiled on the basis of the algorithm.

 This device due to the solution of a fairly wide range of tasks is expensive, which limits the scope of its application in various areas of the national economy.

 The closest in technical essence to the invention is a computer containing an input bus connected to the first input of the unit, the output of which is connected to a memory input, one output of which is connected to the input of the processor, and the other to the first input of the output unit, the output of which is connected to the output bus of the computer , and the second input with the first processor output, the other two outputs of which are connected respectively to the second input input of block 1 and to the memory input 3.

 The disadvantage of using a computer to calculate the DLO is its complexity, low reliability, the need for a program, and therefore high cost, high operating costs. The list of these factors limits the use of computers for compiling, for example, schedules of conveyor-type systems used in the broadest areas of the national economy and military affairs. Scheduling is carried out by calculating the DLO.

 The aim of the invention is to expand the scope of the device by simplifying it.

 This is achieved by the fact that in the device containing the synchronization unit, accumulating the adder, an input unit, consisting of m, n-bit parallel registers (where m is the number of lines of the disjunctive logical determinant, n-bit capacity of the input numbers), m groups of elements And n elements And in each and n OR elements, (m-1) disjunction calculation blocks and an output block, the output of which is connected to the output of the device, m information inputs of which are connected respectively to the information outputs of m parallel registers of the input block, each of the blocks Disjunction tracking consists of a node for calculating the maximum number and two adders, the first and second outputs of the synchronization block being connected respectively to the combined synchronization inputs and the combined zero inputs of m parallel registers of the input block, the output of the ith bit of the jth register of the input block (where i 1, n, j 1, m) is connected to the first input of the i-th element AND of the j-th group of the input block, the output of which is connected to the corresponding input of the th element OR of the input block, the j-th output of the synchronization block, starting from the third output connected to by combined second inputs of AND elements of the jth group, the outputs of all OR elements of the input unit are connected to the information input of the accumulating adder and the first and second information inputs of each of (m-1) disjunction calculation blocks, the output of the accumulating adder is connected to the third information input of the first calculation block disjunction, the output of the l-th block of the calculation of the disjunction (l 1, m-2) is connected to the third information input of the (l + 1) -th block of the calculation of the disjunction, the output of the (m-1) -th block of the calculation of disjunction is connected to the information input ohm of the output block, the (m + 3) -th output of the synchronization block is connected to the combined input of the first adders (m-1) of the disjunction calculation blocks to zero, the input and output enable inputs of the first adder of the k-th disjunction calculation block (k 1, m-1) are connected respectively to the (k + m + 3) -th output and the (k + 2m + 2) -th output of the synchronization block, (3m + 2) -th output of which is connected to the combined zero inputs of the second adders ( m-1) disjunction calculation blocks.

 The input and output enable inputs of the second adder of the k-th disjunction calculation unit are connected respectively to the (k + 3m + 2) -th output and (k + 4m + 1) -th output of the synchronization unit, the first and second control inputs of the maximum number calculation unit k-th block of the disjunction calculation are connected respectively to the (k + 5m) -th output and the (k + 6m-1) -th output of the synchronization block, (7m-1) -th output of which is connected to the third control input of the node for calculating the maximum number of each disjunction calculation unit, the (7m) th, (7m + 1) th and (7m + 2) th outputs of the synchronization block are connected to responsibly setting to zero inputs, permits the input and output data of the accumulator. The triggering, synchronizing and zeroing inputs of the synchronization block are connected respectively to the triggering, synchronizing and zeroing input of a device whose data request output is connected to the (7m + 3) -th output of the synchronization block, whose (7m + 4) -th output is connected with synchronization input output block. The synchronization block contains a master oscillator, a binary counter, a trigger, an AND element, three OR elements, a group of AND elements and a memory element, (7m + 5) -th output of which is connected to the first inputs of the second and third OR elements, (7m + 4) - the ith output of the memory element is connected to the (7m + 4) -th output of the block, the (7m + 3) -th output of which is connected to the (7m + 3) -th output of the memory element and the second input of the second OR element, the first input of which is connected to the third the input of the block and the second input of the third OR element, and the output with the installation input at zero trigger, the information input of which connected to the output of the first OR element, the first and second inputs of which are connected respectively to the first and second inputs of the block, the direct output of the trigger is connected to the first input of the element And and the first inputs of the elements AND groups, the second inputs of which are connected to the corresponding outputs of the binary counter, the installation input to the zero and information input of which are connected respectively to the outputs of the third OR element and the And element, the second input of which is connected to the output of the master oscillator, the outputs of the elements AND groups are connected to the corresponding yuschimi memory element address inputs, the outputs of the first through (7m + 2) -th is connected respectively to the outputs of the first through (7m + 2) -th block.

 Thanks to new distinctive features, the proposed device becomes much simpler, which reduces its cost and increases reliability. Due to the narrow specialization of the device when using the same frequency of the master oscillator, it has a higher speed. This allows you to use the device in various sectors of the economy.

 Figure 1 presents the program for calculating the DLO; figure 2 is a block diagram of a device; in FIG. 3 diagram of the input block; figure 4 circuit block synchronization (BS); 5 is a block diagram of a disjunction calculation unit; 6 is a diagram of a node for calculating the maximum number (UMHF); 7 is a fragment of a diagram of a device for calculating DLO with the number of lines m 3; on Fig time diagrams of the operation of the device for the case m 3.

 Table 1 shows the purpose of the input and output lines of the BS (to complement Fig. 2 and Fig. 7) for m 3; in table 2, the device performs the functions for each clock pulse (see also Figs. 2,7,8) when m 3.

 The numbering of the inputs and outputs of the elements of the device (figure 2 and figure 7) is given for m 3.

 The device (see Fig. 2) contains an input unit 1 (Fig. 3), BS 2 (Fig. 4), an accumulating adder 3, disjunction calculation blocks 4 (Fig. 5,6), an output unit 5. As parallel registers input unit and maximum number selection circuits, K155IR1 microcircuits can be used. The adder is cumulative. The BS memory element can be implemented, for example, on K155RE3 microcircuits.

 The BS binary counter can be implemented on K155IE7 microchips, the comparator on K555SP1 microchips. As the BS master oscillator, the K531GG1 microcircuit can be used. The AND, OR elements and triggers can also be implemented on microcircuits, for example, K155 series.

 The device operates as follows.

). После ввода всех r столбцов получаем искомый результат A $\genfrac{}{}{0ex}{}{\text{v}}{\text{mr}}$ ДЛО.The principle of operation of the proposed device is based not on the wave algorithm, which would require the preliminary introduction of all numbers of the DLO matrix, but on the sequential input of matrix columns into the device. In this case, after entering the numbers of each column, the value A is calculated $\genfrac{}{}{0ex}{}{\text{v}}{\text{ml}}$ , where m is the number of numbers in the column (DLO rows), and l is the current column number (l

) After entering all r columns, we obtain the desired result A $\genfrac{}{}{0ex}{}{\text{v}}{\text{mr}}$ DLO.

 For convenience, understanding the operation of the device (figure 2) it is proposed to consider it for the case when the number of lines of the DLO is three (m 3).

Before starting the operation of the device, input 19 (see Fig. 2, 4, 8) is supplied with a signal for setting the trigger and the BS binary counter to the zero state. Then, input 16 is supplied with a signal for initial startup of the BS. The first clock pulse of the master oscillator determines the reading of information from the first multi-bit cell of the memory element. In this cell, as in others, the pre-recorded information will allow you to receive signals on the corresponding output lines of the memory element (see Fig. 8) (for a list of the functions performed, depending on the number of the clock pulse, see Table 2). After entering the last r-th column of the DLO and performing the corresponding operations on it, for example, similar from the 10th to the 16th clock pulse (see Fig. 8 and Table 2), a signal is sent from the memory element to 17, 24 ( see Fig. 2.7) output lines, as well as at the first inputs of the third and second elements OR BS (see Fig. 4). As a result, this is the desired value of A $\genfrac{}{}{0ex}{}{\text{3}}{\text{rv}}$ from adder 8 _{1 of the} second clause calculation block 4 is transferred to output block 5 (for example, to a parallel register), the trigger and BS counter are set to zero, operation stops.

 In the memory element must first be written to the corresponding addresses that coincide with the numbers of clock pulses, the information presented in Fig. 8.

 In the elements of the device (figure 2) connected by inputs and outputs to the data bus to reduce the current load on this bus, buffer registers with three states can be used. In this case, the bit width of the cells of the memory element, respectively, should increase to gate these registers.

 Thus, the proposed device differs from the prototype in simplicity, which gives it greater reliability and lower cost.

Claims (2)

 1. A device for computing a disjunctive logical determinant, comprising a synchronization unit, accumulating an adder, an input unit consisting of m n-bit parallel registers (where m is the number of lines of the disjunctive logical determinant, n-bit depth of the input numbers), m groups of elements And n elements And in each and n elements OR, m-1 blocks of disjunction calculation, an output block, the output of which is connected to the output of the device, m information inputs of which are connected respectively to the information inputs of m parallel registers input, characterized in that each of the disjunction calculation blocks consists of a node for calculating the maximum number and two adders, the first and second outputs of the synchronization block being connected respectively to the combined synchronization inputs and the combined installation inputs of “0” m parallel registers of the input block, output of the i-th category of the j-th register of the input block (where i = 1, n, j = 1, m) is connected to the first input of the i-th element And of the j-th group of the input block, the output of which is connected to the corresponding input of the j-th element OR input block, jth output of syn block starting from the third output, it is connected to the combined second inputs of AND elements of the jth group, the outputs of all OR elements of the input unit are connected to the information input of the accumulating adder and the first and second information inputs of each of m-1 disjunction calculation blocks, the output of the accumulating adder is connected with the third information input of the first block of the calculation of the disjunction, the output of the l-th block of the calculation of the disjunction (l = 1, m-2) with the third information input of the (l + 1) -th block of the calculation of the disjunction, output of the (m-1) -th block of calculation diz functions with the information input of the output unit, the (m + 3) -th output of the synchronization unit with the combined inputs of the “0” setting of the first adders m-1 of the disjunction calculation unit, the input and output enable inputs of the first adder of the k-th disjunction calculation unit (k = 1, m-1) are connected respectively to the (k + m + 3) -th and (k + 2m + 2) -th outputs of the synchronization block, the (3m + 2) -th output of which is connected to the combined inputs of the installation in "0 "second adders m-1 block disjunction calculation, inputs of input and output data of the second adder of the k-th block disjunction calculation connected respectively to the (k + 3m + 2) -th and (k + 4m + 1) -th outputs of the synchronization block, the first and second control inputs of the node for calculating the maximum number of the k-th block of the disjunction calculation are connected respectively to (k + 5m) - m and (k + 6m-1) -th outputs of the synchronization unit, the (7m-1) -th output of which is connected to the third control input of the node for calculating the maximum number of each disjunction calculation unit, 7m-th, (7m + 1) -th and (7m + 2) -th outputs of the synchronization unit are connected respectively to the inputs of the setting to "0", permissions to input and output data of the accumulating adder, inputs start, synchronize and set to “0” the synchronization unit is connected respectively to the inputs of the same device whose data request output is connected to the (7m + 3) -th output of the synchronization unit, (7m + 4) -th output of which is connected to the synchronization input of the output unit .  2. The device according to claim 1, characterized in that the synchronization unit contains a master oscillator, a binary counter, a trigger, an AND element, three OR elements, a group of AND elements, and a memory element, (7m + 5) -th output of which is connected to the first inputs the second and third elements OR, (7m + 4) -th output of the memory element with (7m + 4) -th output of the block, (7m + 3) -th output of which is connected to the (7m + 3) -th output of the memory element and the second the input of the second OR element, the first input of which is connected to the third input of the block and the second input of the third OR element, and the output with the installation input in the "0" trigger, and the information input of which is connected to the output of the first OR element, the first and second inputs of which are connected respectively to the first and second inputs of the block, the direct output of the trigger is connected to the first input of the element AND and the first inputs of the elements AND groups, the second inputs of which are connected to the corresponding outputs of the binary counter, the input of the installation to "0" and the information input of which is connected respectively to the outputs of the third OR element and the And element, the second input of which is connected to the output of the master oscillator, the outputs of the elements ps are connected to the corresponding address inputs of the memory element, the outputs from the first to (7m + 2) of which are connected respectively to the outputs from the first to (7m + 2) of the block.

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