RU198181U1 - Software and hardware encryption (cryptographic) means of protecting fiscal data - Google Patents

Abstract

The utility model relates to the field of computing. The technical result consists in increasing the level of protection of fiscal data and the reliability of the software and hardware encryption means of protecting fiscal data. A hardware and software encryption tool for protecting fiscal data is disclosed, comprising an easily removable tamper-resistant case with an interface connector (2) for realizing information exchange between a central processor (6) of a software and hardware encryption tool for protecting fiscal data and cash register equipment (11), carrying out information exchange with tax authorities (14), fiscal data operators (12) and marking information systems (13), while the central processor (6) contains a real-time clock (7) and is connected to a cryptographic processor (8) and non-volatile memory ( 9), characterized in that it contains a block of capacitors (3) with external power supply through an interface connector (2), while the block of capacitors (3) is connected to a comparator (4), which has feedback from the central processor (6), in addition , the output of the comparator (4) is connected to the input of the power stabilizer (5), the output of the power stabilizer (5) with connected to the inputs of the cryptographic processor (8), non-volatile memory (9) and the central processor (6), while the central processor (6) is connected with the possibility of transmitting the feedback signal “ASP” to the comparator (4); while entering through the interface connector (2), the external supply voltage is supplied to the capacitor block (3), which smooths the low-frequency fluctuations of the external voltage and serves as an energy accumulator; after the block of capacitors (3), the smoothed input voltage is supplied to the comparator (4), which is designed to control the lower 3.0 V and upper 6.8 V thresholds of the input voltage, within which the power regulator (5) operates in the “comfortable zone” ; when the input supply voltage exceeds the specified thresholds, the comparator (4) generates an interrupt signal, and the signal level “ASP” changes its value; the signal "ASP" is fed to the input of the central processor (6); any change in the value at the input "ASP" puts the central processor in the mode of termination of all operations; to ensure the completion of uninterrupted operations, the central processor, due to the energy stored in the capacitor block (3), completes all uninterrupted operations with the cryptographic processor (8), non-volatile memory (9), transfers the cryptographic processor (8), non-volatile memory (9) and itself in the mode of termination of all operations and with minimal power consumption switches to battery backup power (10). 1 ill.

Description

The field of technology.

The claimed technical solution relates to the field of computer technology, namely, means of protection and control of the authenticity (integrity) of electronic computing devices and means for their implementation.

The prior art.

From the patent of the Russian Federation No. 191278 for a utility model, IPC H04L9 / 00, G07G1 / 12, publ. 07/31/2019, (prototype), a cryptographic fiscal drive is known, which is implemented in a separate protected case with a connector for implementing an exchange channel with CCP (cash register equipment) using the I2C protocol, which allows external power supply through the connector contacts. A control microcontroller, non-volatile fiscal memory, a cryptographic coprocessor and a real-time clock connected to a backup power source are placed in series inside the case.

The disadvantage of the prototype is the lack of protection of fiscal data during fluctuations in external power.

A technical problem, the solution of which is provided when implementing or using a technical solution, is the need to ensure the possibility of performing critical operations (ensuring the integrity and reliability of fiscal documents when they are written to non-volatile memory, transmission and verification of fiscal documents sent / received through the CCP information exchange channel, etc. .d.), i.e. operations that cannot be interrupted instantly and must be completed before the supply voltage of the software and hardware encryption means for protecting fiscal data beyond the acceptable range or its interruption. In addition, it is necessary to expand the functionality of previously known devices.

Disclosure of the claimed technical solution.

The technical result, to which the proposed technical solution is aimed, is to increase the level of protection of fiscal data and the reliability of the software and hardware encryption means of protecting fiscal data.

The essence of the claimed technical solution lies in the fact that the software and hardware encryption tool for protecting fiscal data contains an easily removable tamper-resistant case with an interface connector for the implementation of information exchange between the central processor of the software and hardware encryption tool for protecting fiscal data and cash register equipment that implements information exchange with tax authorities, fiscal data operators and labeling information systems. In this case, the central processor contains a real-time clock and is connected to a cryptographic processor and non-volatile memory. It differs in that it contains a block of capacitors with external power supply through an interface connector. In this case, the capacitor block is connected to a comparator, which has feedback from the central processor. In addition, the output of the comparator is connected to the input of the power stabilizer, the output of the power stabilizer is connected to the inputs of the cryptographic processor, non-volatile memory and the central processor. In this case, the central processor is connected with the possibility of transmitting the feedback signal "ASP" with the comparator. At the same time, through the interface connector, the external supply voltage is supplied to the capacitor block, which smooths the low-frequency fluctuations of the external voltage and serves as an energy accumulator; after the block of capacitors, the smoothed input voltage is supplied to the comparator, which is designed to control the lower 3.0 V and upper 6.8 V thresholds of the input voltage, within which the power conditioner operates in the “comfortable zone”. When the input supply voltage exceeds the specified thresholds, the comparator generates an interrupt signal, and the signal level “ASP” changes its value. The signal "ASP" is fed to the input of the central processor. Any change in the value at the input "ASP" puts the central processor in the mode of termination of all operations. To ensure the completion of uninterrupted operations, the central processor, due to the energy stored in the capacitor block, completes all uninterrupted operations with the cryptographic processor, non-volatile memory, transfers the cryptographic processor, non-volatile memory and itself to the mode of termination of all operations and, with minimal energy consumption, switches to power from backup power batteries.

The above essence is a set of essential features of the claimed technical solution, ensuring the achievement of the claimed technical result.

The author of the claimed technical solution made a prototype of this solution, the tests of which confirmed the achievement of the technical result.

A brief description of the drawings.

The figure 1 shows a schematic diagram of a device.

List of reference designations:

1. hardware-software encryption (cryptographic) means of protecting fiscal data (SKZFD);

2. interface connector;

3. block of capacitors;

4. comparator;

5. power stabilizer;

6. central processing unit;

7. real-time clock (non-volatile timer);

8. cryptographic processor;

9. non-volatile memory;

10. backup battery;

11. cash registers,

12. fiscal data operator,

13. operator of information labeling systems, 1

14. tax authorities.

Implementation of a technical solution.

The hardware-software encryption (cryptographic) means of protecting fiscal data SKZFD (1) is installed in the cash register equipment (11) and contains an internal interface connector (2) through which information is exchanged between the cash registers and cash registers (11), which in turn communicates with the tax authorities (14), fiscal data operators (12) and the operator of the information labeling system (13), through which information exchange channels pass with the central processor (6) and external power is supplied to the capacitor block (3). The latter, in turn, is connected to a comparator (4), from which voltage is supplied to a power stabilizer (5), which generates an output voltage in a given range and provides a stabilized voltage to the cryptographic processor (8), non-volatile memory (9) and the central processor (6). The latter, in turn, includes a real-time clock (7), is connected to a cryptographic processor (8), with non-volatile memory (9), and is also connected with the possibility of transmitting an ASP feedback signal with a comparator (4). SKZFD (1) is made as a separate removable module in its own sealed case, excluding the fact of concealment of

authorized opening (by installing a self-destructive sticker, holographic sticker, etc.), with a backup battery (10) and a real-time clock (non-volatile timer) (7). In this case, SKZFD (1) can be located both in the KKT case (11) and can be located outside the KKT case (11). KCT information exchange channels

(11) UART and / or I2C compliant.

SKZFD (1) meets the requirements of the current legislation of the Russian Federation in the field of protection of information, fiscal data and the procedure for applying CCPs (11).

Examples of specific performance.

Example 1. SKZFD (1) provides the encryption and decryption functions of fiscal documents transmitted between CCPs (11), tax authorities (14), the fiscal data operator (12) and (or) the operator of marking information systems (13).

Example 2. SKZFD (1) provides the implementation of the possibility of information exchange with both tax authorities (14), fiscal data operators (12), and with operators of information marking systems (13).

The implementation of the proposed technical solution is not limited to the above examples.

Job description .

For the stable operation of modern microprocessor systems, stabilized power in the range from 3.0V to 3.6V is necessary. A sudden exit of the supply voltage beyond this range leads to unpredictable consequences, which can be manifested in the loss of part or all of the accumulated information, erroneous recordings, “freezing”, malfunctions, and termination of work, up to the failure of the hardware-software encryption tool for protecting fiscal data.

A feature of the presented technical solution is that the external power supply for the device can be unstabilized and can be in a wider voltage range, from 3.0V to 6.8V. Entering through the interface connector (2), the external supply voltage is supplied to the capacitor block (3), which smooths the low-frequency fluctuations of the external voltage and serves as a kind of energy accumulator. After the block of capacitors (3), the smoothed input voltage is supplied to the comparator (4), which is designed to control the lower 3.0V and upper 6.8V thresholds of the input voltage, within which the power regulator (5) operates in the “comfortable zone”. When the input supply voltage exceeds the specified thresholds, the comparator (4) generates an interrupt signal and the signal level “ASP” changes its value (switches from a logical zero to a logical unit or vice versa). The signal "ASP" is fed to the input of the central processor (6). Any switching (changing the value) at the input “ASP” puts the central processor (6) in the mode of termination of all operations. To ensure the completion of uninterrupted operations, the central processor (6), due to the energy stored in the capacitor block (3), completes all uninterrupted operations with the cryptographic processor (8), non-volatile memory (9), transfers the cryptographic processor (8), non-volatile memory (9 ) and itself in the mode of termination of all operations (high impedance on all buses), and with minimal power consumption switches to backup battery power (10). This mode of operation allows you to not consume the energy of the backup battery (10) with external power in the specified range, successfully complete uninterrupted operations, transfer the central processor (6) and cryptographic processor (8), non-volatile memory (9) to the stop mode of all operations ( the state is “off”) in order to avoid damage to critical information and the manifestation of other emergency situations, which significantly increases the reliability of the device as a whole. At the same time, it is possible to complete operations during the message encryption procedure for tax authorities (14), fiscal data operators (12) and information labeling system (13), since the operation is interrupted

encryption can lead to data corruption and failures in

the cryptographic part of the software and hardware encryption means of protecting fiscal data.

Industrial applicability.

The claimed technical solution is implemented using industrially produced devices and materials and will be widely used at trade enterprises and in the field of public services.

Claims (1)

A hardware-software encryption tool for protecting fiscal data that contains an easily removable tamper-resistant case with an interface connector (2) for implementing information exchange between the central processor (6) of a software-hardware encryption tool for protecting fiscal data and cash register equipment (11) that implements information exchange with tax authorities (14), fiscal data operators (12) and marking information systems (13), while the central processor (6) contains a real-time clock (7) and is connected to a cryptographic processor (8) and non-volatile memory (9 ), characterized in that it contains a block of capacitors (3) with external power supply through an interface connector (2), while the block of capacitors (3) is connected to a comparator (4), which has feedback from the central processor (6), in addition, the output of the comparator (4) is connected to the input of the power stabilizer (5), the output of the power stabilizer (5) is connected to the input dams of cryptographic processor (8), non-volatile memory (9) and central processor (6), while the central processor (6) is connected with the possibility of transmitting the feedback signal “ASP” to the comparator (4); while entering through the interface connector (2), the external supply voltage is supplied to the capacitor block (3), which smooths the low-frequency fluctuations of the external voltage and serves as an energy accumulator; after the block of capacitors (3), the smoothed input voltage is supplied to the comparator (4), which is designed to control the lower 3.0 V and upper 6.8 V thresholds of the input voltage, within which the power regulator (5) operates in the “comfortable zone” ; when the input supply voltage exceeds the specified thresholds, the comparator (4) generates an interrupt signal, and the signal level “ASP” changes its value; the signal "ASP" is fed to the input of the central processor (6); any change in the value at the input "ASP" puts the central processor in the termination mode of all operations; to ensure the completion of uninterrupted operations, the central processor, due to the energy stored in the capacitor block (3), completes all uninterrupted operations with the cryptographic processor (8), non-volatile memory (9), transfers the cryptographic processor (8), non-volatile memory (9) and itself in the mode of termination of all operations and with minimal power consumption switches to power from a backup battery (10).

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