CN100541438C - A kind ofly control the method and apparatus that watchdog circuit resets - Google Patents
A kind ofly control the method and apparatus that watchdog circuit resets Download PDFInfo
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Abstract
The embodiment of the invention provides a kind of method and apparatus that watchdog circuit resets of controlling, and its method comprises: the task to the current operation of central processor CPU is carried out timing; Timing reaches when setting timing cycle, notifies described CPU to handle; CPU interrupts the task of current operation, feeds dog by the aborted handling procedure.The device of control watchdog reset comprises: timing unit, notification unit and Interrupt Process unit.The embodiment of the invention is fed dog by the clocking capability aborted handling procedure among the CPU, thereby prevent that CPU from carrying out the long time when not feeding dog and the situation of watchdog reset takes place, having avoided occupying in the prior art EPLD resource simultaneously and having relied on the EPLD hardware logic and having realized the regularly problem of hello dog.
Description
Technical field
The present invention relates to the electronic device field technology, specially refer to a kind of method and apparatus that watchdog circuit resets of controlling.
Background technology
Development along with embedded system; requirement for the reliability design of satisfying system; usually can on veneer, adopt watchdog circuit monitoring CPU (Central Process Unit in real time; central processing unit) running status and the normal operation of generation reset enable signal system reset recovery when detecting software anomaly; thereby the software of having avoided moving on CPU is because some influence external or internal factor; program fleet occurs or be absorbed in the unusual of endless loop, the situation that causes the total system paralysis and can't recover.
The house dog its working principles is: there is a timer watchdog circuit inside, and its timing cycle (be called again and feed the dog cycle) was generally about 1.6 seconds.If input end does not receive the certain pulses signal in this timing cycle, timer internal is overtime, and watchdog circuit will be exported reset signal; If instead input end receives the certain pulses signal in timing cycle, timer internal will be cleared and pick up counting again, as long as timer internal is not overtime, watchdog circuit just can not exported reset signal.This input end at watchdog circuit provides the certain pulses signal stops its output reset signal with the zero clearing timer internal behavior, be called " feeding dog " by image operates, as long as " on time " feeds dog (promptly regularly providing the pulse signal of zero clearing timer in timing cycle), " dog " just can " not sting the people " (promptly can not export reset signal).Watchdog circuit is realized by software hello dog and output reset signal for the real-time monitoring and the restore funcitons of CPU software.The reset output terminal of watchdog circuit can be connected on the reseting pin of CPU even total system usually.In order to guarantee the system software operate as normal, then require software to feed dog at each at least and regularly provide feeding-dog signal in the cycle, stop watchdog circuit output reset signal and make system reset.In case software produces unusual, such as program fleet, just can't normally provide feeding-dog signal, thus the overtime resetting system of watchdog circuit, avoided total system owing to software anomaly is absorbed in long state of paralysis.
The introducing better guarantees of watchdog circuit the reliable and stable operation of system, but also brought simultaneously some problems that need solve.The target of watchdog circuit monitoring is the application software after the normal startup of system, but before the application software operate as normal, the process (comprising) that CPU has a guiding to start to using the loading of software, this process can take tens seconds time usually.In this process,, also need to carry out dog feeding operation for system can normally be started.For fairly simple software systems of not introducing operating system, the suitable adding of time that can be carried out according to statement in the boot of writing by the peopleware is fully fed dog statement (promptly exporting the program statement of feeding-dog signal) and is prevented watchdog reset.If but introduced embedded OS in the system, in boot, inevitably to carry out operating system initialization, and the process of calling system function.In the invoked procedure to system function, the specific implementation of function is sightless for the peopleware, thereby can't insert hello dog statement and feed dog in these functions; Simultaneously, before the operating system operate as normal, multitask environment is not set up as yet, can't realize feeding dog by seizing of high-priority task yet.The execution time that therefore if system function calls in start-up course long (moving decompression function that process uses etc. such as code), exceeded and fed the dog cycle, watchdog reset will take place in system in calling the process of this class function, cause system normally to start.
In order to solve the problem that the watchdog reset in the CPU electrifying startup process causes system normally to start before operating system and the normal operation of application software, common way is hardware logic EPLD (the Erasable Programmable Logic Device at veneer at present, the erasable programmable logical device) increases the design of feeding the dog function in, make tens times in second behind Board Power up in (concrete duration decide according to the cost of system start-up time) by EPLD logic generation cycle feeding-dog signal, guarantee the behavior that can not produce the watchdog reset system in the CPU start-up course behind the Board Power up.Power on finish system start-up after, the EPLD logic stops to feed dog, feeds dog by software, the recovery watchdog circuit is to the monitoring and the restore funcitons of CPU software.
In carrying out process of the present invention, the inventor finds in the prior art to solve the dog problem of feeding in the CPU electrifying startup process by the EPLD logic, and there are the following problems at least: on the one hand, this function need take the EPLD logical resource, will realize that for logic the timing signal in one tens second itself will realize by the frequency division to system clock, this is considerable for an EPLD logical device with the logical block that tens Mhz (megahertz) divide the frequency dividing circuit of the tens seconds signals that occur frequently to take; On the other hand, in some single board design,, may not adopt the EPLD logical device, and only keep FPGA (Field Programmable Gate Array, field programmable gate array) logical device at present for to other considerations such as cost or volumes.Those of ordinary skill in the art all know, FPGA is RAM (Random Access Memory, random access storage device) logical device of type, a difference of it and the EPLD maximum back internal logic that just is to cut off the power supply can't be preserved, all need after powering on to reload at every turn and could normally move, hello the dog function in the time of therefore can't using fpga logic to finish the CPU electrifying startup.Obviously, in this single board system that does not have an EPLD design, in the Board Power up start-up course, adopt hardware logic EPLD dog-feeding method infeasible.
Summary of the invention
Embodiment of the invention technical matters to be solved provides a kind of method and apparatus that watchdog circuit resets of controlling, to solve in the prior art in the Board Power up start-up course by taking the EPLD resource and relying on the problem that the EPLD hardware logic realizes feeding in the watchdog reset dog.
The embodiment of the invention provides a kind of method of controlling watchdog reset, comprising:
Electrifying startup task by timer or the current operation of register pair central processor CPU is carried out timing;
Timing reaches when setting timing cycle, and described register notifies described central processor CPU to handle by producing the unusual or described timer of register by producing look-at-me;
Described central processor CPU interrupts the task of current operation, feeds dog by the aborted handling procedure.
The embodiment of the invention provides a kind of device of controlling watchdog reset, comprising: timing unit, notification unit and Interrupt Process unit;
Timing unit is used for carrying out timing by the electrifying startup task of timer or the current operation of register pair central processor CPU;
Notification unit links to each other with timing unit, is used for this timing unit timing and reaches when setting timing cycle, and described register notifies described central processor CPU to handle by producing the unusual or described timer of register by producing look-at-me;
The Interrupt Process unit is used for notification unit notify described central processor CPU to handle after, feed dog by the aborted handling procedure.
This shows, the embodiment of the invention is carried out timing by the timing unit among the CPU to the task of the current operation of CPU very easily, when timing reaches predefined timing cycle, notice CPU, CPU interrupts the task of current operation, feed dog by the aborted handling procedure, when thereby the task of preventing the current operation of CPU is not fed dog in the long time of execution, and the situation of generation watchdog reset has been avoided occupying in the prior art EPLD resource simultaneously and has been relied on the problem that the EPLD hardware logic realizes regularly feeding dog.
Description of drawings
The method flow diagram of the control watchdog reset that Fig. 1 provides for the embodiment of the invention one.
What Fig. 2 provided for the embodiment of the invention is basic startup flow process and the dog-feeding method process flow diagram thereof during PPC CPU in the VxWorks system at application scenarios.
What Fig. 3 provided for the embodiment of the invention is the basic startup flow process and the dog-feeding method process flow diagram thereof of IXP23XX network processing unit in the VxWorks system at application scenarios.
The installation drawing of the control watchdog reset that Fig. 4 provides for the embodiment of the invention five.
Embodiment
The embodiment of the invention discloses the method and apparatus that the control watchdog circuit resets.
In embodiments of the present invention, the method and apparatus of control watchdog reset is actually the dog problem of feeding that solves in the watchdog circuit, and said hello dog of the embodiment of the invention and control watchdog reset are to solve the same problem.
The method of the control watchdog reset that the embodiment of the invention one provides as shown in Figure 1, specifically comprises:
Step 101, the task of the current operation of central processor CPU is carried out timing;
Step 102, timing reach when setting timing cycle, notify described CPU to handle;
The task that step 103, described CPU interrupt current operation is fed dog by the aborted handling procedure.
The embodiment of the invention is utilized the register among the CPU on the veneer or the clocking capability of timer module, carry out dog feeding operation by software programming aborted handling procedure, because interrupt priority level is the highest, when timing reaches predefined timing cycle (promptly feeding the dog cycle), operation that can the interrupts of CPU current task, carry out dog feeding operation, and then the guiding task in the Board Power up start-up course of preventing is being called the execution time during long system function, the situation of watchdog reset takes place, and has avoided taking in the Board Power up start-up course of the prior art the EPLD resource simultaneously and has relied on the problem that the EPLD hardware logic realizes regularly feeding dog.
The embodiment of the invention two provides a kind of concrete application scenarios of controlling watchdog reset in VxWorks system (a kind of embedded real-time operating system that wind river company provides).By PPC (PowerPC, one group of CPU series title that Freescale Freescale company releases) DEC (the Decrementer Register on the CPU environment (as MPC8260) of series, register successively decreases) carry out timing, utilize and regularly interrupt realizing feeding dog, be specially:
All has a DEC register among the CPU of PPC series, it is a counter that successively decreases automatically according to fixed frequency, and when the most significant digit of this register changes when becoming 1 by 0, expression reaches predefined timing cycle, it is unusual to produce corresponding D EC, and notice CPU handles.Write DEC aborted handling procedure, realize dog feeding operation, and give DEC register assignment again, and be articulated to this unusual vector place, just can realize regularly interrupting feeding the dog function according to the relation of the frequency of successively decreasing of feeding dog cycle and DEC by this program.
The embodiment of the invention three provides another to control the concrete application scenarios of watchdog reset in the VxWorks system.By PPC (Power PC, one group of CPU series title that Freescale Freescale company releases) the CPU environment (as MPC8260) of series is gone up CPM (Communication ProcessorModule, communication processor module) timer Timer carries out timing, utilize and regularly interrupt realizing feeding dog, be specially:
CPM Timer is the timer module among the PPC series CPU, it produces a Timer and interrupts when timing is finished, interruptable controller in the notice sheet, again by interruptable controller output external interrupt signal, it is unusual that notice CPU has produced external interrupt, and to the unusual vector of external interrupt place execute exception interrupt handling routine.Though this is the process that a secondary interrupts, and relate to and interrupt comparatively complicated operations such as multiplexing, but finish the initialization of interrupt system in operating system after, the peopleware only need write basic interrupt service routine, articulates function and just can realize regularly interrupting feeding dog by what system provided.
The embodiment of the invention four also provides a kind of concrete application scenarios of controlling watchdog reset in the VxWorks system.In the network processing unit environment (as IXP2350) by IXP23XX (Intel network processing unit) series, the Timer timer module on the APB bus is carried out timing, utilizes regularly to interrupt realizing feeding dog, is specially:
The Timer timer module produces a Timer and interrupts when timing is finished, the notice interruptable controller, (at IXP23XX series network processing unit is arm processor (AdancedRISC Machines to interruptable controller notice CPU, CompanyName, also be a kind of common name of processor)) kernel generation interrupt request, as FIQ (Fast Interrpt Request, quick interrupt request) or IRQ (Interrupt Request, interrupt request) unusual, regularly interrupt realizing feeding dog by the execution generation of corresponding aborted handling procedure.Be similar to the CPM Timer of above-mentioned PPC, this is that secondary process of interrupting and relating to is interrupted comparatively complicated operations such as multiplexing, when operating system has not been set up interrupt system as yet, interrupt feeding the dog scheme with respect to the DEC among the PPC series CPU, except creating FIQ or the first-level interrupt handler of IRQ, be articulated to the respective vectors place, also need the initialization interruptable controller, articulate Timer abnormal interruption handling procedure, make its interruption that can receive the Timer module and notice kernel FIQ or the unusual generation of IRQ, finish and regularly interrupt feeding dog.
Below in conjunction with accompanying drawing the embodiment of the invention is done further and to be elaborated.
What Fig. 2 provided for the embodiment of the invention is basic startup flow process and the dog-feeding method process flow diagram thereof during PPC CPU in the VxWorks system at application scenarios.
PPC CPU start-up course is comparatively complicated in the actual VxWorks system, only stresses with feeding dog relevant part in the start-up course herein.As shown in Figure 2, the CPU that has briefly described a simplification in the entity square frame of the left side basic start-up course that application software brings into operation that powers on, the empty frame note in the right has then illustrated the dog-feeding method in this start-up course.
At first in step 201, the C language environment normally realizes the basic initialization of CPU, RAM before setting up with assembly language, and this process is shorter, and the general mode of inserting statement that adopts realizes that hello dog can meet the demands.
In step 202, just need the call operation system function to realize most of functions, some operation (as decompress, the configuration of MMU (Memory Management Unit, memory management unit) etc.) be more consuming time, adopting interrupt timing to feed dog is reasonable method.Simultaneously in the sheet of CPU before the interruptable controller initialization, directly using DEC to feed dog unusually is comparatively simple scheme, just can initialization DEC unusual therefore before step 202, adopts the timing of DEC to interrupt realizing hello dog.
Step 203, system start-up enter initialization system hardware (comprising the initialization to interruptable controller), the configuration of operating system and the kernel that starts the operating system.
Step 204, system clock initialization, and the initialization (promptly finishing the establishment of multitask running environment) of module such as the management of complete operation Installed System Memory, IO system.But acquiescence is enabled DEC and is interrupted producing system clock in the os starting process, so we stopped using DEC regularly to interrupt feeding dog before the initialization of step 204 system clock.
In step 204 (system clock initialization) before, stop using DEC regularly to interrupt feeding dog, use CPM Timer instead and interrupt feeding dog, this moment system each unusual vector all finished initialization and interruptable controller also initialization finish, articulate the also more convenient realization of interrupt handling routine of the Timer of CPM.
At last, start before the operation of application software in step 205, the timing that stops CPM Timer interrupts feeding dog, feeds dog by the application software task of enabling, and recovers the monitoring function of house dog for running software.
What Fig. 3 provided for the embodiment of the invention is the basic startup flow process and the dog-feeding method process flow diagram thereof of IXP23XX network processing unit in the VxWorks system at application scenarios.
In IXP23XX series network processing unit, do not possess the abnormal interruption that DEC among the above-mentioned similar PPC series CPU has timing function like this, only on the APB bus, hang with the Timer timer module, so utilize the function of Timer timer module to realize feeding dog.
Because adopt vxWorks operating system equally, start-up course is a basically identical with step shown in Figure 2.Different is, because the CPU framework difference that adopts is regularly interrupted dog-feeding method also different (empty collimation mark is shown).In IXP23XX series network processing unit, have only the Timer module can be used for producing regularly and interrupt, so step 302 all can only use this regularly to interrupt feeding dog before the application software operation in the step 305 in start-up course.And before step 302, operating system is not set up fully, to regularly interrupt feeding dog by Timer, except creating the exception handler of one-level FIQ or IRQ, be articulated to the respective vectors place, also need the initialization interruptable controller, articulate secondary Timer interrupt service routine, regularly interrupt dog feeding operation to finish.Then, in step 304, operating system will be finished the foundation of system's vector initialization and interrupt system, the abnormality processing that former cause peopleware oneself realizes and the multiplexing program of interruptable controller all will lose efficacy, thereby need again the function of call operation system, articulate the timer interrupt service routine again and proceed timing and interrupt dog feeding operation.In the final step 305, before the application software operation, close Timer and regularly interrupt, feed dog, recover the supervisory function bit of house dog for running software by the application software task of enabling.
The embodiment of the invention five provides a kind ofly controls the device that watchdog circuit resets, and as shown in Figure 4, comprises timing unit, notification unit and Interrupt Process unit;
Timing unit is used for the task of the current operation of CPU is carried out timing;
Notification unit links to each other with timing unit, is used for the timing unit timing and reaches when setting timing cycle, and notice CPU handles;
The Interrupt Process unit is used for notification unit notice CPU handle after, feed dog by the aborted handling procedure.
Timing unit can be DEC register, CPM Time or Timer.But timing unit is not limited only to above-mentioned several, and the unit that any on the veneer can clocking capability can be used for timing.
More than lift preferred embodiment; the purpose, technical solutions and advantages of the present invention have been carried out further detailed description; institute is understood that; more than be the preferred embodiments of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind ofly control the method that watchdog circuit resets, it is characterized in that,
Electrifying startup task by timer or the current operation of register pair central processor CPU is carried out timing;
Timing reaches when setting timing cycle, and described register notifies described central processor CPU to handle by producing the unusual or described timer of register by producing look-at-me;
Described central processor CPU interrupts the task of the current operation of described central processor CPU, feeds dog by the aborted handling procedure.
2, the method for claim 1 is characterized in that, described electrifying startup task by timer or the current operation of register pair central processor CPU is carried out timing and comprised:
Register DEC carries out timing to the task of the current operation of described central processor CPU by successively decreasing; Perhaps
Timer carries out timing to the task of the current operation of described central processor CPU by Communications Processor Module CPM timer; Perhaps
By timer module Timer the task of the current operation of described central processor CPU is carried out timing.
3, method as claimed in claim 2, it is characterized in that, when by the register DEC that successively decreases the electrifying startup task of the current operation of described central processor CPU being carried out timing, described timing reaches when setting timing cycle, notifies described central processor CPU to carry out treatment step and is specially:
When described most significant digit of successively decreasing register DEC changed, it was unusual and notify described central processor CPU to handle to produce the register DEC that successively decreases.
4, method as claimed in claim 3 is characterized in that, describedly feeds dog by the aborted handling procedure and is specially:
Register DEC aborted handling procedure is fed dog by successively decreasing.
5, method as claimed in claim 4, it is characterized in that, the described register DEC aborted handling procedure that successively decreases also is used for giving the described register DEC assignment again of successively decreasing according to the frequency relation that successively decreases of described setting timing cycle and the described register DEC that successively decreases, and is articulated to the unusual vector of the register DEC place of successively decreasing.
6, method as claimed in claim 2 is characterized in that, when the electrifying startup task of the current operation of described central processor CPU being carried out timing by described Communications Processor Module CPM timer Timer,
Described timing reaches when setting timing cycle, notifies described central processor CPU to handle the task of interrupting the current operation of described central processor CPU with described central processor CPU, feeds the dog step by the aborted handling procedure and is specially:
When described Communications Processor Module CPM timer Timer timing is finished, produce Timer interruption and notice interruptable controller;
Described interruptable controller output look-at-me, it is unusual to notify described central processor CPU to produce external interrupt, and to the unusual vector of described external interrupt place execute exception interrupt handling routine, described aborted handling procedure realizes regularly interrupting feeding dog by the function that articulates that system provides.
7, method as claimed in claim 2 is characterized in that, when the electrifying startup task of the current operation of described central processor CPU being carried out timing by timer module Timer,
Described timing reaches when setting timing cycle, notifies described central processor CPU to handle the task of interrupting the current operation of described central processor CPU with described central processor CPU, feeds the dog step by the aborted handling procedure and is specially:
When finishing, timer module Timer timing produces Timer interruption and notice interruptable controller;
Described interruptable controller notifies described central processor CPU to produce interrupt request, and the execute exception interrupt handling routine produces and regularly interrupts realizing feeding dog.
8, method as claimed in claim 7 is characterized in that, described interrupt request is: quick interrupt request FIQ is unusual or interrupt request IRQ is unusual.
9, method as claimed in claim 7, it is characterized in that, before by timer module Timer the electrifying startup task of the current operation of described central processor CPU being carried out timing, also further comprise: the described interruptable controller of initialization articulates the Timer aborted and handles service routine.
10, a kind ofly control the device that watchdog circuit resets, it is characterized in that, comprise timing unit, notification unit and Interrupt Process unit;
Described timing unit is used for carrying out timing by the electrifying startup task of timer or the current operation of register pair central processor CPU;
Described notification unit links to each other with described timing unit, is used for described timing unit timing and reaches when setting timing cycle, and described register notifies described central processor CPU to handle by producing the unusual or described timer of register by producing look-at-me;
Described Interrupt Process unit is used for notification unit notify described central processor CPU to handle after, feed dog by the aborted handling procedure.
11, device as claimed in claim 10 is characterized in that, described timing unit is: DEC register, Communications Processor Module CPM timer Time or timer module Timer.
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