RU1829073C

RU1829073C - Device for conversion of arrays of binary numbers within interval

Info

Publication number: RU1829073C
Application number: SU904861552A
Authority: RU
Inventors: Дмитрий Степанович Наумов
Original assignee: Центральное конструкторское бюро "Алмаз"
Priority date: 1990-08-20
Filing date: 1990-08-20
Publication date: 1993-07-23

Description

А 0 и счетчик 1 сигналом со 2-го выхода А О, КА 2 блока сравнени 4 сразу переводитс на число 5 (или 7). В блоке пам ти 2 происходит стирание чисел, кратных 5 и 7.A 0 and counter 1 by the signal from the 2nd output A O, KA 2 of block 4 are immediately transferred to the number 5 (or 7). In the memory unit 2, the numbers multiple of 5 and 7 are erased.

В результате выполнен второй такт работы устройства, т.е. по исходному массиву полного множества простых чисел в интервале значений 2П, 2 + 1 - 1 осуществлено его преобразование в аналогичный массив в интервале значений 2П , 2П h 2, т.е. по исходному множеству 5, 7 (в интервале значений 22, 22 1 - осуществлено его преобразование в множество 11, 13 (в интервале значений 2 ч . 2 1) при этом в процессе работы устройства во врем первого и второго тактов работы числа , не вл ющиес простыми в интервале значений 8, 15, т.е. 8, 9. 10, 12. 14. 15, стерты (обнулены) в блоке пам ти 2.As a result, a second clock cycle of the device was performed, i.e. over the original array of the full set of primes in the range of 2P, 2 + 1 - 1 values, it was converted to a similar array in the range of 2P, 2P h 2 values, i.e. in the initial set 5, 7 (in the range of values 22, 22 1 - it was converted into a set of 11, 13 (in the range of 2 hours 2 1) while the device did not during the first and second cycles of operation of the number which are simple in the range of 8, 15, i.e. 8, 9. 10, 12. 14. 15, are erased (zeroed) in the memory unit 2.

Далее процесс работы устройства продолжаетс аналогично первым двум тактам, но при п 3, п 4, т.д. соответственно при других (больших) значени х чисел А. При А 2 процесс работы устройства заканчиваетс сигналом с 3-го выхода А 2т , блока сравнени 4 (при этом обнул етс входной счетчик 1 и блок синхронизации 14).Further, the operation of the device continues similarly to the first two measures, but with n 3, n 4, etc. respectively, for other (large) values of the numbers A. At A 2, the operation of the device ends with a signal from the 3rd output A 2t, comparison unit 4 (the input counter 1 and synchronization unit 14 are reset to zero).

При зтом в блоке пам ти 2 сформировано полное множество простых чисел в за данном интервале значений от 0 до 2т.Moreover, in the memory block 2, a complete set of primes is formed in a given range of values from 0 to 2t.

Claims

The claims

A device for converting arrays of binary numbers in the range of 2 °, 2P + 1 -1, comprising an argument register, an output register, a memory unit, an auxiliary register, an adder and a synchronization unit, characterized in that, in order to expand the class of tasks to be solved by converting arrays of binary numbers in the range of values 2n + 1, 2P + 2 - 1. a counter, the first and second groups of OR elements, from the first to

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35 40

10

fifteen

twenty

25

thirty

the fourth group of AND elements and a comparison circuit, the counter outputs being connected to the information inputs of the AND elements of the first and second groups, the control inputs and outputs of the AND elements of which are connected to the clock input of the synchronization unit and the first inputs of the OR elements of the first and second groups, respectively, the second inputs of the elements OR which are connected to the outputs of the OR elements of the third and fourth groups, respectively, and the outputs, respectively, with the address and information inputs of the memory unit, the recording input of which is combined with the second inputs by elements And of the third and fourth groups and is connected to the output A KA 2t of the comparison circuit (where A 2 is the output number of the memory unit, K 1, 2, Z ... pl is the power of the number), the output is K A 2t. (or A 0). which is connected to the inputs of the zero setting of the adder, the output register, the reading input of the memory unit, the counting input of the counter and the stop input of the synchronization unit, the clock input of which is combined with the input of the initial installation of the counter and connected to the output A 2t - 1 of the comparison circuit, the first input of which is combined with the information input of the adder and connected to the output of the output register, the output of the adder is connected to the second inputs of the AND elements of the third group and to the second input of the comparison circuit, the third input of which is connected to the output of the register an argument whose input is connected to the start input of the synchronization unit and the information input of the device, the register output is connected to the second inputs of the And elements of the fourth group, the clock output of the synchronization unit is connected to the synchronization inputs of the counter, memory unit, adder and output register, the output of the memory unit is connected with an input of an output register, the output of which is the output of the device.