RU1817047C - Device for testing serviceability of module of amplification system of radioelectronic equipment - Google Patents

Abstract

The invention relates to a measurement technique. The device contains a source 1 of a test signal, terminals for connecting a controlled amplifier module 2, matching cascade 3, counter 4, lines 5, 8 and 11 of the delay, elements NOT 6 and 7, comparators 9 and 10, elements BAN 12 and 13 and display unit 14 . The device has enhanced functionality by providing simultaneous control of the amplitude and duration of pulses at the output of the monitored module, the generation and stability of the module characteristics. 2 ill., 1 tab. G

Description

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About N x |

The invention relates to instrumentation.

The purpose of the invention is to expand the functional capabilities of the device by ensuring its adaptability to simultaneously control the presence of generation, amplitude, pulse duration from the output of the control object, and control the stability of characteristics.

In Fig. 1 is a schematic diagram of a device; Fig. 2 is a timing chart illustrating its operation.

Figure 1 shows the source 1 of the test signal, the output and input terminals of the monitored module 2, matching cascade 3, binary counter 4, the first delay line 5, the first element NOT 6, the second element H E 7, the second delay line 8, the first comparator 9, second comparator 10. third delay line 11, first element BAN 12, second element BAN 13, latching unit 14, including RS triggers 15-19, indicators 20-24, isolation diodes 25 and 26. In FIG. 2, :

gi is the nominal pulse duration at the output of the module;

t, gu - the lower and upper limit of the permissible pulse durations (the outcome of the specified tolerances of 5%, 10%, etc.);

Au is the nominal amplitude of the pulse at the output of the module;

AN, AB - the lower and upper boundaries of the amplitude;

tav taa pulse delay time delay line 5 and 3.

t is the time axis;

Urn is the voltage plot at the output of the pulse generator;

THOM - nominal pulse duration;

Pauses pause duration between the end of the previous and the beginning of the subsequent impulses;

output mode - voltage plot at the output of the controlled module;

ile2 voltage plot at the output of the second delay line;

Unai plot of the voltage at the output of the first delay line;

output mode (generator) - voltage diagram at the output of the module in case of a malfunction of the generation type;

ills voltage plot at the output of the third delay line;

UHE-diagram of the voltage at the output of the element NOT,

The device operates as follows.

In the initial state, the RS-flip-flops of the display unit 14 and counter 4 are briefly supplied with a reset pulse from the key (not shown in Fig. 1), the test signal source 1 does not give test pulses to the input of the controlled module 2, the output of which is absent , also there is no pulse at the output of the matching stage 3, the input and output of the binary

counter 4, delay lines 5.8 and 11, comparators 9-10, S-inputs of RS-flip-flops 15, 17, 18 and 19, a logic level 1 signal is supplied from the outputs of the elements NOT b and 7, respectively, to the input of the element BAN 12, for which there is no signal at input b, and input B is forbidden 13. From the output of PROHIBIT 12, logic 1 is supplied to the input of the RS-flip-flop 16, from the input R- of which the signal has already been removed, from the output of the RS0 flip-flop 16, the signal to illuminate indicator 21, there is no signal at the output of the BAN 13 element, there is no signal at the outputs of RS-flip-flops 15, 17. 18 and 19 and input Odes of indicators 20, 22, 23 and 24.

5 Means allowing setting the necessary thresholds for the operation of elements 9 and 10 are included in the internal correction circuits of comparators 9.10 (as a rule, these are internal voltage divider resistors 0).

The response levels of these elements are determined by the particular type of monitored modules and are set during the setup phase of the device.

5 The choice of the circuit construction of the matching stage 3 is carried out at the stage of design and commissioning of the device, because its specific performance depends on the elemental composition of the controlled module and device.

0 So in order to normalize the signal from the output of a module having, in normal operation, an unacceptably large amplitude for the input circuits of the device, it is necessary to perform element 3, for example, in

5 as a resistive divider, and in the case of a signal with a small amplitude, as a linear amplifier, etc.

When you turn on the generator 1 test pulses from its output test

0 pulses are fed to the input of the controlled module 2, amplified to the required value, and from the output they go to the input of the matching device 3, the output of which goes to the inputs of the binary counter 4, delay lines 5, 8 and 11, elements NOT 6 and 7 and comparators 9 and 10.

In case of serviceability of the controlled module 2, a pulse will be generated at its output, which, passing through the matching device 3, will have a duration of t

Ti TB and amplitude AC Ay Av. On the leading edge of the pulse, 1 will be written into counter A, and then the state of the counter will not change until the end of this pulse, the state of trigger 15 will not change, indicator 20, which indicates the abnormal number of pulses during t time, will not light, at the output of element 6, logic O is activated for a while, after time t-3i THDM + An + Ar2 at the output of delay line 5 and input b of the element BAN, a pulse is generated which, through the diode 25, will reset binary counter 4 to the zero state and remove it from the output ban item 12 and input s-three of logic 15, logical 1, to the input R of which, after a time t33 of tpause + Tnom -A t, it is supplied from the output of the delay line 11, which contains a differential circuit, briefly logical 1 and changes the state of the RS-trigger 16, indicator 21, indicating the state norms of maximum pulse duration, go out. When the pause time at the output of the element 6 is reached, logical 1 will appear, which, through t tsi + Tn, will appear at the output of the element BAN 12, will change the state of the trigger 16 and the indicator 21 will again light up.

On the leading edge of the monitored pulse at the output of the element NOT 7 and the input b of the element FORBID 13, logic 0 is displayed, and at the input a and the output of the element FORBID 13, after a time Il2 n, logic 1 from the output of element 8, which will transfer the RS-trigger 17 and will cause the indicator 22 to light up, indicating that the duration of the monitored pulse is greater than the lower tolerance. After the time Teznom + Tauzy-L, after the end of the pulse from the delay line 8, there will be a logical 0 at the input S of the trigger 17, a logical 1 at the input R, the indicator 22 will go out, then the process repeats again. Also, a comparator 10 is triggered on the leading edge of the pulse, tuned to the lower amplitude tolerance, and the trigger 19 will be in a single state, indicator 24, indicating that the amplitude level of the monitored pulse is above the lower tolerance, will light up. After a period of time: 3s IHOM + pause-Arc of the delay line 11, through the diode 26, logic 1 will go to the R-input of trigger 19, change its state, indicator 24 will turn off. The process is then repeated. The comparator 9, tuned to the upper tolerance in amplitude, does not work, does not change the state of the RS-trigger 18, indicator 23, indicating that the amplitude

the monitored pulse did not exceed the upper tolerance; it does not light up.

In the event of a malfunction of the controlled module 2, which leads to a shortening of the pulse at its output in excess of the lower tolerance, the device operates as described above, but the pulse at the output of the element BAN 13 is not generated, because at the output of the element NOT 7 and the input b of the element is FORBIDDEN 13

logical level 1 is earlier than at input a of element BAN 13 and will be present during the action of a pulse from the output of delay line 8, the state of the RS-trigger will not change, its output will have a level of logical 0, indicator 22, indicating the normal pulse duration at the bottom Tolerance will not shine.

In case of malfunction of the controlled module 2, leading to lengthening

pulse at its exit beyond the upper tolerance, the device operates similarly to that described for a working module, except that the signal at the output of the element is NOT 6 and the input of the element is NOT allowed 12 later. than at the output of the delay line 5; At the output of the element PROHIBIT 12, logic level 1 does not appear, after a period of time ТЗЗ THOM + тауеы А г, a reset pulse is received at the input R of trigger 16 and puts the trigger in zero state, indicator 21, indicating the state of the duration of the monitored pulse below the upper tolerance, goes out and in the subsequent state of the trigger 16 and indicator 21 will not change.

in the event of a malfunction of the controlled module 2, which leads to a decrease in the amplitude of the pulse at its output below the tolerance, the device operates similarly to that described for a working module, except that the comparator 10, tuned to the lower allowable level of the pulse amplitude Am (does not work, the amplitude settings are less than the logical level 1, the RS-flip-flops 15, 16 and 17 may be unstable, and the indicators 20, 21 and 22 will glow respectively), trigger 19 will not be reset to the single state and indicator 24, indicating state controlled pulse amplitude above the lower tolerance will not svetits. In the case of a malfunction of the controlled module 2, which leads to an increase in the amplitude of the pulse at its output above the upper tolerance, the device operates similarly to that described for a working module, except that the comparator 9, tuned to the upper permissible amplitude level Av, will trigger, trigger 18 will be reset to a single state indicator 23,

indicating that the amplitude has exceeded the upper tolerance, lights up.

In the event of a malfunction of the monitored module 2. leading to the appearance of several output pulses per input (generation), the device will work similarly to that described for a faulty module, when the pulse duration from the output of module 2 is shorter than the lower permissible limit, except for the second the generated pulse counter 4 will overflow, a signal will appear on the S input of the trigger 15 and its output, the indicator 20, indicating the presence of a malfunction of the generation type module, will light up, Cases of complex malfunction Tey, where both the amplitude and duration of the pulses at the output of the controlled unit 2 will be released for access, there is no need to describe, since device operation in these cases will represent combinations of device operation for the cases described above.

The status of the indicators of the device for the initial position and the main faults is presented in the table.

By periodically lighting up or extinguishing the indicators (time of lighting up or extinguishing of the pulse repetition period), one can judge the stability of the parameters of the controlled REA module.

Claims (1)

SUMMARY OF THE INVENTION A device for monitoring the operability of a module of an amplifier path of electronic equipment, comprising terminals for connecting a monitored module, an input signal source, the output of which is connected to a terminal for connecting an input monitored module, the matching stage, the input of which is connected to the terminal for connecting the output of the monitored module, the first and second comparators, the combined inputs of which are connected to the output of the matching stage, an indication unit, the first and second inputs of which are connected to the outputs of the first and second comparators, characterized in , what, in order to expand the functionality, it introduced a counter, three delay elements, two inverters, two FORBID elements and two diodes, the combined inputs of the delay elements, inverters and counter connected to the output of the matching stage, the first and second inputs of the first inhibit element are connected respectively to the outputs of the first inverters and the delay element, the first and second inputs of the second the elements of the PROHIBITION are connected respectively to the outputs of the second inverters and the delay element, the outputs of the counter, the first and second elements of the PROHIBITION are connected respectively to the third, fourth and fifth inputs of the display unit, the outputs of the first and third elements of the delay are connected respectively through the first and second diodes to the Reset bus, connected to the combined control inputs of the counter and a display unit, wherein the display unit contains five P -5 flip-flops, the combined R-inputs of which form the control input of the display unit, the S-inputs of R-S-flip-flops from the first to fifth are inputs of the block indications, respectively, from the first to fifth, and the outputs of the R-S flip-flops from the first to fifth are connected to the indicators of the same name. Device LED Status Note. 1 - indicator is on. O - the indicator is off.