RU1815638C - Device for testing microprocessor system - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to build microprocessor systems based on the KR580IE80A microprocessor. The aim of the invention is to increase the reliability of control. The goal is achieved by introducing into the device triggers 2, 3, 4, 5, comparison circuits 10 and 11, element And 13, inverter 15. The invention consists in detecting downtime of the microprocessor system and increasing the number of monitored control signals generated on the control bus. 6 ill. ate with

Description

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The invention relates to automation and computer engineering and can be used in the construction of microprocessor systems based on the KR580IE80A microprocessor.

The aim of the invention is to increase the reliability of control.

In FIG. 1 shows a functional diagram of a device; Figures 2-5 are timing diagrams of the operation of the device in various modes, using the notation introduced in Figure 1; Fig. b shows the operation algorithm of the microprocessor of the K580IK80A series in standby and capture modes.

The device (see figure 1) contains the first 1, second 2, third 3, fourth 4 and fifth 5 triggers, the first 6, second. 7 and third 8 elements OR, first E, second 10 and third 11 comparison schemes, the first 12 , third 13 and second 14 elements AND, element NOT 15.

The inputs of the device 16-23 are connected respectively to the inputs (outputs) of the microprocessor SYNC, Fi, WAIT, READY, F2. HOLD. HLDA, DBIN,

Consider the purpose of the elements of the device (figure 1). The first trigger 1 is designed to fix the mismatch of the signals generated by the microprocessor and generated by the control device. Fixation is carried out on each trailing edge (decay) of the FI clock pulses generated by the microprocessor. In the initial state, the trigger is set to 0, in case of an error (malfunction) of the microprocessor system, the trigger is set to 1. The trigger can be performed on the basis of a two-stage RSC trigger. The objectives of its initial installation are not conditionally shown.

The second trigger 2 is for detecting the start of a machine cycle. The trigger for each SYNC pulse generated by the microprocessor at the beginning of each machine cycle is set to a single state, enabling triggers 3 and 4. Then, in each cycle, the trigger is set to zero. The trigger can be performed on the basis of two-stage ICK triggers.

The third trigger 3 is designed to fix the standby request signal received with the output of the element HE 15. The trigger is installed on the trailing edge of the clock pulses of phase F2 of the microprocessor: when set to the single state, the clock pulses Гг second

5

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5

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the first clock cycle (T2) of the microprocessor, and when set to zero, the clock pulses of the cycle in which the wait request was made. The operation of trigger 3 corresponds to the logic for generating a signal at the output of the WAIT microprocessor. Trigger 3 can be performed on a DCV trigger.

The fourth 4 and fifth 5 triggers are designed to fix the signal of the request for the state of capture HOLD, which is received at the information input of the fourth trigger 4. The signal is polled and recorded by trigger 4 at the back of the clock pulses of the phase Ra of the second clock cycle TC (signal 1 - capture request) and in each clock cycle following at T2 (signal O - removal of a capture request).

The fifth trigger 5 interrogates and fixes the HOLD signal according to the sync pulse of phase F2 of the TK cycle (signal 1 to the capture request and by the sync pulse F2 in each cycle of the next to the TK, i.e. in the clock cycles of the state of capture (signal O of the request to capture) Both triggers 4 and 5 generate capture signals at their direct outputs in accordance with the logic of generating a similar signal at the output of the HLDA microprocessor. The fourth 4 and fifth triggers can be performed on the basis of two-stage DCV triggers. and 5 on their way out x signals that exactly correspond to the signals generated by the microprocessor are implemented according to the microprocessor operation algorithm shown in Fig. b.

The first OR element 6 is intended to summarize the signals generated at the outputs of the comparison circuits 9 and the third 13 and the second 14 of the AND elements,

The second 7 and third 8 OR elements are designed to enable the third 8 and fourth 4 triggers to operate in cycles following the second, when trigger 2, which controls the operation of these triggers, is already reset to zero and does not allow trigger 3 to poll READY signal for phase F2 in the standby mode and trigger 4 of the HOLD signal according to the pulse of phase F2 in capture mode.

The first 9, second 10 and third 11 comparison circuits are designed to verify that the microprocessor correctly generates standby and capture signals (generated by the microprocessor at the WAIT and HLDA outputs, respectively) and similar signals.

formed by the control device at the outputs of triggers 4, 5 and 3.

Elements 13 and 14 are designed to transmit a mismatch signal from the outputs of the comparison circuits 10 and 11, respectively, at the required times, i.e. in exact accordance with the algorithm shown in Fig.6.

The first element 12 And is designed to reset the second trigger 2 v. Zero in each machine cycle of the microprocessor. Zeroing the second trigger is carried out in the cycle following the second cycle, according to the clock pulse Fr .:

 The HE15 element is for converting a READY signal into an inverse signal. This allows the readiness signal in state 1 at the output of the inverter to be identified as a standby request signal, and in state O, as a no request signal.

Consider the operation of the device. It is characterized by three modes of operation (in accordance with the algorithm shown in Fig.6):;

1. Control of the standby mode (see figure 2, 6) ;. .

2. Control of the capture mode in the read and write or write and output cycles (see Fig. 3, Fig. 4, Fig. 6); . 3. Control of standby and capture modes while simultaneously requesting (see FIG. 5, FIG. 6); .;

The device operates as follows. :. ..:; ::; :. .-,. In the initial state, all memory elements are in the zero state (reset circuits in O are not shown conditionally).

In the first mode (see Fig. 2, Fig. 6), in each machine cycle along the trailing edge of the SYNC signal received at input 16 of the device (see Fig. 2), trigger 2 is activated and is set to state 1 (time t2 in Fig. 2) and thereby enabling the recording of the READY signal (output 15 in Fig. 2) along the trailing edge of the pulse of phase F2 of clock cycle T2. If there is a wait request signal READY 1. Trigger 3 is set to a single state (time t, Fig. 2), generating at its direct output a copy of the wait state confirmation signal, similar to the signal generated by the microprocessor at the WAIT output. The single state of trigger 3 through element 7 OR confirms the enable signal for recording information from the READY output at input V of trigger 3. while the second trigger2, which previously enabled operation5

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of trigger 3, is set to the zero state on the leading edge of the pulse of phase FI in the cycle following the cycle T2 (see FIG. 2).

Thus, due to a single signal at the output of the OR element 7, trigger 3 polls the READY signal in each clock cycle Tw (standby clock cycles) according to the phase clock clock Fa. If the READY 1 signal disappears, which corresponds to the removal of the waiting request, the trigger 3 is set to the zero state on the trailing edge of the pulse of phase F2 (moment t.4 see Fig. 2), blocking its operation until the next clock cycle T2 (due to zero the signal at the output of the element 7 OR, the time ts in figure 2). Setting trigger 3 to zero mode simulates the microprocessor waking up from the standby state and the corresponding setting of the zero level of the wait acknowledgment signal. At a similar WAIT output of the microprocessor, a zero signal is also generated at the leading edge of the pulse of phase FI. Thus, the output of trigger 3 and the output. trigger 3 and the output of the WAIT microprocessor, synchronous signals are generated, which are compared by comparison circuit 9. The comparison result is recorded in trigger 1 by the rear front of the FL phase pulse. The further propagation of signals at the outputs of the second 10 and third 11 comparison circuits in the standby mode is blocked by elements 13 and 14I. by means of a zero signal at inverse output 3 (time interval ti ... ts see Fig. 2). In the future, the operation of the device is similar to that discussed above.

If READY 1 is absent, trigger 3 will be set to O and the signal corresponding to the wait acknowledgment signal will not be generated, just as the microprocessor output signal WAIT will not be generated. In this case, trigger 1 will remain in the zero state (in case of correct operation).

In the second mode, when the microprocessor transitions to the capture state and exits from it (in the absence of a wait request), similar to the first mode in the second cycle 12, a single control pulse is generated at the direct output of trigger 2 (time interval ti. ..t4 Fig. 3, Fig. 4). This pulse enables the fourth trigger 4. which polls the HOLD signal on the back of the pulse of phase F2. In case of a request for capture (HOLD i),

at time point (see Fig. 3, 4), trigger 4 is set to a single state in the same way as the microprocessor announces the transition to the state of capture by the HLDA signal 1 set on the leading edge FI of tact T (see Fig. 3, 4). The single state of trigger 4 picks up the signal when it is continuously set to zero on the R-input of trigger 5. A feature of the KR580 IK80A microprocessor is the dependence of the transition to the capture state on the type of cycle performed. If a reading cycle or water has been performed, then the transition to the capture state is carried out in the cycle following T2, and if the recording or output cycle is performed in the cycle next to T2. This feature was taken into account in the operation of the device using trigger 5. In the read or input cycles when the signal DBIN 1, the HLDA microprocessor signal is compared with the signal generated at the output of trigger 4 (point in time, see fig. 3, see outputs 22 , 4). The comparison is ensured by the presence of the DBIW enable signal at the input of the 14I element, which passes the result of the comparison to the input of the OR element. The comparison result is recorded by trigger 1 at each trailing edge of the pulses of phase FI. In write or input cycles, the HLDA signal is compared with the signal generated at the output of trigger 5. Setting trigger 5 to a single state is carried out with a delay of one clock cycle, i.e. in the cycle following the TK (moment ts-figure 4). In this case, the DBIN signal is 0, and the comparison is carried out by the comparison circuit 10, since the AND element 14 is locked. During further operation in the capture clocks T, the HOLD signal is sampled by the trailing edge of the pulse of phase F2 by trigger 4. In case the capture request signal is released (HOLD-0), trigger 4 is set to the zero state (time ts - Fig. Zab - Fig. 4), setting the trigger 5 to zero with a certain delay equal to the trigger time. In both cases (in any cycles), the microprocessor exits from the capture state along the leading edge of the T1 clock cycle (see Fig. 3, 4, Fig. 6). The signal of the comparison result, coming through the elements 13 and 14, is fixed in the trigger 1 along the trailing edge of the clock pulse FI.

In the third mode, when state and hold requests are received simultaneously (relative to pulse F2 in step T2). the operation of the elements of the device is similar to the work in the first and second modes.

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The peculiarity is that the mode is first executed (waiting, and then capturing). This is ensured by the fact that in the standby mode, trigger 3 is in the single state (time interval t2 ... t3 of Fig. 5), blocking the state On its inverse output, the operation of trigger 5 and the transmission of comparison signals through elements 13 and 14I.

When signal O is removed from the inverse output of trigger 3 (at the end of the standby mode), the trigger 5 is set to a single state via so, as well as permission to transmit the comparison results through elements 13, 14 And, depending on the type of cycle. Further, the operation of the device is completely determined by the operation in the second mode.

It should be noted that when the device is operating at the outputs of elements 7 and 8 OR in a clock following T2 (see Fig. 2-4), short-term signal drops are possible due to the asynchronous actuation of triggers 2 and 3 (4). However, the influence of these transient processors on the operation of triggers 3 and 4 does not occur due to synchronization with signal F2.

Transients (see Fig. 5, interval t4 ... t5) are associated with the asynchrony of the compared WAIT signals at the output of trigger 3. HLDA and at the outputs of trigger 4 and 5, can lead to false triggering of trigger 1. In order to eliminate this of the effect, it is necessary to choose the element performance, proceeding from the fact that the operation of the longest signal comparison chain should end by the time the trailing edge of the sync pulse FI arrives, i.e. the condition must be fulfilled:

TF1 TDCV + TM2 + 2 + P,

where gr- | - the duration of the clock FI; TDCV, M2 TE - 1 response time of the elements respectively: DCV trigger, modulo 2 adder, AND and OR elements.

Formula of the invention

A device for controlling a microprocessor system, comprising a first comparison circuit, first to third OR elements, first and second elements I. first trigger, wherein the output of the first comparison circuit is connected to the first input of the first OR element, the output of the first trigger is a control output of the device.

characterized in that, in order to increase the reliability of the control, second to fifth triggers, a third AND element, an NOT element, a second and a third comparison circuit are additionally introduced into it, the first input of the device being connected to the output of the start signal of the machine cycle of the controlled microprocessor system, with a single input and a second trigger clock, an inverse input of the first element AND, the second input of the device is connected to the first synchronization output of the controlled microprocessor system, with the synchronization input of the first three the first input of the first element AND, the output of which is connected to the installation input of the second trigger, the zero inputs of the first and second triggers are connected to the bus of zero potential. monitored microprocessor system, the third input of the device is connected to the status confirmation output of the monitored microprocessor system, and with the first input of the first comparison circuit, the fourth input of the device is connected to the request input for the monitored microprocessor system and through the element NOT with the information input of the third trigger, my output of which is connected to the second input of the first comparison circuit, and the first input of the second OR element. the second input of which is connected to the direct output of the second trigger, the output of the second OR element is connected to the enable input of the third trigger, the fifth input of the device is connected to the second synchronization output of the controlled microprocessor system and synchronization inputs

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from the third to fifth triggers, the sixth input of the device is connected to the input of the request for capture of the controlled microprocessor system and the information input 5 of the fourth trigger, the direct output of which is connected to the first input of the third OR element, the second input of the third OR element is connected to the direct output of the second trigger , the output of the third OR element is 10 connected to the enable input of the fourth trigger, the direct output of which is connected to the first input of the third comparison circuit "and the information input of the fifth trigger, which allows input which is connected to the inverse output of the third trigger, the inverse output of the fourth trigger is connected to the installation input of the fifth trigger, the direct output of which is connected to the first input of the second comparison circuit, the second inputs of the second and third comparison circuits are connected to the seventh input of the device connected to the status confirmation output nor capture of a controlled microprocessor system, the eighth input of the device is connected to the output of the read signal of the controlled microprocessor system and the first inputs of the second and third ... And elements, the second inputs of the second and third - 30 of its elements And are connected respectively to the outputs of the second and third comparison circuits, the third inputs of the second and third elements And are connected to the inverse trigger output, the outputs of the second and third elements 35 are connected respectively, with the second and third inputs of the first OR element, the output of which is connected to a single input of the first trigger.

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