SU1267594A1 - Controlled pulse generator - Google Patents

Abstract

The invention can be used in devices of electronic computers and discrete control systems. The purpose of the invention is improving noise immunity and expanding the functionality of the device. Pulse generator contains registers 1, decoder 2, inverter 3, delay line 4, block 5 elements AND, element OR 6, Introduction of counter 7 pulses, trigger 8 mode, elements OR 9 and 10, inverter 11, element 12, prohibition element 13 of the element OR-HE 14 and the formation of new connections between the elements of the device synchronizes the moments of the entry of control codes and ensures the formation of a series of pulses. 2 Il.

Description

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CO 4 "The invention relates to a pulse technique and can be used in electronic computing devices and discrete control systems. The aim of the invention is to improve the noise immunity due to the synchronization of the moments of insertion of the control codes and the expansion of the functional capabilities of the controlled pulse generator due to the formation of a series of pulses. FIG. 1 shows a functional diagram of a controlled pulse generator; in fig. 2 - time diagrams of his work. The control pulse generator contains (FIG. 1) a register 1, the outputs of which are connected to the inputs of the descrambler 2, the inverter 3, the delay line 4 whose outlets are connected to the first inputs of the block 5 of elements And, the outputs of the decoder 2 are connected to the second inputs of the block 5 of elements And The outputs of which through the element OR 6 are connected to the input of the inverter 3, the output of which is the output bus of the device, pulse counter 7, mode trigger 8, elements OR 9 and 10, inverto 11, element 12, prohibition element. 13 and the OR-NOT 14 element, the inputs of the OR-NO 14 element are connected to the taps of the delay line 4, and the output is connected to the direct INPUT of the prohibition element 13, the inverse input of the prohibition element 13 is connected to the forward output of the trigger 8, whose single input is the first control bus 15 of the device, and the zero input is the second control bus 16 of the device, the setup inputs of the register 1 are connected to the information buses 17 of the device, the first input of the element OR 9 is the input bus 18 Starting the device, the second input of the element OR 9 connected to the output of the inverter 11, and the third in q OR 9 connected to the output member 13 ban; the output of the OR element 9 is connected to the synchronization inputs of the register 1 and the counter 7, the installation inputs of which are connected to the device information buses 19, and the subtractive input is connected to the output of the AND 12 element, the first input of the AND 12 element is sent to the forward output of the trigger 8, and the second to the input. delay line 4, the outputs of the counter 7 are connected to the inputs of the element OR 1C, the output of which is connected to the input of the inverter 941 11 and the third inputs of the block 5 of the elements I. The time diagram of the controlled generator (Fig. 2) is shown only for the case of generation Periodic oscillations with a repetition period T, Tj and TI, where - the first section of the delay time of the delay line 4; tjAj is the delay time of the first two sections of the delay line 4; delay time m sections of the delay line 4; ti and t4 - generator start up times for generating pulses with a tracking period t - generator start up time for generating pulses with a tracking period T t 3 - generator start up time for generating pulses with tracking periods - the default maximum switching time of register 1 and decoder 2. In the original The state at the output of inverter 3 is a constant high potential. The device operates in the mode of periodic oscillations of a given duration and in the mode of setting a series of pulses, which are set using trigger 8, when its zero input is excited via bus 16, the mode of periodic oscillations of a given duration is set, and the single input on bus 15 is set up in a series of pulses. In the periodic oscillation mode, the initial input of the element OR 9 is given a signal of the device’s initial start-up via bus 18, which from its output goes to the synchronizing inputs of register 1 and counter 7, and their installation inputs receive codes through the information buses 17 and 19 of the device. To generate pulses with a period of, for example, T, a register must be entered in register 1, in which the first output of decoder 2 will be excited (Fig. 2 °). In this case, it is enough to enter any code other than zero into counter 7. The positive voltage drop from the first output of the decoder 2 is fed to the second input of the first element I of block 5, to the first input of which a positive potential is fed from the first retraction of the delay line 4 (Fig 2g) and to the third input is a positive potential from the output the element OR 10, due to the code recorded in the counter 7, other than zero. The positive voltage passed through the first element of block 5 and the element of OR 6 is inverted by the inverter 3, and at its output it appears with a negative voltage drop with a back front of the output pulses of the generator. This negative differential arrives at the input of the delay 4 and over time, it appears at its first tap and the first input of the first element AND of block 5. Since the AND element of block 5 is closed, a low voltage level is formed at its output (the rest the elements of AND block 5 are also closed), which through the element OR 6 enters the input of the inverter 3, where it is inverted. Thus, the leading edge of the output pulses is formed. A positive differential from the output of the inverter 3 is again fed to the input of delay 4 and after a time t ,, ftj appears at its first tap and first input of the first element And block 5, then goes through it, again inverted, and so on . Thus, the device will generate pulses with a period of following T. If it is necessary to generate pulses with a different period, for example T, in register 1, such a code should be entered so that the second output of decoder 2 is excited (Fig. 7.6). For stable operation of the device, it is necessary that the code be entered in register 1 at time when all the outputs of the delay line 4 is present low potential. This moment is detected by the element OR-HE 14, at the output of which a positive voltage drop is generated, which arrives at the direct input of the prohibition element 13. At the inverse input of the prohibition element 13 at this time, the low potential comes from the direct output of the trigger 8. The resolving potential from the output prohibition element 13 through the third input of the element OR 9 enters the synchronization inputs of register 1 and counter 7, ensuring the entry of a new control code. So, at time tj, a new code will be entered into register 1 for generating pulses with a period of following Tj. After a period of time, the first element of AND 5 will have a control potential from the second output of the decoder 2 on OTKjiK 4eHF) biM, and F F TOPOM of the second element of the 5th unit WITS. Now the first two sections of the line will participate in the work. xk 4, with a delay time t ,, jt, (fig. 2d, d). As a result, pulses with a period of following T 2t ,,, j Tj will be generated at the output of the generator until a new control code is entered into register 1. The generation of pulses with the maximum period T, 2t ,, takes place when a code is entered in register 1, at which the th -th output of the decoder 2 will be excited (Fig. 2b). In this case, all the m sections of the delay line 4, the total delay time of which is equal to t (Fig. 2 g, d, e, W), will be included in the feedback circuit with the help of the And block 5 element. To stop the generator, a zero code is entered into register 1, in which the zero output of decoder 2 is excited, therefore all elements AND of block 5, which are used to connect sections of delay line 4, are disconnected and a constant high potential on the output bus of the device (inverter 3) . To put the device into operation for generating a series of bounded pulse sequences with a predetermined follow-up period, a single trigger input 8 is excited via bus 15, the forward output of which sets a high potential. At the first input of the element OR 9, the initial start signal is again supplied to bus 18, which then goes to the synchronization inputs of register 1 and counter 7, thus ensuring that the necessary codes are entered through the installation inputs. In this case, a register is entered into register 1, which provides the necessary period of the generated pulses, and their number 7 in the specified sequence (series) in counter 7. After installing the code in register 1, the device begins to generate a sequence of pulses with a follow-up period defined by the recorded code. During the formation of the leading edge of the next pulse, a positive voltage drop from the output

the inverter 3 is fed to the second input of the element 12, to the first input of which a high potential is supplied from the direct output of the trigger 8.

The signal from the output of the element And 12 is fed to the subtractive input of counter 7 and reduces its contents by one.

the output bus of the device (inverter 3) again reduces the counter contents by one.

This continues until the number of pulses in the sequence reaches a predetermined number. At this point, counter 7 is zero, resulting in a negative voltage drop at the output of the OR 10, which will turn off all elements AND block 5. The generator stops working.

At the same time, the signal from the output of the element OR 10 through the inverter 11 and are turned on 25

The input element OR 9 enters the synchronization inputs of register .1 and counter 7, allowing new codes to be written to them. At this cycle of operation of the device in the formation of a series of pulses ends.

In the next cycle, you can change the number of generated pulses of the same duration, or set a new period for them to follow.

Changing the pulse duration in one series is not allowed. For this purpose, the generator provides for blocking the recording of code in register 1 until the end of the device operation cycle (generation of a series). In this case, when all outputs of the delay line 4 have a low potential, the signal from the output of the OR-NOT 14 element will not pass through the inhibit element 13 and then through the third input of the OR element 9 to the clock inputs of register 1 and counter 7, since the inverse input prohibition element 1-3 at this time comes a high potential from the direct output of the trigger 8.

About ORT e and

Control of the pulse generator containing the first inverter, the output of which is connected to the input of the delay line, the taps of which are connected to the first inputs of the block of elements AND whose outputs through the first element OR are connected to the input of the first inverter, the output of which is connected to the output bus of the device, the second inputs of the block elements And are connected to the outputs of the decoder, the inputs of which are connected to the outputs of the register, the installation inputs of which are connected to the first information buses of the device, characterized in that, in order to noise immunity and expansion of functionality, a pulse counter, a mode trigger, a second and a third OR elements, a second inverter, an AND element, a prohibition element and an OR-NOT element, whose inputs are connected to the VieHTB prohibition input, the inverse input of which is connected are entered into it with the direct output of the mode trigger, whose single input is connected to the first control bus of the device, and the zero input is connected to the second control bus of the device, the first input of the second element OR is connected to the startup bus, second the input of the second element OR is connected to the output of the second inverter, the third input of the second element OR is connected to the output of the inhibit element, and the output of the second element OR is connected to the synchronization inputs of the register and pulse counter, the installation inputs of which are connected to the second information buses of the device, and the subtractive input is connected to the output element is And, perk to the taps of the delay line, and the input of which is connected to the direct output of the mode trigger, and the second input is connected to the input of the delay line, the outputs of the pulse counter are connected to the input am third OR gate, whose output is connected to the second inverter WMOs The house and third inputs of the block elements I.

FIG. 2

Claims (1)

A controlled pulse generator containing the first inverter, the output of which is connected to the input of the delay line, the taps of which are connected to the first inputs of the block of AND elements, whose outputs through the first element OR are connected to the input of the first inverter, the output of which is connected to the output bus of the device, the second inputs of the block And elements are connected to the outputs of the decoder, the inputs of which are connected to the outputs of the register, the installation inputs of which are connected to the first information buses of the device, characterized in that, in order to increase the resiliency and enhanced functionality, it introduced a pulse counter, a mode trigger, the second and third elements OR, the second inverter, the element AND, the inhibit element and the OR-NOT element, the inputs of which are connected to the taps of the delay line, and the output is connected to the direct input 'a ban, the inverse input of which is connected to the direct output of a mode trigger, a single input of which is connected to the first control bus of the device, and the zero input is connected to the second control bus of the device, the first input of the second OR element under is connected to the start bus, the second input of the second OR element is connected to the output of the second inverter, the third input of the second OR element is connected to the output of the inhibit element, and the output of the second OR element is connected to the synchronization inputs of the register and pulse counter, the installation inputs of which are connected to the second information buses of the device and the subtracting input is connected to the output of the AND element, the first input of which is connected to the direct output of the mode trigger, and the second input is connected to the input of the delay line, the outputs of the pulse counter are connected to the input am third OR gate, whose output is connected to an input of the second inverter and a third input block elements I.