RU1798897C - Ms-flip-flop - Google Patents

Abstract

The invention relates to pulse technology and can be used in automatic and computing devices. SUMMARY OF THE INVENTION: The M-S trigger comprises an input transistor, an additional transistor, first and second transistors of a first current switch of the first arm. the first and second transistors of the second current switch of the first shoulder, the first and second transistors of the third current switch of the first shoulder, the first auxiliary transistor, the first and second transistors of the first current switch of the second shoulder, the first and second transistors of the second current switch of the second shoulder, the first and second transistors of the third switch second arm current, second auxiliary transistor, 3 current sources, 2 additional current sources, 2 additional resistors, 2 collector resistors, 3 res ora current sources, two additional resistor current sources, data input, clock input, output, bus 3 the reference voltage supply bus 2. 1 ill. (L

Description

The invention relates to pulse technology, and can be used in automatic and computing devices.

The aim of the invention is to increase the noise immunity.

The drawing shows a diagram of the M-S-trigger.

MS-trigger contains the first and second arm, each of which contains three current switches on transistors, an input transistor 1, an additional input transistor 2. The first current switch of the first arm contains the first and second transistors 3, 4, the second current switch - the first and second transistors 5, 6, the third current switch is the first and second transistors 7, 8 MS-trigger has a first auxiliary transistor 9.

The first current switch of the second arm contains the first and second transistors 1.0.1 T, the second current switch contains the first and second transistors 12, 13, the third current switch contains the first and second transistors 14, 15. The M-S trigger has a second auxiliary transistor 16,

The M-S trigger contains three current sources 17, 18, 19 and the first and second additional current sources 20, 21, the first and second additional resistors 22.23, the first and second collector resistors 24.25. The first, second and third current sources 17, 18, 19 have resistors 26, 27, 28.

The first and second additional current sources have resistors 29, 30.

The M-S trigger has an informational input 31-1. synchronization input 31-2, output

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32-1 M-S-flip-flop, the first, second, third voltage rails 33-1, 33-2, 33-3, the first and second power rail 3.4-1, 34-2.

The base of the input transistor 1 is connected to the synchronization input 31-2, the collector to the first power supply bus 34-1, the emitter to the emitter of the additional input transistor 2 and through the first current source 17 to the second power supply bus 34-2. The base of the auxiliary input transistor 2 is connected to the first reference voltage bus 33-1, the collector to the first power supply bus 34t 1 through a resistor divider on the first and second additional resistors 22, 23, the middle terminal of which is connected to the base of the first auxiliary transistor

9. a collector which is connected to a first power supply bus 34-1, and an emitter through a first additional current source 19 to a second power supply bus 34-2. PIA.

Collectors of the first transistors 3, 5,

10. The 12 first and second current switches of the first and second arm are connected to the first power supply bus 34-1, to which collectors of the second transistors 4, b, 11.13 of the first and second current switches of the first are connected through the first and second collector resistors 24.25 and the second shoulder.

The base of the first transistor 3 of the first current switch of the first shoulder is connected to the information input 31-1, the base of the first transistor 10 of the first current switch of the second shoulder is connected to the base of the first transistor 5 of the second current switch of the first shoulder and with the collector of the second transistor 4 of the first current switch of the first shoulder, the base which is connected to the base of the second transistor 6 of the second current switch of the first shoulder and to the first reference voltage bus 33-1, to which the bases of the second transistors 11,13 of the first and second are connected ereklyuchatel current of the second arm, which is connected to the collectors of the first base of the transistor 12 of the second switch current output and the second arm 32-1 M-S-flip-flop.

The emitters of the first and second transistors 3, 4 of the first current switch of the first arm are connected to the collector of the first transistor 7 of the third current switch of the first arm. The emitters of the first and second transistors 5, b of the second current switch of the first arm are connected to the collector of the second transistor 8 of the third switch of the first switch.

The base of the first transistor 7 of the third current switch of the first arm is connected to the second reference voltage bus 33-2 to which the base is connected

the second transistor 15 of the third second arm current switch, the collector of which is connected to the emitters of the first and second transistors 12, 13 of the second second arm current switch.

The collector of the first transistor 14 of the third current switch of the second arm is connected to the emitters of the first and second transistors 10.11 of the first current switch of the second arm.

The control inputs of the current sources 17, 18, 19, 20, 21 are connected to the third reference voltage bus 33-3.

The collector of the second auxiliary transistor 16 is connected to the first bus

34-1 power supply, the base - with the collector of the additional input transistor 2, the emitter through the second additional current source 20 with the second bus 5-2 of the power source and with the base of the first transistor

14 of the third current switch of the second arm.

The M-S trigger works as follows.

When a synchronizing pulse is applied to transistor 1 from a resistive divider on resistors 22, 23, voltage pulses are removed, which are transmitted through emitter followers on transistors 9. 16 to the bases of transistors 8, 14. The signal at the base of transistor 8 corresponds to signal C1 figure 1, and the signal based on the transistor 14 corresponds to the signal C2.

Due to the different magnitude of the amplitude of pulses 01, C2, the moments when these signals cross the level of the reference voltage on bus 33-2 are different: the negative edge of signal C2 crosses the level on bus 33-2 by the value Ati earlier than signal C1, positive

the front of signal C2 is At2 later than signal C1. This leads to the fact that on the negative edge of the clock signal at first, the slave (output) D-latch switches from the mode of receiving information to the mode

storage, and after a time interval D ti, the leading (input) D-latch switches from the storage mode to the information receiving mode. On the second SI front, the trigger works similarly, only

D-latches work in reverse order. This provides reliable protection for the operation of the M-S trigger, as information from the trigger input cannot pass through two D-latches to the output due to the fact that the modes

The reception of information at both D-latches is spaced apart in time by the value of Ati (Ata), and the value of Ati (At2) is determined by the values of resistors 22 and 23. Using the proposed devices provides the following advantage over existing devices: improved noise immunity at the synchronization input.

Claims (1)

The formula invents an MS trigger containing the first and second arms, each of which is made with three current switches on transistors, two auxiliary transistors, three current sources and an input transistor, the base of which is connected to the synchronization input, a collector - with the first power bus, emitter - through the first current source with the second power bus, the collectors of the first transistors of the first and second current switches of the first and second arm are connected to the first power bus, to which through the first and second collector resistor the collectors of the second transistors of the first and second current switches of the first and second arms are connected, the base of the first transistor of the second current switch of the first shoulder is connected to the information input, the base of the first transistor of the first current switch of the second shoulder is connected to the base of the first transistor of the second current switch of the first shoulder and the collector of the second transistor of the first current switch of the first arm, the base of which is connected to the base of the second transistor of the second current switch of the first arm and the first the second reference voltage bus, to which the bases of the second transistors of the first and second current switches of the second arm are connected, the collectors of which are connected to the base of the first transistor of the second current switch of the second arm and the output of the MS flip-flop, the emitters of the first and second transistors of the first current switch the first arm are connected to the collector of the first transistor of the third current switch of the first shoulder, the emitters of the first and second transistors of the second current switch of the first the shoulders are connected to the collector of the second transistor of the third current switch of the first shoulder, the base of the first transistor of the third current switch of the first shoulder is connected to the second reference voltage bus to which the base of the second transistor of the third current switch of the second shoulder is connected, the collector of which is connected. with the emitters of the first and second transistors of the second current switch of the second shoulder, the collector of the first transistor of the third current switch of the second shoulder is connected to the emitters of the first and second transistors of the first current switch of the second shoulder, the emitters of the first and second transistors of the third current switch of the first shoulder are connected through a second current source with a second power bus, to which emitters of the first and second transistors of the third current switch of the second player are also connected via a third current source a, the control inputs of the first, second, and third current sources are connected to the third reference voltage bus, with the exception of the fact that, in order to increase noise immunity, an additional input transistor, two additional sources are introduced into it current and a resistor divider on two additional resistors, with the emitter of the additional input transistor connected to the emitter of the input transistor, the base with the first voltage reference bus, the collector with the first power bus through the resistor divider on the first and second additional resistors, the middle terminal of which is connected to the base of the first auxiliary transistor, the collector of which is connected to the first circuit. power supply, emitter - through the first additional current source with a second power line, the collector of the second auxiliary transistor is connected to the first power line, the base - with the collector of the additional input transistor, the emitter - through the second additional current source with the second power line, and the control inputs first and second additional current sources are connected to a third voltage reference bus. and / G -Sl jj-z Ai. C2 4iz