RU1778900C - Dc voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in secondary power sources. An object of the invention is to increase the reliability of a converter device. The converter is made in the form of unregulated push-pull converters 1 with a constant current output, connected to each other in parallel at the input and output. The control unit includes a clock pulse generator 9, a pulse distributor 10 and N identical nodes for generating control signals containing two collector voltage sensors 23, 24, an EXCLUSIVE OR element 25 and two AND elements 17, 20, outputs connected to the control the input inputs of the transistor switches 15, 16. In contrast to the known one, the converter is equipped with two delay elements 11, 12, and each control signal generating unit is equipped with a HE 26 element, a 2IS element

Description

ME 28. element 2 OR 32 and RS-trigger 29. The pulse distributor is made in the form of 2N D-triggers 10, interconnected in a special way. The output of the EXCLUSIVE OR 25 element is connected to the input of the element NOT 26, the output of which is connected to the input of the element 2 AND NOT 28. The second input of this element is connected to the output of the element 2 OR 32, and the output to the installation input RS of trigger 29. Installation R

the input of the RS flip-flop 29 is connected to the output of the second delay element 12. and the output Q is connected to the second inputs of the elements AND 17, 20, the first inputs of which are additionally connected to the inputs of the element 2 OR 32. The control unit made in this way ensures that the converter protection circuit operates without delay , which increases the reliability of its work, 3 ill.

The invention relates to the field of electrical engineering and can be used in converting equipment devices and secondary power sources

A push-pull converter is known that is designed according to a parallel circuit of push-pull unregulated converting cells (ПЯ), for example, operating with a mutual phase shift, each of which contains a transformer, transistor switches and a rectifier bridge with a common capacitive filter. Such inclusion of the converter cells can significantly reduce the energy consumption of the output capacitor filter. The disadvantage of switching on the converter cells is that the processes of absorption of excess charge in the diodes of the output rectifiers only accelerate (their duration decreases, but the amplitude of the reverse current through the blocking diodes increases), which causes a pulsed current overload of the rectifier diodes and transistor switches both commuting and all others and reduces efficiency and reliability.

The closest technical solution is the voltage converter, made according to the differential circuit of a push-pull inverter, the control inputs of the power transistor switches connected to the outputs of two elements of type AND (AND-NOT). the first inputs of which are connected to the antiphase outputs of a clock pulse generator of a rectangular shape such as a meander, and the second and third inputs are pairwise combined and connected to the capacitor plates. One of the capacitor plates is connected to the output of the logical control signal source, and the other of its capacitor plates is connected through the resistor to the output of the EXCLUSIVE OR element. Element Inputs

EXCLUSIVE OR connected to the fourth inputs of AND elements (AND NOT) and connected to the outputs of two identical measuring and matching elements,

the input of each of which is connected to the connection point of the primary half-winding of the transformer and the power transistor switch. The control inputs of the power transistor switches are connected to the outputs

elements 4I.

The disadvantage of this voltage converter is the fundamental delay in the response of the protection circuit due to the RC circuit in the output

element chains EXCLUSIVE OR. In addition, the converter loses operability when introducing zero pauses in the output voltage.

An object of the invention is to increase the reliability of a voltage converter.

Known DC / DC converter, contains N non-adjustable push-pull converters with

DC output connected in parallel to each other at the input and output, each of which includes a transformer and two power transistor switches. The control unit includes a clock generator, a pulse distributor and N identical control signal generating units. These nodes include collector voltage sensors of power transistor switches,

outputs connected to the inputs of an EXCLUSIVE OR element and two AND elements, the first inputs of which are connected to two control inputs of an unregulated push-pull converter, and the outputs

connected to the control inputs of its power transistor switches. In contrast to the known, two delay elements are introduced into the converter, each control signal generating unit is equipped with an element NOT, an element 2 OR, an element 2AND, and an RS trigger. The pulse distributor is made in the form of 2N D triggers, counting C inputs of which are connected to the output of the clock pulse generator, the output Q of each i-ro D-trigger, where 1 1, 2 .... N is connected to the input D i + 1- ro D-flip-flop and the first control input of i-ro non-adjustable push-pull converter. The output Q N + i-ro of the D-flip-flop is connected to the input D N + H-1st of the D-flip-flop and the second control input of the i-ro inverter. The output Q of the last 2N D-trigger is connected to the input D of the first D-trigger. The installation inputs R of the first N-1 D-flip-flops are connected to the installation inputs S of the subsequent N-H D-flip-flops and are connected to the output of the first delay element combined with the input of the second delay element. The output of the EXCLUSIVE OR element through the element is NOT connected to the first input of the element 2 AND NOT, the second input of which is connected to the output of the element 2 OR, and the output to the installation S input of the RS trigger, the installation R input of which is connected to the output of the second delay element, The Q RS output of the trigger is combined with the second inputs of AND elements (2AND), the first inputs of which are additionally connected to the inputs of the 2OR element.

The invention is illustrated by the drawings, in which: FIG. 1 is a circuit diagram of a DC / DC converter; FIG. 2 is a schematic diagram of an unregulated push-pull converter with a constant current output; in FIG. 3 are timing diagrams explaining the operation principle of the converter.

The DC / DC converter (see Fig. 1) is made in the form of N uncontrolled push-pull converters 1 with a DC output connected to the input to the common power buses 2, 3. The outputs of all non-adjustable push-pull converters 1 are connected to common load terminals 4, 5. Each non-adjustable push-pull converter 1 has two control inputs 6, 7 and installation input 8. The converter control unit includes a clock generator 9 connected to counting C inputs 2N D- flip-flops 10. The output Q of the i-ro D-flip-flop 10 is connected to the input D i + 1-ro of the D-flip-flop 10 and the control input 6 of the i-ro non-adjustable push-pull converter 1. The output Q of the NH-ro D-flip-flop 10 is connected to the input D N + i + 1-ro D-flip-flop 10 and control input 7 then As for the uncontrolled push-pull 5th converter 1. The output Q 2N-ro of the D-trigger 10 is connected to the input D of the first D-trigger 10 and the input 7 of the N-ro of the uncontrolled push-pull converter 1. The output of the delay element 11, which in the simplest case, can represent an integrating RC circuit, connected to the input of a similar delay element 12 and the inputs R of the first N-1 D-flip-flops 10 and the inputs S of the subsequent N + 1 D-flip-flops 10. Output

5 of the delay element 12 is connected to the installation inputs 8 of all non-adjustable push-pull converters 1. The power part of each non-adjustable push-pull converter 1 contains a transformer 13. rectifier bridge 14, two identical power transistor switches 15 and 16, and the primary winding of the transformer 13 and power transistor switches 15 and 16 are included by the known differential

circuit (midpoint circuit) of the inverter.

Transistor Control Inputs

keys 15 and 16 are connected respectively

to the outputs of two control elements 2INE 17 with control inputs 18, 19 and 20

0 control inputs 21, 22. The inputs of the collector voltage sensors 23 and 24 are connected to transistor switches 15 and 16, and their outputs are to the inputs of element 25 EXCLUSIVE AND-LI, whose output through element 5 is NOT 26 connected to input 27 of element 2I- NOT 28. The output of element 2I-NOT 28 is connected to the installation input S of the trigger 29, the installation input R of which is connected to the installation input 8

0 non-adjustable push-pull converter 1. The RS output of the trigger 29 is connected to the input 18 of the element 2I-NOT 17 and the input 21 of the element 2I-NOT 20. The input 19 of the element 2I-NOT 17 is combined with the input 30 of the element

5 OR 32 and is connected to the control input of the uncontrolled push-pull converter 1. Input 22 of the 2I-Н Е 20 element is connected to the input 33 of the OR element 32 and connected to the control input 6. Output

0 of the OR 32 element is connected to the input 34 of the 2N-NOT 28 element. Power transistor switches 15, 16 and collector voltage sensors 23,24 can be used of any type, for example, those described in 3.

5 Consider the operation of the converter After applying the supply voltage, the clock pulse generator 9 starts working. -For simplicity, we consider the option of parallel connection of three uncontrolled push-pull converters 1. From the output of the delay element 11, the pulse U11 sets the first two D-flip-flops 10 (N 3) and in the zero state, the subsequent (N + 1) four D-t riggers

10 (see figure 3). The clock pulses Ug overwrite information from one D-flip-flop 10 to another. As a result, at the outputs of the D-flip-flops 10, forming a circular shift register, a sequence of PULSE UQ-I, UQ2, Ud3 appear which are fed to the control inputs 6 and 7 of each unregulated push-pull converter 1. In this case, the first unregulated push-pull converter is fed pulses from the outputs Q of the first and fourth D-flip-flops 10 UQ-I and UGH.

In the time interval ti-t2, the power transistor switch 15 is unlocked. At time t2, current U, / 2 starts flowing through it (D is the reduced load current), since the first and second unregulated push-pull converters 1 are turned on at this time. on the collector of the transistor key 15 will be equal to UKH, and on the collector of the key 16 it will be (2EP - UKH). At time t3, the supply of the unlocking voltage to the base of the transistor switch 15 is stopped and the process of resorption of minority carriers begins. At the same time, the unlocking of one of the transistor switches of the third unregulated push-pull converter 1 starts. After it is fully unlocked, the current flowing through the open transistor switches of all three unregulated push-pull converters 1 will become equal to n / 3. At time t4, the process of resorption of minority carriers in the base of the transistor switch 15 of the first uncontrolled push-pull converter 1 ends and it closes, while the self-induction EMF appears in the primary winding of the transformer 13. The voltage at the collector of the transistor switch 15 will become approximately 2EP, and at the collector of the transistor switch 16-O. At the same time, both STKs will remain closed. When the unlocking voltage is applied to the base of the transistor switch 16, it will open and the voltage on its collector will become equal to UKH, and the current Гн / 3, since at that time one of the transistor switches of the second unregulated push-pull converter 1 will remain open due to the absorption of minority carriers at its base. After a time tf (tf is the duration of the voltage front of the transistor key), a high logic level is supplied from the output of the delay element through the setting input 8 to the input R of the trigger 29. The supply of the unit level U12 includes a protection circuit. The delay of the protection circuit activation is made

during transients at the time of turning on the DC / DC converter.

We consider the operation of the protection circuit for

when emitter followers 23, 24 are used as collector voltage sensors. If a certain threshold voltage is exceeded, a logical level appears at its input at the output

0 units (3). In the event of a malfunction in the converter circuit, for example, failure of one of the transistor switches 15 or 16 of a malfunction in the control unit, or for any 5 reasons, such as an overload, both power transistor switches 15, 16 will be simultaneously closed or open. This will cause the appearance of collector voltage sensors 23, 24,

0 associated with the inputs of the element EXCLUSIVE OR 25 identical logic levels, which will translate it into a zero state. As a result of this, the logical unit

5 which, through element 28, 2I-NB, will enter input S of flip-flop 29 and overturn it to the zero state. A zero level at the output Q of flip-flop 29 will cause the control elements 2I 17 and 20 to be blocked and a locking zero level will be generated at their outputs, which will cause the transistor switches to be locked 15. 16.

It is known that the breakdown of a semiconductor rp junction has two development stages: electrical non-destructive breakdown and thermal destructive breakdown, with the first stage necessarily preceding the second. As a result of the development of the first stage, the breakdown, the voltage at

0, the collector of the transistor decreases, which inevitably causes a corresponding current overload of another open transistor switch and its exit from the saturation mode. As a result, the protection circuit is triggered and both transistor switches are locked, preventing the electrical breakdown becoming irreversible thermal. Based on the foregoing, it is obvious that the proposed scheme

0 DC / DC converter implements the functions of automatic diagnostics of malfunctions of power circuit elements and protective locking of the STK, preventing their failure and necessity

5 of their subsequent replacement during the repair process. . After eliminating the causes of the protective shutdown of the converter, its operability is maintained and it can be turned on again by re-supplying the supply voltage.

In the time interval t / i-ts, during a pause when both transistor switches 15 and 16 are closed, as shown above, the voltages on the collectors of these switches change, which leads to the simultaneous appearance of the collector voltage sensors 23 and 24 identical logic levels, which in turn leads to the presence of zero pauses at the output of the element 25 EXCLUSIVE OR I. This can cause a false response of the protection circuit. To prevent this from happening, during a pause, the protection circuits are switched off by pulses 1Y of the zero level (see Fig. 3) supplied to the input 34 of the 2I-NOT 28 element, which are obtained by logically adding the control voltages 1) si and UQ4 supplied to the inputs 30 , 33 of the element 32. Thus, the protection circuit is ready for operation during the entire stroke of the converter.

Claims (1)

The claims DC / DC converter containing N uncontrolled push-pull converters with DC output connected in parallel to the input and output, each of which includes a transformer and two power transistor switches and a control unit including a clock generator, a pulse distributor and N identical nodes of the formation of control signals, including collector voltage sensors of said power transistor switches, connected by outputs to the inputs of the ISK element BUT OR and two AND elements, the first inputs of which are connected to two control inputs of the corresponding J i Јп- $ 2 sf / VH-s.5 Tb non-adjustable push-pull converter, and the outputs are connected to the control inputs of its power transistor switches, characterized in that for the purpose 5 to increase reliability, the converter control unit is provided with two delay elements, each control signal generating unit is equipped with an element NOT, an element 2 OR, an element 2 AND NOT and 10 by an RS flip-flop, and the aforementioned pulse distributor is designed as 2N D-flip-flops. counting C-inputs of which are connected to the output of the clock generator, Q output of each i-ro D-trigger, 15 where I 1,2N, is connected to the input of the D (1 + 1) -th D-flip-flop and the first control input of the i-ro uncontrolled push-pull converter, the output Q (N + i) -ro of the D-flip-flop is connected to the input D (N + i + 1) -ro of the D-flip-flop and 0 the second control 1- the uncontrolled push-pull converter, while the output Q of the last, 2N-ro D-flip-flop is connected to the input D of the first D-flip-flop, the installation R inputs of the first N-1 D-flip-flops and 5, the installation S-inputs of the remaining () D-flip-flops are connected to the output of the first delay element connected to the input of the second delay element, the output of the above element EXCLUSIVE OR MORE in each node for generating control signals connected to the input of the element NOT, the output connected to the first input element 2 AND NOT, the second input of which is connected to the output of element 2 5 OR, the output is to the installation S-input of the mentioned RS-flip-flop, the installation R-input of which is connected to the output of the second delay element, and the output Q - to the second inputs of the AND elements, the first inputs of which are additionally connected to the OR element 2.