RU176178U1 - Information signal processing device - Google Patents

Abstract

The claimed technical solution relates to information signal processing devices operating on autonomous power sources, and can be used to implement a wireless field device for controlling production processes.

The technical result is to increase energy efficiency.

The information signal processing device comprises a receiving antenna, an analog amplifier with AGC, a bandpass filter, a mixer, a harmonic signal generator, a low-pass filter, a 90 ° phase shifter, a matched filter, a threshold detector, a clock generator, a clock controller, a buffer, and a clock element. 1 of FIG.

Description

The claimed technical solution relates to information signal processing devices operating on autonomous power sources, and can be used to implement a wireless field device for controlling production processes.

It is known that modern devices for processing information signals contain elements whose calculation speed depends on the clock frequency generated by the clock generator. Such a generator with respect to the clocked element can be both external and part of the device itself. Among the clocked elements are, in particular, microcontrollers, programmable logic integrated circuits (FPGAs) and other similar elements.

A common feature of the work of clocked elements is the dependence of their performance (the number of computational operations per unit time) and power consumption (power consumption) on the value of the clock frequency.

So, with the receipt of each clock pulse of the clock frequency ƒ there is a change in the state of the element, providing the next computing operation. During time t, N computational operations can be performed: N ~ ƒ⋅t. From this ratio it follows that, for example, increasing the clock frequency improves the performance of the element (and devices based on it).

Moreover, over time t, the element consumes energy E ~ i ² ⋅t, where i is the average current consumed by the element. The value of this current is proportional to the clock frequency ƒ, since each change in the state of an element due to clocking requires a certain portion of charge. In this connection, E ~ ƒ ² ⋅t. From this ratio it follows that, for example, increasing the clock frequency increases the energy consumption of the element (and devices based on it).

The energy efficiency of an ε element is defined as the number of computational operations per unit of energy expended, and is inversely proportional to the clock frequency: ε = N / E ~ 1 / ƒ.

For field devices used to control production processes and operating on autonomous power supplies, efficient energy consumption is a critical feature. At the moment, there is a need to create a device of a class of devices for processing information signals with improved energy efficiency.

The prior art solutions are known that by lowering the clock frequency increase the energy efficiency of the element and devices based on it.

For example, a feedback transmitter is known, consisting of a clock generator, a multiplexer, a shift register, an impulse response controller, an output buffer, a constant current source, a main digital-to-analog converter connected to a controller, receiver, and phase-locked loop (Beukema T., Soma M. , Sekandr K.A. 6.4-Gb / s CMOS serdes core with feed-forward and decision-feedback equalization. // IEEE Journal of Solid-State Circuits, vol. 40, pp. 2633-2645, Dec. 2005.).

However, the disadvantage of such a known solution is the relatively low energy efficiency associated with the fact that the energy consumption of such a device is practically independent of the intensity of incoming information signals, and in the case of a low intensity of the latter, the energy consumption of the device remains almost the same as in the case of high. In other words, at low intensities of information signals, a known device without energy processing of information carries out energy consumption.

The invention is known according to patent RU 2558609 "Transmitter with tracking feedback", published December 27, 2014. The technical result of the invention is to reduce the power consumption of the transmitter. The servo feedback transmitter contains a clock associated with phase-locked loop, a multiplexer connected to the controller, a shift register, an impulse response regulator, an impulse response regulator decoder, an output buffer, a constant current source, and a main digital-to-analog converter, with an additional digital-to-analog converter and an additional digital-to-analog converter decoder associated with the receiver to provide control of the minimum the effective range of the differential voltage of the transmitter output signal from the current correction depth of the intersymbol interference of the receiver.

In this technical solution, the energy efficiency of the receiver is achieved due to the fact that the output buffer provides the minimum allowable swing of the differential voltage of the output signal that meets the specification specification and consumes the minimum required power for the current value of the correction depth of intersymbol interference. The disadvantage of this technical solution is that during the operation of the transmitter, the clock frequency generated by the clock generator is not controlled.

The closest analogue to the claimed solution is the “Information Signal Processing Device” (application for a patent of the Russian Federation for utility model No. 2016146585) containing a clock element, a clock generator, a clock controller and a buffer, the information and degree of filling of which is transmitted to the clock element, and the clock the element generates a control signal for the clock controller.

This technical solution allows to increase the energy efficiency of the clocked element and a device based on it by controlled reduction of the clock frequency on the clocked element depending on the intensity of information exchange. However, the disadvantage of this solution is the need to maintain the clock frequency on the clocked element in the absence of a useful signal on the air.

The technical problem is to create a device for processing information signals with high energy efficiency.

The technical result consists in increasing the energy efficiency of the information signal processing device.

The technical result is achieved due to the fact that the information signal processing device comprising a clock generator, a clock controller, the first input of which is connected to the output of the clock generator, a clock element, the first input of which is connected to the clock controller, and the output is connected to the second input of the clock controller frequency, a buffer whose output is connected to the second input of the clocked element,

additionally contains a receiving antenna, the input of which receives an analog input signal, an analog amplifier with automatic gain control (AGC), the input of which is connected to the output of the receiving antenna, a bandpass filter, the input of which is connected to the output of the analog amplifier with AGC, a mixer, the first input of which is connected with the output of the bandpass filter, a harmonic signal generator, the output of which is connected to the second input of the mixer, a low-pass filter, the input of which is connected to the output of the mixer, a 90 ° phase shifter, input which is connected to the first output of the low-pass filter, a matched filter, the first input of which is connected to the output of the phase shifter by 90 °, and the second input is connected to the second output of the low-pass filter, the third output of which is connected to the input of the buffer, a threshold detector, the input of which is connected to the output of the matched filter , and the output is connected to the third input of the clock controller.

The advantage of the proposed technical solution is a controlled reduction, including the complete shutdown of the clock frequency of the digital processing units of information signals at the channel and network level interfaces, depending on the intensity of information exchange between the field device and the access point.

The claimed technical solution is illustrated by the drawing, where:

FIG. - structural diagram of a device for processing information signals.

The claimed technical solution contains the following reference position in the drawing:

1 - receiving antenna;

2 - analog amplifier with AGC;

3 - band-pass filter;

4 - mixer;

5 - harmonic signal generator;

6 - low-pass filter;

7 - phase shifter 90 °;

8 - matched filter;

9 - threshold detector;

10 - clock generator;

11 - clock speed controller;

12 - buffer;

13 - clocked element.

A device for processing information signals operates as follows.

The analog input signal is fed to the input of the receiving antenna 1, from the output of which the signal is transmitted to the input of an analog amplifier with AGC 2, which allows amplifying the input signal. From the output of amplifier 2, the signal is fed to the input of a bandpass filter 3, which provides the selectivity of determining the presence of an information signal in the required frequency band. From the output of filter 3, the signal goes to the first input of mixer 4. The second input of mixer 4 receives a harmonic signal of a priori frequency from the output of the harmonic signal generator. The mixer 4 provides a shift of the signal spectrum from the operating frequency to 0. From the output of the mixer 4, the signal is fed to the input of a low-pass filter 5, which allows to get rid of the high-frequency spurious components of the signal.

Then the signal from the first output of the low-pass filter 6 is fed to the input of the phase shifter 90 ° 7. The phase shifter 90 ° 7 allows you to generate a coherent component of the signal, which from the output of the phase shifter 90 ° 7 goes to the first input of the matched filter 8. From the second output of the low-pass filter 6 the signal goes to the second input of the matched filter 8. The matched filter 8 allows you to detect the presence of a coherent signal and generate an analog output signal of variable amplitude. From the output of the filter 8, the signal is fed to the input of the threshold detector 9, which allows you to detect the presence of the beginning of the useful signal in the receiving path.

The clock generator 10 generates a constant frequency clock in a continuous mode, which are fed to the first input of the clock controller 11.

Each input signal entering the receiving path is transmitted from the third output of the low-pass filter 6 to the input of the buffer 12. Information about the degree of filling of the buffer 12, namely, the fill signal of the buffer 12 is supplied to the second input of the clocked element 13 from the output of the buffer 12. Based on this The clock element 13 determines the required value of the clock frequency and transmits a control signal to the second input of the clock controller 11. The clock frequency communicated to the clock element is calculated by multiplying the clock frequency second oscillator 10 by a factor given by the control signal.

In accordance with the clock frequency set by the controller 11, the input signal is supplied to the second input of the clock element 13 from the output of the buffer 12.

If the level of the input signal exceeds the threshold level set on the threshold detector 9, then the third input of the clock controller 11 from the input of the threshold detector 9 receives a signal to enable the transmission of the clock frequency to the clocked element. Otherwise, to the third input of the clock controller 11 from the input of the threshold detector 9 a signal prohibits the transmission of the clock frequency to the clocked element, which allows you to disable the clock frequency on the clocked element 13.

The clock frequency communicated to the clock element 13 determines the performance and energy efficiency of the clock element.

The size of the buffer 12 and the control range of the clock frequency values of the controller 11 are selected so that even with a strong change in the intensity of the input information signals, the buffer 12 does not overflow.

The proposed device for processing information signals, firstly, ensures the performance of the clocked element corresponding to the intensity of the incoming information signals, and secondly, provides the ability to turn off the clock frequency on the clocked element, which allows to increase the energy efficiency of the clocked element and the device based on it .

The patent was prepared as part of the work under the agreement between the Ministry of Education and Science of the Russian Federation and UrFU No. 14.578.21.0136 of October 27, 2015, PNIER RFMEFI57815X0136.

Claims (2)

An information signal processing device comprising a clock generator, a clock controller, the first input of which is connected to the output of the clock generator, a clock element, the first input of which is connected to the clock controller, and the output is connected to the second input of the clock controller, the buffer of which is connected to the second input of the clocked element, characterized in that additionally contains a receiving antenna, the input of which receives an analog input signal, an analog amplifier with automatic gain control (AGC), the input of which is connected to the output of the receiving antenna, a bandpass filter, the input of which is connected to the output of the analog amplifier with AGC, a mixer, the first input of which is connected with the output of the bandpass filter, a harmonic signal generator, the output of which is connected to the second input of the mixer, a low-pass filter, the input of which is connected to the output of the mixer, a 90 ° phase shifter, input which is connected to the first output of the low-pass filter, a matched filter, the first input of which is connected to the output of the phase shifter by 90 °, and the second input is connected to the second output of the low-pass filter, the third output of which is connected to the input of the buffer, a threshold detector, the input of which is connected to the output of the matched filter , and the output is connected to the third input of the clock controller.

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