KR101140962B1 - System and method of enabling a signal processing device in a relatively fast manner to process a low duty cycle signal - Google Patents

System and method of enabling a signal processing device in a relatively fast manner to process a low duty cycle signal Download PDF

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KR101140962B1
KR101140962B1 KR1020107022554A KR20107022554A KR101140962B1 KR 101140962 B1 KR101140962 B1 KR 101140962B1 KR 1020107022554 A KR1020107022554 A KR 1020107022554A KR 20107022554 A KR20107022554 A KR 20107022554A KR 101140962 B1 KR101140962 B1 KR 101140962B1
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circuit
complementary devices
input signal
inputs
processing
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KR20100121546A (en
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러셀 존 파그
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콸콤 인코포레이티드
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Priority to US12/045,595 priority Critical
Priority to US12/045,595 priority patent/US7812667B2/en
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Priority to PCT/US2008/057146 priority patent/WO2009114021A1/en
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/294Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/451Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/30Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
    • H03F2203/30099Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the pull transistor being gated by a switching element
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/30Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
    • H03F2203/30132Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the push transistor being gated by a switching element
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7206Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7215Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the input of the amplifier

Abstract

A system and method for improving the power efficiency of a receiver for low duty cycle applications. In one aspect, the receiver includes an LNA that can be enabled in a relatively quick manner to amplify the incoming signal as needed and then disabled to set the low noise amplifier (LNA) in a low power consumption mode. In particular, the LNA includes a pair of complementary devices and an enable circuit that is adapted to quickly cause the complementary devices to conduct substantially the same current. In another aspect, a bias voltage generation device is provided that uses the residual voltage from a previous operation to set a current bias voltage for an LNA. In particular, the apparatus includes a controller adapted to tune the adjustable capacitor with a capacitance based on the residual voltage applied to the fixed capacitor and to couple the capacitors together to set the bias voltage.

Description

SYSTEM AND METHOD OF ENABLING A SIGNAL PROCESSING DEVICE IN A RELATIVELY FAST MANNER TO PROCESS A LOW DUTY CYCLE SIGNAL}
The present invention relates generally to communication systems, and more particularly to a method and system for improving the power efficiency of a receiver for low duty cycle applications.
Limited power sources, such as battery operated communication devices, typically use techniques to consume relatively small amounts of power while providing the intended functionality. One increasing technique relates to receiving signals using pulse modulation techniques. This technique generally involves receiving information using low duty cycle pulses and operating in a low power mode during times of not receiving the pulses. Thus, in these devices, power efficiency is typically better than communication devices that continue to operate the receiver.
Since this type of reception technique is effective, one or more of the devices forming the receiver must be enabled and quickly enabled to be capable of effectively processing the low duty cycle pulses it receives. This allows the receiver to remain in a lower power consumption mode for a longer period of time and to be in a higher power consumption mode for the time required to process incoming pulses. Additionally, any residual potential energy remaining after one or more receiving devices have processed the pulse should be used to improve the power efficiency of the receiver.
Aspects of the invention include a first circuit having first and second complementary devices having inputs coupled together and outputs coupled together; And a second circuit comprising at least a portion coupled between the inputs and outputs of the complementary devices, wherein the second circuit is configured to be complementary when the first circuit is enabled. It is adapted to cause the devices to conduct substantially the same current. In another aspect, the additional circuitry is further adapted to set a voltage specific to the inputs or outputs of the complementary devices when the first circuitry is disabled. One aspect may include at least one element of the claims.
In another aspect, the second circuit is adapted to respond to a control signal for enabling or disabling the amplifier. The second circuit may be further configured to enable the first circuit within the specified constant time. Additionally, the second circuit can be adapted to add or remove charges to or from inputs of the complementary devices to cause the complementary devices to conduct substantially the same current. have. Also, a second circuit can be adapted to route charges to the inputs of the complementary devices to cause the complementary devices to conduct the same current. The complementary devices can include a p-channel field effect transistor (FET) and an n-channel FET. The device may be used as part of a receiver adapted to amplify an input signal having a partial spectrum of at least about 20% or more, a spectrum of at least about 500 MHz, or a spectrum of at least about 20% and a spectrum of at least about 500 MHz.
In another aspect, the invention relates to an apparatus for generating or setting a bias voltage for one or more components. In particular, the apparatus tunes first and second capacitive elements, and the second capacitive element to a capacitance based on a first voltage across the first capacitive element, and biases across the first capacitive element. And a controller adapted to couple the first capacitive element and the tuned second capacitive element to set a voltage. The controller may be further adapted to couple a source of a first voltage to the first capacitive element. The controller is further adapted to couple the first voltage source to the first capacitive element in response to a first timing signal and to tune the second capacitive element tuned in response to a second timing signal to the first. It is further adapted to couple to the capacitive element. In another aspect, an apparatus for processing an input signal may further include a third circuit adapted to set a voltage specific to the inputs or outputs of the complementary devices when the first circuit is disabled, The second and third circuits may be configured to enable the first circuit within a specified constant time.
Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
1 shows a block diagram of an exemplary receiver for low duty cycle applications in accordance with an aspect of the present invention.
2 shows a timing diagram of example signals generated and / or processed by an example receiver in accordance with another aspect of the present invention.
3 shows a schematic diagram of an exemplary low noise amplifier (LNA) including an example enable circuit in accordance with another aspect of the present invention.
4 shows a schematic diagram of another exemplary low noise amplifier (LNA) incorporating an exemplary enable circuit in accordance with another aspect of the present invention.
5 shows a schematic diagram of an exemplary bias voltage setting circuit according to another aspect of the present invention.
6 illustrates a timing diagram of example signals generated and / or processed by an exemplary bias voltage setting circuit according to another aspect of the present invention.
7 shows a block diagram of an exemplary communications device in accordance with another aspect of the present invention.
8 shows a block diagram of another exemplary communication device in accordance with another aspect of the present invention.
9A-D show timing diagrams of various pulse modulation techniques in accordance with another aspect of the present invention.
10 shows a block diagram of various communication devices in communication with each other over various channels in accordance with another aspect of the present invention.
11 shows a block diagram of an exemplary apparatus according to another aspect of the present invention.
Various aspects of the invention are described below. It is to be understood that the teachings herein may be embodied in a wide variety of forms and that any particular structure, function, or both disclosed herein is merely representative. Based on the teachings herein, one of ordinary skill in the art should understand that an aspect disclosed herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of aspects described herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects described herein. As an example of some of the above concepts, in some aspects the present invention relates to a system and method for improving the power efficiency of a receiver for low duty cycle applications. In one aspect, the receiver includes a low noise amplifier (LNA) that can be enabled in a relatively fast manner to amplify incoming data pulses and then disabled to set the LNA to a low power consumption mode. In particular, the LNA includes a pair of complementary devices and an enable circuit that is adapted to quickly cause the complementary devices to conduct substantially the same current. In another aspect, a bias voltage generation device is provided that uses the residual voltage from a previous operation to set a current bias voltage for an LNA. In particular, the apparatus includes a controller adapted to tune the adjustable capacitor to a capacitance based on the residual voltage and to couple the capacitors together to form a bias voltage for the LNA.
1 illustrates an example receiver 100 for low duty cycle applications in accordance with an aspect of the present invention. In summary, the receiver 100 enables the LNA in a relatively fast manner so that the LNA can amplify the incoming pulses, and disables the LNA in a relatively fast manner so that the LNA can be in a low power consumption mode again. It includes an enable circuit for a low noise amplifier (LNA) configured. Additionally, the receiver 100 includes a bias voltage setting circuit that uses the residual charges or voltage remaining from the previous operation of the LNA to set the bias voltage for subsequent operation of the LNA. These features help to improve the power efficiency of the receiver 100.
In particular, receiver 100 includes an LNA 106 that includes a timing generator 102, a bias voltage setting circuit 104, and an enable circuit for the LNA. LNA 106 receives and amplifies an input signal to produce an output signal. The input signal may be configured as one or more low duty cycle pulses. The LNA 106 is configured to enable the LNA in a relatively fast manner so that the LNA can amplify the input signal pulses, and to disable the LNA in a relatively fast manner so that the LNA can be in a low power consumption mode. Include the circuit internally.
The bias voltage setting circuit 104 is configured to set up the bias voltage Vdd_Lna for the LNA 106 by using the residual voltage or charges remaining in the external capacitor C remaining from the previous operation of the LNA 106. As will be discussed in more detail below, the timing generator 102 adjusts the enable and disable of the LNA 106 by the setup of the bias voltage Vdd_Lna and the use of individual bias voltage enable and LNA enable signals.
2 shows a timing diagram of example signals generated and / or processed by an example receiver 100 in accordance with another aspect of the present invention. According to the timing diagram, timing generator 102 first asserts a bias voltage enable signal to cause bias voltage setting circuit 104 to set up bias voltage Vdd_Lna for LNA 106. If LNA 106 has not been previously operated, there will be no residual voltage across external capacitor C. Accordingly, the bias voltage setting circuit 104 sets up the LNA bias voltage Vdd_Lna from zero volts. After the bias voltage Vdd_Lna is set, the bias voltage enable signal may be de-asserted before the LNA enable signal is asserted. However, as will be discussed in more detail below, it should be understood that the bias voltage enable signal may continue to be asserted throughout the receive window for the LNA 106.
After the LNA bias voltage Vdd_Lna is set up, the timing generator 102 asserts the LNA enable signal to enable the LNA 106 in a relatively fast manner to properly amplify the incoming signal pulses. The timing generator 102 continues to assert the LNA enable signal for a time sufficient to form a receive window or time interval for the input signal pulses to be received. As shown in this example, the input signal pulses are received relatively early in the first receive window, which can be interpreted in a particular manner, for example as a logic high. After the receive window, timing generator 102 stops asserting the bias voltage enable and LNA enable signals to disable LNA 106 and put it in a low power consumption mode. In this manner, the receiver 100 operates the LNA 106 in a relatively low power mode when no input signal is expected, and operates the LNA in a relatively high power mode when an input signal is expected. Is operated.
When it is time for the next receive cycle, timing generator 102 again asserts bias voltage enable signal to cause bias voltage setting circuit 104 to set up LNA bias voltage Vdd_Lna. In this example, since the LNA 106 has already been operated, the part between the external capacitor C that the voltage setting circuit 104 uses to set the LNA bias voltage Vdd_Lna for subsequent operation of the LNA 106. There may be residual voltage. Again, in this manner, receiver 100 is operated in a power efficient manner by utilizing the residual potential energy that may remain from previous operation to provide power to LNA 106. In accordance with the previous receive cycle, timing generator 102 then asserts the LNA enable signal to enable LNA 106 in a relatively fast manner to properly amplify the incoming signal pulse. In this example, the input incoming pulse is received relatively late in the second receive window, which can be interpreted in another particular way, such as a logic low.
3 illustrates a schematic diagram of an example low noise amplifier (LNA) 300 including an example enable circuit in accordance with another aspect of the present invention. LNA 300 may be an example of LNA 106 previously discussed. In particular, LNA 300 includes a pair of p-channel field effect transistors (FETs) M1 and M2, a pair of n-channel FETs M3 and M4, and a pair of resistors R1 and R2. ). The sources of p-channel FETs M1 and M2 are adapted to receive the bias voltage Vdd_Lna. Gates of the FETs M1 and M4 are adapted to receive the LNA enable signal discussed previously.
Gates of FETs M2 and M3 are adapted to receive an input signal. The output signal is generated at the drains of the FETs M3 and M2. The drain of the FET M1 is electrically coupled to the input signal terminal (and the gates of the FETs M2 and M3). Resistor R1 is electrically coupled between the source of FET M4 and the input signal terminals (gates of FETs M2 and M3) as an example of a controllable switch. Resistor R2 is electrically coupled between the drain of FET M4 and the output signal terminals (drains of FETs M2 and M3). The resistor R1, the FET M4 and the resistor R2 are examples of the second circuit. The source of FET M3 is electrically coupled to the Vss potential, which may be at a ground potential or at a more negative potential than Vdd_Lna.
In operation, LNA 300 may be in a low power consumption mode when the LNA enable signal is at a low logic level. The low logic level on the gate of FET M1 causes T (M1) as an example of the third circuit to be turned on. This causes the voltage Vdd_LNA to be applied to the gates of the FETs M2 and M3. As a result, this turns off FET M2 and turns on FET M3. Additionally, the low logic level of the LNA enable signal applied to the gate of FET M4 causes FET M4 to turn off. Therefore, in the low power consumption mode, the output signal terminal of the LNA 300 is at approximately Vss potential due to the turn on of the FET M3 and the turn off of the FET M2. The input signal terminal is at substantially Vdd_Lna potential due to the turn on of the FET M1 and is substantially separated from the output signal terminal due to the turn off of the FET M4.
When the LNA enable signal transitions from a low logic level to a high logic level, FET M1 is turned off and FET M4 is turned on. Before the LNA enable signal transitioned to the high logic level, the voltage on the input signal terminal was substantially at Vdd_Lna, and FET M3 was turned on, so turning on FET M4 caused the charges to be transferred from the input signal terminal to resistor R1. ), The source and the drain of the FET M4, the resistor R2, and the source and the drain of the FET M3. This causes the voltage at the input signal terminal to drop, resulting in the FET M2 conducting more current and the FET M3 conducting less current.
The voltage on the input signal terminal drops until the currents conducted by the FETs M2 and M3 reach a substantial equilibrium. In equilibrium, the voltage at the input signal terminal (eg, the gates of the FETs M2 and M3) is approximately Vdd_Lna / 2. When this occurs, both the FETs M2 and M3 are biased in substantially the same linear region and the FETs M2 and M3 as an example of the first circuit are complementary to amplify the input signals to produce an output signal. Act as enemy push-pull devices. Self-biasing of the FETs M2 and M3 when LNA enable signal transitions to a high logic level occur within a relatively small defined time interval allows the LNA 300 to quickly amplify the input signal when needed. To be set up. As discussed above, once the input signal is processed, the LNA enable signal is set to a low logic level to put the LNA 300 back into a low power consumption mode.
4 illustrates a schematic diagram of another exemplary low noise amplifier (LNA) 400 that includes an exemplary enable circuit in accordance with another aspect of the present invention. LNA 400 may be another example of LNA 106 discussed above. In particular, LNA 400 includes a p-channel FET M2, three (3) n-channel FETs M1, M3 and M4, a pair of resistors R1 and R2, and a pair of inverters. (I1 and I2). The source of the p-channel FET M2 is adapted to receive the bias voltage Vdd_Lna. The input of inverter I1 is adapted to receive the LNA enable signal discussed above.
Gates of FETs M2 and M3 are adapted to receive an input signal. The output signal is generated at the drains of the FETs M2 and M3. The drain of the FET M1 is electrically coupled to the input signal terminals (gates of the FETs M2 and M3). Resistor R1 is electrically coupled between the source of FET M4 and the input signal terminals (gates of FETs M2 and M3). Resistor R2 is electrically coupled between the drain of FET M4 and the output signal terminals (drains of FETs M2 and M3). The sources of FETs M1 and M3 are electrically coupled to Vss, which may be the ground potential or may be a negative potential more than Vdd_Lna. The output of inverter I1 is electrically coupled to the gate of FET M1 and the input of inverter I2. The output of inverter I2 is electrically coupled to the gate of FET M4.
In operation, LNA 400 is in a low power consumption mode when the LNA enable signal is at a low logic level. Inverter I1 inverts the low logic level to produce a high logic level. The high logic level causes the FET M3 to turn on, thereby grounding the input signal terminals (gates of the FETs M2 and M3) or applying a Vss potential. The ground or Vss potential at the gates of the FETs M2 and M3 causes the FET M2 to turn on and the FET M3 to turn off. Inverter 12 inverts the high logic level at the output of inverter I1 to produce a low logic level at the gate of FET M4. This causes the FET M4 to turn off, thereby separating the output signal terminal from the input signal terminal. In the low power mode, the voltage at the output signal terminal is approximately Vdd_Lna, and LNA 300 draws little current since the FETs M1 and M3 are both turned off.
When the LNA enable transitions from a low logic level to a high logic level, inverter I1 generates a low logic level, thereby turning off FET M1. Inverter I2 then inverts the low logic level at the output of inverter I1 to produce a high logic level thereby turning on FET M4. Prior to transitioning the LNA enable signal to a high logic level, the voltage at the output signal terminal was approximately Vdd_Lna, so the turn-on of the FET M4 causes charges to flow from the output signal terminal to the input signal terminal, whereby To increase the voltage.
The voltage at the input signal terminal rises until it creates a substantial equilibrium in the currents conducted by the FETs M2 and M3. In this equilibrium state, the voltage at the input signal terminals (gates of the FETs M2 and M3) is almost Vdd_Lna / 2. If this occurs, both the FETs M2 and M3 are biased in substantially the same linear regions, and the FETs M2 and M3 are complementary push-pull devices that amplify the input signal to produce an output signal. It works. Self-biasing of the FETs M2 and M3 causes the LNA 400 to amplify the input signal when necessary when LNA enable signal transitions to a high logic level occur within a relatively small defined time interval. Enable it as quickly as possible. As discussed above, once the input signal has been processed, the LNA enable signal is set back to put the LNA 400 in a low power consumption mode.
5 shows a schematic diagram of an exemplary bias setting circuit 500 in accordance with another aspect of the present invention. The bias voltage setting circuit 500 may be an example of the voltage setting circuit 104 discussed previously. The bias voltage setting circuit 500 sets up the bias voltage Vdd_Lna for the LNA. As discussed previously, if there is some residual voltage across the external capacitor after operation of the LNA, the bias voltage setting circuit 500 uses the residual voltage to set Vdd_Lna during the next operating cycle of the LNA. In this way, the bias voltage setting circuit 500 improves the power efficiency of the LNA or receiver including the LNA.
In particular, the bias voltage setting circuit 500 includes a controller 502, a variable capacitor 506, an off-chip capacitor C and a pair of FETs T1 and T2. The controller 502 includes an input for receiving a bias voltage enable signal from the timing generator 102. The controller 502 further includes inputs for receiving voltages Vdd_Chip, Vdd_Lna and Vss, where Vss may be a ground potential. The controller 502 further includes outputs for generating voltage Vdd_Boost across the variable capacitor 506 and separate control signals for the gates of the FETs T1 and T2. The voltage Vdd_Boost may be higher or lower than the voltage Vdd_Chip. The controller 502 also includes an output for generating a tuning word for the variable capacitor 506.
The source of FET T1 is adapted to receive the voltage Vdd_Chip. The drain of the FET T1 is electrically coupled to the termination of the external capacitor C and the drain of the FET T2. The bias voltage Vdd_Lna for the LNA is generated at the drain of the FET T1. The other end of capacitor C is electrically coupled to the Vss potential, which may be the ground potential as previously discussed. The source of FET T2 is electrically coupled to the Vdd_Boost rail and the termination of variable capacitor 506. The other end of the variable capacitor 506 is electrically coupled to Vss. The operation of the bias voltage setting circuit 500 is described as follows.
6 shows a timing diagram of example signals generated and / or processed by an example bias voltage setting circuit 500 in accordance with another aspect of the present invention. Prior to the first operation of the LNA, the voltage at Vdd_Lna may be represented by V 0 , which may be zero volts. The controller 502 generates a tuning word and a voltage Vdd_Boost for the variable capacitor 506 based on the current voltage Vdd_Lna, which in this example is V 0 . In essence, the controller 502 compares the voltage V 0 with the reference voltage to select an appropriate capacitance and voltage Vdd_Boost for the variable capacitor 506. In this example, since voltage V 0 can be relatively small (eg, ~ 0 volts), controller 502 tunes variable capacitor 506 to a relatively high capacitance and generates a relatively high voltage Vdd_Boost, It can thus transfer the charges to the external capacitor C where the specified Vdd_Lna voltage is required to be set.
In response to the bias voltage enable signal received from timing generator 102, controller 502 sends a pulse to the gate of FET T1. This temporarily turns on FET T1 and applies Vdd_Chip to capacitor C. In response, the voltage Vdd_Lna rises from V 0 to V 11 . The controller 502 then sends a pulse to the gate of the FET T2. This temporarily turns on FET T2 to transfer charges from variable capacitor 506 to external capacitor C. In response, the voltage Vdd_Lna rises from V 11 to V 12 , the specified bias voltage for the LNA. The LNA enable signal is then asserted to enable the LNA for a period of time to form a receive window for the input signal pulses. In this example, FET T2 is only turned on for a time sufficient to transfer the required charges from variable capacitor 506 to external capacitor C, but FET T2 may be turned on for a time that LNA is enabled. This should be understood. As described in the timing diagram, during the operation of the LNA, the voltage Vdd_Lna drops from V 12 to V 13 .
In a second operating cycle, the controller 502 generates another tuning word for the variable capacitor 506 based on the current voltage Vdd_Lna, which in this example is now V 13 . As discussed above, the controller 502 compares the voltage V 13 with the reference voltage to select an appropriate capacitance for the variable capacitor 506. In this example, the controller 502 tunes the variable capacitor 506 to a relatively low capacitance because the voltage V 13 may be higher than V 0 since it is the residual voltage across the external capacitor C remaining from the previous operation of the LNA. And generate a relatively low voltage Vdd_Boost because it does not need to shift so much voltage to the external capacitor C to obtain the specified Vdd_Lna voltage for the LNA. In this way, the bias voltage setting circuit 500 uses the residual voltage from the previous operation of the LNA to set the current bias voltage Vdd_Lna. This improves the power efficiency of the receiver because the residual charge on C is conserved from one receiving period to the next.
The second cycle operates similar to the operation of the first cycle. Specifically, in response to the timing signal received from timing generator 102, controller 502 sends a pulse to the gate of FET T1. This temporarily turns on FET T1 and applies Vdd_Chip to capacitor C. In response, the voltage Vdd_Lna rises from V 13 to V 21 . Again, in response to another timing signal received from timing generator 102, controller 502 sends a pulse to the gate of FET T2. This temporarily turns on FET T2 to move charges from variable capacitor 506 to capacitor C. In response, the voltage Vdd_Lna rises from V 21 to V 22 . The LNA enable signal is then asserted to enable the LNA for a period of time to form a receive window for the input signal pulses. As described in the timing diagram, during the operation of the LNA, the voltage Vdd_Lna drops from V 22 to V 23 . This process is repeated during the Nth operating cycle of the LNA, as shown in the timing diagram.
In the example provided, although the bias voltage setting circuit 500 has been described in connection with setting the bias voltage for the LNA, it should be understood that the circuit can be used to set the bias voltage for other devices. Again, the bias voltage setting circuit uses the residual voltage from the previous operation of the device to set a new bias voltage for the device. This is a power efficient way of setting bias voltages for any device other than just the LNA described above since the residual charge on C is conserved from one receiving period to the next.
7 shows a block diagram of an example communications device 700 including an example receiver in accordance with another aspect of the present invention. Communication device 700 may be particularly suitable for transmitting data to and receiving data from other communication devices. The communication device 700 includes an antenna 702, a Tx / Rx separation device 704, a front-end receiver 706, an RF-to-baseband receiver 708, a baseband unit 710, a baseband A large-to-RF transmitter 712, a transmitter 714, a data receiver 716 and a data generator 718. Receiver 706 may comprise or include at least some of the components of receiver 100 discussed previously, including one or more of LNAs 300 and 400 and a bias voltage setting circuit 500. Can be.
In operation, the data processor 716 may include an antenna 702 that picks up an RF signal from the telecommunications device, a Tx / Rx separation device 704 that transmits the signal to the front-end receiver 706, and amplifies the received signal. A receiver front-end 706, an RF-to-baseband receiver portion 708 that converts an RF signal into a baseband signal, and a baseband unit 710 that processes the baseband signal to determine received data. It is possible to receive data from a telecommunications device via. Thereafter, data receiver 716 may perform one or more defined operations based on the received data. For example, data processor 716 may include a microprocessor, a microcontroller, a reduced instruction set computer (RISC) processor, a display, an audio device such as a headset including a transducer such as speakers, medical equipment, shoes, A watch, a robot or mechanical device responsive to the data, a user interface such as a display, one or more light emitting diodes (LEDs), and the like.
Further, in operation, the data generator 718 includes a baseband unit 710 for processing outgoing data into a transmission baseband signal, and a baseband-to-RF transmitter section for converting the baseband signal into an RF signal. 712, a transmitter 714 that adjusts the RF signal for transmission over the wireless medium, and a Tx / Rx separation device 704 that routes the RF signal to the antenna 702 while separating input to the receiver front-end 706. And output data for transmission to another communication device via an antenna 702 that radiates an RF signal to the wireless medium. The data generator 718 may be a sensor or other type of data generator. For example, data generator 718 may include a microprocessor, microcontroller, RISC processor, pointing device such as a keyboard, mouse or trackball, audio device such as a headset including a transducer such as a microphone, medical equipment, shoes, data A robot or mechanical device, a user interface, for example, a display, one or more light emitting diodes (LEDs), and the like, may be used to generate the device.
8 shows a block diagram of an example communications device 800 that includes an example receiver in accordance with another aspect of the present invention. Communication device 800 may be particularly suitable for receiving data from other communication devices. The communication device 800 includes an antenna 802, a front-end receiver 804, an RF-to-baseband transmitter 806, a baseband unit 808, and a data receiver 810. Receiver 804 may be configured or include at least some of the components of receiver 100 discussed previously, including one or more of LNAs 300 and 400 and bias voltage setting circuit 500.
In operation, data processor 810 includes an antenna 802 that picks up an RF signal from a telecommunications device, a receiver front-end 804 that amplifies the received signal, and an RF-to-band that converts the RF signal to a baseband signal. Receive data from a telecommunications device via a baseband receiver portion 806 and a baseband unit 808 processing the baseband signal to determine received data. The data receiver 810 may then perform one or more defined operations based on the received data. For example, the data processor 810 may include a microprocessor, a microcontroller, a reduced instruction set computer (RISC) processor, an audio device such as a headset including a transducer, such as a display, speakers, medical equipment, shoes, watches, data, and the like. A robot or mechanical device, a user interface, such as a display, one or more light emitting diodes (LEDs), or the like, that responds to the response.
9A shows different channels (channels 1 and 2) defined with different pulse repetition frequencies (PRFs) as one example of pulse modulation that may be used in any of the communication systems described herein. Specifically, the pulses for channel 1 have a pulse repetition frequency (PRF) corresponding to the pulse-to-pulse delay period 902. On the other hand, the pulses for channel 2 have a pulse repetition frequency (PRF) corresponding to the pulse-to-pulse delay period 904. Thus, this technique can be used to define pseudo-orthogonal channels with a relatively low probability of pulse collisions between two channels. In particular, the probability of low pulse collisions can be achieved through the use of a low duty cycle for the pulses. For example, through proper selection of pulse repetition frequencies (PRFs), substantially all pulses for a given channel may be transmitted a different number of times than pulses for any other channel.
The pulse repetition frequency (PRF) defined for a given channel may depend on the data rate or rates supported by that channel. For example, a channel that supports very low data rates (eg, on the order of kilobytes or Kbps per second) may use a corresponding low pulse repetition frequency (PRF). On the other hand, a channel supporting relatively high data rates (eg, several megabits per second or Mbps) may use a correspondingly higher pulse repetition frequency (PRF).
9B shows different channels (channels 1 and 2) defined with different pulse positions or offsets as an example of modulation that may be used in any of the communication systems described herein. Pulses for channel 1 are generated at a point in time as represented by line 906 according to the first pulse offset (eg, not shown and for a given point in time). On the other hand, pulses for channel 2 are generated at a point in time as represented by line 908 according to the second pulse offset. Given a pulse offset difference between the pulses (as indicated by arrow 910), this technique can be used to reduce the probability of pulse collisions between two channels. Depending on any other signaling parameters defined for the channels (eg, as discussed herein) and the accuracy of timing between the devices (eg, relative clock drift), the use of different pulse offsets is orthogonal Or to provide pseudo-orthogonal channels.
9C shows different channels (channels 1 and 2) defined with different timing hopping sequences that can be used in any of the communication systems described herein. For example, pulses 912 for channel 1 may be generated at times according to one time hopping sequences, while pulses 914 for channel 2 may be generated at times according to another hopping sequences. Can be generated from Depending on the specific sequences used and the accuracy of the timing between the devices, this technique can be used to provide orthogonal or pseudo-orthogonal channels. For example, time hopping pulse positions may not be periodic to reduce the likelihood of repetitive pulse collisions from neighboring channels.
9D shows different channels defined with different time slots as an example of pulse modulation that may be used in any of the communication systems described herein. Pulses L1 for the channel are generated at certain points in time. Similarly, pulses L2 for the channel are generated at different points in time. In the same way, pulse L3 for the channel is generated at further points in time. In general, time points associated with different channels may be inconsistent or orthogonal to reduce or eliminate interference between the various channels.
It should be understood that other techniques may be used to define the channels in accordance with pulse modulation schemes. For example, a channel may be defined based on different spreading pseudo-random sequences, or some other suitable parameter or parameters. In addition, a channel can be defined based on a combination of two or more parameters.
10 illustrates a block diagram of various ultra wideband (UMB) communication devices in communication with each other over various channels in accordance with another aspect of the present invention. For example, UWB device 1 1002 is in communication with UWB 2 1004 via two simultaneous UWB channels 1 and 2. UWB device 1002 is in communication with UWB device 3 1006 over a single channel 3. In addition, UWB device 3 1006 is in communication with UWB device 4 (1008), in turn, over a single channel (4). Other configurations are also possible. Communication devices can be used for many other applications, for example, headsets, microphones, biometric sensors, heart rate monitors, pedometers, EKG devices, watches, shoes, remote controls, switches, tire pressure monitors, or other communication devices. Can be implemented as
11 shows a block diagram of an example apparatus 1100 in accordance with another aspect of the present invention. The apparatus 1100 includes a module 1102 for an input signal comprising inputs coupled together to receive an input signal, and first and second complementary devices having output signals generated and coupled together. It includes. Apparatus 1100 couples the inputs and outputs of the first and second complementary devices and causes the first and second complementary devices to have substantially the same currents when processing module 1102 is enabled. And further includes a module 1104 adapted to conduct.
Any of the above aspects of the invention may be implemented in many different devices. For example, in addition to medical applications as described above, aspects of the present invention can be applied to health and athletic applications. In addition, aspects of the present invention can be implemented in a shoe for different types of applications. There are many other applications that may include any aspect of the present invention as described herein.
Various aspects of the invention have been described above. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any structure, function, or both disclosed herein, are merely representative. Based on the teachings herein, one of ordinary skill in the art should understand that an aspect disclosed herein may be implemented independently of any other aspects, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of aspects described herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. As an example of some of the above concepts, in some aspects concurrent channels may be established based on pulse repetition frequencies. In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.
Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different techniques and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above descriptions may include voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or It can be represented by optical particles, or any combination thereof.
Those skilled in the art will appreciate that various exemplary logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be designed using electronic hardware (eg, source coding or some other technique). Digital implementation, analog implementation, or combination thereof), various forms of program or design code including instructions (for convenience, referred to herein as "software" or "software module"), or a combination of both It will be further understood that it can be implemented. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented in hardware or software depends upon the particular applications and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented within or performed by an integrated circuit (“IC”), an access terminal, or an access point. The IC may be a general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, electrical components, optical Components, mechanical components, or any combination thereof designed to perform the functions described herein, and may execute code or instructions residing within the IC, external to the IC, or both. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, eg, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors associated with a DSP core, or any other such configuration.
It is understood that any specific order or hierarchy of steps in any disclosed process is an example of a sample approach. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present invention. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The steps of a method or algorithm described in connection with the aspects disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. Software modules (eg, including executable instructions and associated data) and other data may be stored in data memory, such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, It may reside in a removable disk, CD-ROM, or any other form of computer-readable storage medium known in the art. The sample storage medium may be coupled to, for example, a computer / processor (which may be referred to herein as a “processor” for convenience) such that the processor reads information (eg, code) from the storage medium and stores the storage. Information can be recorded on the medium. The sample storage medium may be integrated into the processor. The processor and the storage medium may reside in an ASIC. The ASIC can reside in user equipment. In the alternative, the processor and the storage medium may reside as discrete components in a user equipment. In addition, in some aspects any suitable computer-program product may comprise a computer-readable medium comprising code associated with one or more of the aspects of the present invention. In some aspects, the computer program product may include a package.
Although the present invention has been described in connection with various aspects, it will be understood that the present invention is capable of further modifications. Such an application generally follows the principles of the present invention and any modifications, uses, etc. of the present invention, including deviations from the present invention as known within the related art and in custom implementation. Or intended to cover adaptation.

Claims (31)

  1. An apparatus for processing an input signal,
    A first circuit comprising first and second complementary devices having inputs coupled together and outputs coupled together; And
    A second circuit comprising at least a portion coupled between the inputs and outputs of the complementary devices,
    The second circuit is adapted to cause the complementary devices to conduct the same current when the first circuit is enabled,
    A device for processing an input signal.
  2. The method of claim 1,
    A third circuit adapted to set a voltage specified for inputs or outputs of the complementary devices when the first circuit is disabled,
    A device for processing an input signal.
  3. The method of claim 2,
    The second or third circuit is adapted to respond to a control signal for enabling or disabling the first circuit,
    A device for processing an input signal.
  4. The method of claim 3,
    The second and third circuits are configured to enable the first circuit within a specified constant time,
    A device for processing an input signal.
  5. The method of claim 1,
    The second circuit is adapted to remove electrical charges from the inputs of the complementary devices to cause the complementary devices to conduct the same current,
    A device for processing an input signal.
  6. The method of claim 1,
    The second circuit is adapted to route charges to the inputs of the complementary devices to cause the complementary devices to conduct the same current,
    A device for processing an input signal.
  7. The method of claim 1,
    The complementary devices include a p-channel field effect transistor (FET) and an n-channel field effect transistor (FET),
    A device for processing an input signal.
  8. The method of claim 1,
    Wherein the first circuit comprises a low noise amplifier (LNA),
    A device for processing an input signal.
  9. The method of claim 1,
    The second circuit includes a resistor element coupled in series with the controllable switch;
    A device for processing an input signal.
  10. The method of claim 2,
    The third circuit comprises a controllable switch located between the inputs or outputs of the complementary devices and the source of the specified voltage,
    A device for processing an input signal.
  11. A method of processing an input signal,
    Processing the input signal using a pair of complementary devices having inputs coupled together and outputs coupled together; And
    Coupling the inputs to the outputs of the devices to enable the devices to conduct the same current to enable processing of the input signal,
    How to process an input signal.
  12. The method of claim 11,
    Setting a voltage specified for inputs or outputs of the complementary devices to disable processing of the input signal,
    How to process an input signal.
  13. The method of claim 12,
    Setting a voltage specific to the inputs or outputs of the complementary devices is responsive to a control signal indicating whether to enable or disable processing of the input signal;
    How to process an input signal.
  14. The method of claim 11,
    Enabling processing of the input signal within a specified constant time,
    How to process an input signal.
  15. The method of claim 11,
    Further comprising removing charges from inputs of the complementary devices to cause the complementary devices to conduct the same current;
    How to process an input signal.
  16. The method of claim 11,
    Further comprising routing charges to the inputs of the complementary devices to cause the complementary devices to conduct the same current;
    How to process an input signal.
  17. The method of claim 11,
    The complementary devices include a p-channel field effect transistor (FET) and an n-channel field effect transistor (FET),
    How to process an input signal.
  18. As a device,
    Means for processing the input signal using a pair of complementary devices having inputs coupled together and outputs coupled together; And
    Means for coupling the inputs and outputs of the complementary devices together,
    The coupling means is adapted to cause the complementary devices to conduct the same current when the processing means is enabled,
    Device.
  19. The method of claim 18,
    Means for setting a voltage specified for the inputs or outputs of the complementary devices when the processing means is disabled,
    Device.
  20. 20. The method of claim 19,
    The specified voltage setting means is adapted to respond to a control signal for enabling or disabling the processing means,
    Device.
  21. The method of claim 18,
    The coupling means is configured to enable the processing means within a specified constant time,
    Device.
  22. The method of claim 18,
    The coupling means is adapted to remove charges from the inputs of the complementary devices to cause the complementary devices to conduct the same current,
    Device.
  23. The method of claim 18,
    The coupling means is adapted to route charges to inputs of the complementary devices to cause the complementary devices to conduct the same current,
    Device.
  24. The method of claim 18,
    The complementary devices include a p-channel field effect transistor (FET) and an n-channel field effect transistor (FET),
    Device.
  25. The method of claim 18,
    The processing means is adapted to process the input signal having at least 20% of the partial spectrum, at least 500 MHz of the spectrum, or at least 20% of the partial spectrum and at least 500 MHz of the spectrum;
    Device.
  26. The method of claim 18,
    The processing means comprises a low noise amplifier (LNA),
    Device.
  27. The method of claim 18,
    Said coupling means comprising a resistive element coupled in series with a controllable switch;
    Device.
  28. 20. The method of claim 19,
    The specified voltage setting means comprises a controllable switch located between the inputs or outputs of the complementary devices and the source of the specified voltage,
    Device.
  29. As a headset,
    A first circuit adapted to process the signal; Said first circuit comprising first and second complementary devices having inputs coupled together and outputs coupled together; ;
    A second circuit coupled between the inputs and outputs of the complementary devices; The second circuit is adapted to cause the complementary devices to conduct the same current when the first circuit is enabled? ; And
    A transducer adapted to generate sound based on the signal,
    headset.
  30. As a watch,
    A first circuit adapted to process the signal; Said first circuit comprising first and second complementary devices having inputs coupled together and outputs coupled together; ;
    A second circuit coupled between the inputs and outputs of the complementary devices; The second circuit is adapted to cause the complementary devices to conduct the same current when the first circuit is enabled? ; And
    A user interface adapted to provide an indication based on the signal,
    clock.
  31. As a sensing device,
    A first circuit adapted to process the signal; Said first circuit comprising first and second complementary devices having inputs coupled together and outputs coupled together; ;
    A second circuit coupled between the inputs and outputs of the complementary devices; The second circuit is adapted to cause the complementary devices to conduct the same current when the first circuit is enabled? ; And
    A sensor adapted to generate second data in response to or based on the signal;
    Sensing device.
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EP2274828B1 (en) 2017-08-16
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KR20100121546A (en) 2010-11-17
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US20090224832A1 (en) 2009-09-10
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CN101971487B (en) 2013-03-06
TW200939615A (en) 2009-09-16
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JP2011514118A (en) 2011-04-28
WO2009114021A1 (en) 2009-09-17
US7812667B2 (en) 2010-10-12
EP3249808A1 (en) 2017-11-29
JP5313270B2 (en) 2013-10-09

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