RU2558609C2 - Servo feedback transmitter - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to switching media for computer systems and can be used as a component part of a high-speed serial multichannel transceiver. The servo feedback transmitter comprises a clock generator connected to a phase-locked-loop frequency control, a multiplexer connected to a controller, a shift register, a pulse response controller, a pulse response controller decoder, an output buffer, a stable current source, a main digital-to-analogue converter, wherein the transmitter is provided with an additional digital-to-analogue converter and a decoder for the additional digital-to-analogue converter, connected to a receiver, to control the minimum allowable swing of the differential voltage of the output signal of the transmitter from the current receiver intersymbol interference correction depth.

EFFECT: low transmitter power consumption.

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Description

The invention relates to the field of switching environments for computing systems and can be used as part of a high-speed serial multi-channel transceiver.

A known feedback transmitter consisting of a clock generator, a multiplexer, a shift register, an impulse response controller, an output buffer, a stable current source, a main digital-to-analog converter connected to a controller, receiver, and phase-locked loop (Beukema T., Soma M., Sekandr K.A. 6.4-Gb / s CMOS serdes core with feed-forward and decision-feedback equalization. // IEEE Journal of Solid-State Circuits, vol. 40, pp. 2633-2645, Dec. 2005.)

The disadvantage of the described transmitter is a rather large power consumption, since there is no dependence of the amplitude of the differential voltage of the output signal on the current depth of correction of intersymbol interference.

The objective of the invention is to ensure the operation of the device for multichannel transceiver systems, as well as systems on a chip.

This problem is solved in that the servo feedback transmitter, consisting of a clock generator, multiplexer, shift register, impulse response regulator, impulse response regulator decoder, output buffer, stable current source, main digital-to-analog converter connected to the controller, receiver, and phase-locked loop frequency, according to the invention is equipped with an additional digital-to-analog Converter associated with the output buffer, and an additional qi decoder roanalogovogo converter associated with the receiver to monitor minimum amplitude of the transmitter output signal of a differential voltage to current receiver depth correction intersymbol interference.

The technical result from the use of the invention is to reduce the power consumption of the transmitter by ensuring the operation of the device for multi-channel transceiver systems, as well as systems on a chip.

The invention is illustrated in the drawing, which shows a structural diagram of a transmitter with tracking feedback.

The device consists of a controller (KR) 1, a transmitter (TRANSMITTER) 2, a receiver (RECEIVER) 3, a phase-locked loop (PLL) 4. The transmitter 2 consists of a clock generator (TG) 5, a multiplexer (M) 6, a shift register (SR ) 7, an impulse response controller (RICH) 8, an output buffer (WB) 9, a stable current source (IST) 10, a main digital-to-analog converter (OCAP) 11, a decoder of an additional digital-to-analog converter (DTSAP) 12, an additional digital-to-analog converter (ДЦАП) 13 pulse decoder decoder Characteristics (DRIH) 14.

The transmitter operates as follows. The clock generator (TG) 5 generates clock signals for the multiplexer (M) 6 and the shift register (SR) 7 from the reference signal coming from the phase-locked loop (PLL) 4. The unit of the multiplexer (M) 6 converts the parallel low-frequency data bus coming from the controller (KP) 1, into a serial high-frequency stream. By transmitting this data over the channel, a frequency-dependent attenuation occurs, which leads to the occurrence of intersymbol interference. The combination of the shift register (SR) 7, the impulse response regulator (IIR) 8 and the output buffer of the output buffer (WB) 9 acts as an equalizer necessary to compensate for the intersymbol interference. The equalizer is based on the principle of operation of a non-recursive filter with a finite impulse response (FIR).

From the output of the multiplexer (M) 6, the stream is fed to the input of the shift register (CP) 7, which acts as a delay line. The number of delay line elements is determined by the order of the implemented filter. The delay time of one element in the line corresponds to a unit interval of the processed data stream. The output signal of the shift register (SR) 7 is a set of sequential flows, where each subsequent one is shifted relative to the previous one unit interval. The task of the impulse response regulator (RIH) 8 is to multiply the input flows coming from the shift register (SR) 7 in the proportions corresponding to the coefficients formed at the output of the decoder of the impulse response regulator (DRI) 14. The impulse response regulator (RI) 8 block is implemented as discrete multi-channel multiplexing matrix with digital control, in the process of redistributing the contribution of each input stream to the total stream generated at the output of the output buffer (WB) 9.

The task of the output buffer (WB) 9 is not only to act as an adder of the final impulse response (FIR) of the filter, but also to provide the required electrical characteristics of the output signal entering the channel. The maximum output swing at the output buffer (WB) 9 output is determined by the sum of the currents from the main digital-to-analog converter (DAC) 11 and the additional digital-to-analog converter (DAC) 13. In the absence of the output current from the additional digital-to-analog converter (DAC) 13, the output current of the main digital-to-analog converter (DAC) 11 should provide the minimum allowable differential voltage swing of the output signal of the output buffer (WB) 9 that meets the requirements of the specification. During operation, the output current of the main digital-to-analog converter (DAC) 11 is constant and works from the reference current of the generated stable current source (IST) 10. The reference current for the additional digital-to-analog converter (DAC) 13 is defined as a portion of the output current of the main digital-to-analog converter (DAC) 11.

From the receiver unit (RECEIVER) 3 to the inputs of the decoder of the impulse response controller (DRI) 14 and the decoder of the additional digital-to-analog converter (DTSAP) 12, information is received on the depth of correction of intersymbol interference, which the transmitter must form (TRANSMITTER) 2. If the correction depth is zero, the output of the decoder of the impulse response regulator (DRI) 14 will generate a logic code in which the multiplexing matrix of the impulse response regulator (RIH) 8 passes through k corresponding to the zero order of the finite impulse response (FIR) of the filter. In other words, all filter coefficients except the zero order coefficient are equal to zero. In this case, the output control signal of the decoder of the additional digital-to-analog converter (DTsAP) 12 corresponds to the zero current output of the additional digital-to-analog converter (DTsAP) 13. As the correction depth increases, the code at the output of the decoder of the impulse response regulator (DRI) 14 will redistribute the output flows of the impulse response regulator (RIH) 8, increasing the coefficients of non-zero orders of the final impulse response (FIR) of the filter. Simultaneously with the increase in the correction depth, the current at the output of the additional digital-to-analog converter (DAC) 13 increases. The addition of the main digital-to-analog converter (DAC) 11 to the main current increases the maximum amplitude of the output differential signal at the output of the output buffer (WB) 9 in proportion to the increase in the correction depth. This means that the minimum allowable range of the differential voltage at the output of the output buffer (WB) 9 will remain constant. Therefore, on the one hand, the output buffer (WB) 9 provides the minimum allowable swing of the differential voltage of the output signal that meets the requirements of the specification, and on the other hand consumes the minimum necessary power for the current value of the correction depth of intersymbol interference.

Thus, the invention allows to reduce the power consumption of the transmitter.

Claims (1)

A servo feedback transmitter consisting of a clock associated with a shift register, phase locked loop, and a multiplexer associated with a controller and a shift register associated with an impulse response controller associated with an output buffer and an impulse response regulator decoder associated with a receiver a digital-to-analog converter connected to a stable current source and an output buffer, characterized in that the transmitter is equipped with an additional digital-to-analog the converter and the decoder of the additional digital-to-analog converter, the additional digital-to-analog converter connected to the output buffer and the main digital-to-analog converter, and the decoder of the additional digital-to-analog converter connected to the receiver and the additional digital-to-analog converter to provide control of the minimum allowable difference in the differential voltage of the transmitter output signal from the current correction depth of the intersymbol receiver interference.