RU153302U1 - ENCODING DEVICE - Google Patents

Abstract

An encoding device containing an input register, a bit analyzer, a key control unit, a key block, a ROM, a multiplexer unit, an output register, as well as a clock generator, frequency divider, counter and output register with the following connections: input register 1-n output is connected to inputs the discharge analyzer and with the key management unit, the outputs of the 1-n analyzer are connected to the information inputs of the key unit, and the outputs of the 1-n key management unit are connected to the control inputs of this unit, the outputs of which are 1-n connected to the ROM inputs, and the outputs 1-2n of the ROM are connected to the information inputs of the multiplexer unit, the outputs of which 1-n are the outputs of the device marker; outputs 3-8 of the input register are connected to the output register, the outputs of which are outputs of the information bits of the device; the output of the clock generator through the counter is connected to the control inputs of the multiplexer unit, and through the frequency divider, to the control inputs: through the output. 1 input register, through out. 2 with a key management unit, and through the out. 3 with output register.

Description

The utility model relates to electronic technology, namely to computer technology - systems for transmitting encoded information in the form of binary signals.

This device is designed to represent characters in the form of binary numbers and can be used to transfer text data from one computer to another when compressing a code sequence.

A common problem (task) of transmitting encoded information is to increase the speed of information transfer.

Known RF patent No. 2386210 "Method of data compression", in which the method of data compression is carried out using an encoder. The first memory block and encoder store pre-recorded code combinations (CC ₁ ) with the number of bits n, where n = 2, 3, 4 ..., which are a complete set of possible input code combinations (CC). In the second memory block of the encoder, pre-recorded code combinations of KK ₂ are stored, uniquely corresponding to KK ₁ , with the number of bits less or the same as in KK ₁ . The input data stream is divided into QC with the same number of bits n. QC is sequentially introduced into the encoder, identified by comparison with QC ₁ , and the corresponding output code combination of QC _{2 is} displayed. KK ₂ are a sequence of groups with the same number of bits n in each. The total number of code combinations KK ₂ -m ⁿ , where m = 2, 3, 4 ..., n = 1, 2, 3 ... The number of consecutive KK groups is defined as t ¹¹ " ¹ , t ¹¹ " ² ... Bit KK2 in the group align by adding insignificant zero before the code combination.

The disadvantage of the device according to this patent is the circuit complexity, which complicates its use.

Known RF patent №2168857, "A method and device for compressing an encoded sequence of characters from an ordered m-ary alphabet into an encoded sequence of binary characters." The method consists in preliminary forming approximating encoded sequences (ACMP), coding them, determining and comparing the length of each approximating encoded sequence (ACMP) with a predetermined maximum permissible length, erasing ACMP for which the lengths of their corresponding ACMP exceed the maximum permissible length, choosing from the remaining AKMP closest to the encoded sequence and its adoption as an encoded sequence of binary characters. A device for implementing the method consists of an identification unit, a unit for calculating statistical parameters, first and second normalization units, first, second and third registers of normalizing shift, first and second registers of right shift, subtractor, comparator, first, second and third switching units, adder, the first and second blocks of memory of the encoding parameters, the register of the code interval, the first and second registers of the left shift, the register of the lower encoding boundary, as well as from the newly entered block of pa the memory of the encoded sequence, the AKmP memory block, the switch, the selection block, the AKmP memory block, the comparison block, the maximum permissible length memory block. The technical effect achieved during their implementation is to reduce the transmission time of the encoded sequence over the communication channel while reducing the required memory size of the storage devices of the encoded sequence - PROTOTYPE.

Its drawback is even greater circuit complexity, which increases its cost and reduces reliability, in addition, the prototype does not allow the transfer-coding of block data arrays, which is very important to improve performance.

Known widely used American standard ASCP code for the exchange of information in the form of binary numbers, designed to represent the text transmission of data between computers.

This code belongs to the group of primary codes, as in it, each code combination is allowed [2]. In addition, this code is uniform, because all code combinations have the same length [1]. All code combinations of this code are 8-bit. The base of the code, i.e. the number of values that each bit [1] can take is two.

It should be noted that this code is case-free. Register - a collection of characters of the alphabet, united by any attribute [1]. An example of a register code is the MTK-2 code, in which 3 registers are organized. Thus, the characters of different registers are encoded by one code combination [1]. In ASCII code, each code combination defines its own individual character.

The technical result of the utility model is simplicity of implementation while reducing the transmission time of text information, as well as reducing traffic in data networks with the exception of the nth number of bits.

To solve this problem, it is proposed:

An encoding device containing an input register, a bit analyzer, a key control unit, a key block, a ROM, a multiplexer unit, an output register, as well as a clock generator, frequency divider, counter and output register with the following connections: input register 1-n output is connected to inputs the discharge analyzer and with the key management unit, the outputs 1-n of the analyzer are connected to the information inputs of the key unit, and the outputs 1-n ² of the key management unit are connected to the control inputs of this unit, the outputs of which 1-n are connected to the inputs of the ROM, and the outputs 1-2n of the ROM are connected to the information inputs of the multiplexer unit, the outputs of which 1-n are the outputs of the device marker; outputs 3-8 of the input register are connected to the output register, the outputs of which are outputs of the information bits of the device; the output of the clock generator through the counter is connected to the control inputs of the multiplexer unit, and through the frequency divider, to the control inputs: through the output. 1 input register, through out. 2 with a key management unit, and through the out. 3 with output register.

The drawing shows the structural electrical part of the device, which depicts; 1 - input register, 2 - digit analyzer, 3 - control unit

keys, 4 - key block, 5 - ROM, 6 - multiplexer block, 7 - counter, 8 - output register, 9 - frequency divider, 10 - clock generator, also an 8-bit device input, 1-n - device marker outputs , n + 1 - 8 - output information bits.

The device has the following connections: the input register 11-n output is connected to the inputs of the bit analyzer 2 and to the key control unit 3, the outputs 1-n ^{2 of the} analyzer 2 are connected to the information inputs of the key block 3, and the outputs 1-n ² to the control inputs of this a unit whose outputs 1-n ^{2 are} connected to the inputs of the ROM 5, and the outputs 1-2n of the ROM 5 are connected to the information inputs of the unit of the multiplexer 6, the outputs of which 1-n are the outputs of the device marker; the outputs 3-8 of the input register 1 are connected to the output register 8, the outputs of which are outputs of the information bits of the device; the output of the clock generator 10 through the counter 7 is connected to the control inputs of the unit of multiplexers 6, and through the frequency divider 9 - to the control inputs: through output 1 of the input register 1, through output 2 with the key control unit 3, and through output 3 with the output register 8.

The device operates as follows: eight-bit code combinations are input to the device in parallel code and are recorded in input register 1. The highest bits of the code combination, the number of which is determined by the number of bits to be excluded (n), are input to the bit analyzer 2 and simultaneously to the input of the key control unit 3.

The bit analyzer 2 is a decoder that generates a single signal at one of its outputs, depending on what code combination is at the input, and the number of its outputs is determined by the expression n ² . The generated signal from the output of the analyzer of 3 groups is supplied to the corresponding key of the key block 4, which is controlled by the key control block 3. Its task is to open the keys 4 only at those times when a marker should be formed. Depending on the code combination received at the input, a unit is generated at a certain output of the key management unit 3. This unit is fed to the corresponding control input of the key unit 4 and opens the corresponding key. Thus, the unit from the output of the digit analyzer 2 passes through the corresponding key to the input of the ROM 5.

The key management unit 3 is constructed in such a way that if the next code combination recorded in input register 1 has the same high order bits as the previous one, then it does not issue a unit, and the key does not open a second time. Thus, the key management unit 3 opens the keys only when changing the values of the highest n bits in the input code combination.

The formed unit at the output of the key block 4 is supplied to a read-only memory (ROM 5), which stores markers whose bit capacity is determined by the formula 2n. Depending on which input of ROM 5 is supplied with a unit, the corresponding code combination will be formed at its output, which is a marker.

From the output of the ROM 5, the marker is supplied to the block of multiplexers 6. The number of multiplexers corresponds to the number n. Multiplexers provide the conversion of each pair of bits of the marker from serial to parallel, as well as shorten the duration of each bit by half. Thus, at each output of the block of multiplexers 6, a pair of bits is formed with a total duration equal to the duration of the information discharge. The address inputs of each multiplexer are controlled by a single-bit counter 7, the output of which determines which information input of each multiplexer will be connected to the output. The decrease in the duration of the marker bits is due to the fact that the clock pulses supplied to the counter 7 from the clock generator 10 are two times shorter than the information bits. Thus, the counter 10 changes its state twice during the duration of the discharges at the inputs of the multiplexers. This means that the discharges at the output of the multiplexers will be two times shorter. Thus, the number of bits at the output of the block of multiplexers 6, and in duration, corresponds to the number of bits to be excluded from the original eight-bit code combination.

While a marker is being formed, bits 3–8 are written from the output of the input register to output register 8. After that, they are read to the output of the circuit.

Thus, at the output of the device, two types of code combinations can be formed:

1. n-bit, which consists of an n-bit marker and 8-n information bits;

2. 8-n bit, which is formed when the highest n bits of the code combination are similar to the same bits of the previous code combination.

To ensure the synchronous operation of the entire circuit, a clock generator 10 is used, which produces a clock sequence with a frequency two times the information frequency. Since the input 1 and output 8 registers, as well as the key management unit 3 work with the repetition rate of information bits, it is necessary to reduce the repetition rate of the clock signals supplied from the clock generator 10. To do this, set the frequency divider 9 into two.

The decoding scheme is not considered in this application, because its description is not of interest.

Claims (1)

An encoding device containing an input register, a bit analyzer, a key control unit, a key block, ROM, a multiplexer unit, an output register, as well as a clock generator, frequency divider, counter and output register with the following connections: input register 1-n output is connected to inputs the analyzer of discharges and with the key management unit, the outputs 1-n ^{2 of the} analyzer are connected to the information inputs of the key unit, and the outputs 1-n ² of the key management unit are connected to the control inputs of this unit, the outputs of which 1-n ^{2 are} connected to the inputs of the PP Y, and the outputs 1-2n of the ROM are connected to the information inputs of the multiplexer unit, the outputs of which 1-n are the outputs of the device marker; outputs 3-8 of the input register are connected to the output register, the outputs of which are outputs of the information bits of the device; the output of the clock generator through the counter is connected to the control inputs of the multiplexer unit, and through the frequency divider - to the control inputs: through the output. 1 input register, through out. 2 with a key management unit, and through the out. 3 with output register.

Images