RU2672625C1 - Device for compression of data - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to computer technology and is intended for use in information processing systems. Apparatus comprises: N input characters D1, D2, …, DN by k digits, input data register, the first group of N OR elements, the first group of N AND elements, multi-output priority block, NOR element, second group of (N-1) OR elements, a group of N synchronous D flip-flops, a data switch block, an output buffer, an external synchronization input C, an external CLR input of the asynchronous setting to zero, external Q outputs of the device, an internal data line DD of N characters of k digits, an internal N bit line of M character mask, an internal N bit line of the trigger outputs T, and a group of W internal lines of high character pointers U1, U2, …, UW, wherein the data switch unit comprises W switches, and the multi-output priority block comprises W stages, each i-th stage comprising a group of (N-1-i) OR elements, a group of (N-i) inhibition elements AND with one inverse input and a group of (N-i) AND elements.EFFECT: reduced time of data transfer and increased information capacity without loss of information.1 cl, 3 dwg

Description

The invention relates to the field of computer technology and is intended for use in information processing systems, and can also be used in lossless data compression and decompression units in systems for the rational use of data storage and transmission devices, data processing of physical experiments.

A known method of data compression (RU No. 2386210 C2, IPC Н03М 7/40, Н03М 7/46, announced 04.08.2006, published 04.10.2010, Bull. No. 10), in which data compression is performed using an encoder. The first block of memory of the encoder stores pre-recorded code combinations (CC ₁ ) with the number of bits n, where n = 2, 3, 4, ..., which are a complete set of possible input code combinations (CC). In the second memory block of the encoder, pre-recorded code combinations of KK ₂ are stored, uniquely corresponding to KK ₁ , with the number of bits less or the same as in KK ₁ . The input data stream is divided into QC with the same number of bits n. QC is sequentially introduced into the encoder, identified by comparison with KK ₁ , and the corresponding output code combination of KK _{2 is} displayed. KK ₂ are a sequence of groups with the same number of bits n in each. The total number of code combinations KK ₂ -m ⁿ , where m = 2, 3, 4, ..., n = 1, 2, 3, .... The number of consecutive QC groups is defined as m ^n-1 , m ^n-2 , .... Bit depth KK2 in the group is leveled by adding insignificant zero before the code combination.

There is a known method of compression of lossless data recovery (RU No. 2403677 C1, IPC Н03М 7/30, announced on February 2, 2009, published November 10, 2010, Bull. No. 31), which uses data compression that has previously been compressed. In the compressible data stream, the number of zeros is n ₀ and the number of units is n ₁ , the algorithm for assigning non-repeating digital codes to all possible permutations with repetitions of n ₀ zeros and n ₁ units is selected and the corresponding permutation is assigned to which the digital code N _c is assigned, the total number of codes n _s , the values d ₁ = n ₀ + n ₁ -n _c and d ₂ = (n ₀ + n ₁ ) / 2 are determined, and the reverse operations are performed to restore the data stream.

Adaptive block coding (RU No. 2413360 C1, IPC Н03М 7/40, announced on November 14, 2007, published February 2, 2011, Bull. No. 6) is known in the art of using memory, which uses variable length coding (VLC) with low data complexity. The code structure defines groups of codewords in the code tree, each of the groups includes codewords representing values having the same weighting factors, and codewords are ordered lexicographically with respect to values represented by codewords. In addition, the code structure defines the first and second subgroup of code words in each of the groups, the first subgroup includes code words having a first length, and the second subgroup includes a second length different from the first length. Then form the result of encoding a variable length for at least one of the storages in the storage device, transfer to the device or presentation to the user.

A coding device is known (RU No. 153302 U1, IPC Н03М 7/30, declared June 17, 2014, published July 10, 2015, Bull. No. 19), which contains an input register, a bit analyzer, a key management unit, a key block, a ROM, a multiplexer block, the output register, as well as the clock generator, frequency divider, counter and output register with the following connections: the output of the input register 1-n is connected to the inputs of the digit analyzer and to the key control unit, the outputs 1-n ^{2 of the} analyzer are connected to the information inputs of the key block, and outputs 1-n ² - with control inputs of this a unit whose outputs 1-n ^{2 are} connected to the inputs of the ROM, and the outputs 1-2n of the ROMs are connected to the information inputs of the unit of the multiplexer, the outputs of which 1-n are the outputs of the device marker; outputs 3-8 of the input register are connected to the output register, the outputs of which are outputs of the information bits of the device; the output of the clock generator through the counter is connected to the control inputs of the multiplexer unit, and through the frequency divider, to the control inputs: through output 1 of the input register, through output 2 with the key control unit, and through output 3 with the output register.

The disadvantage of these devices is the circuit complexity, which complicates their use.

The closest device of the same purpose to the claimed invention in terms of features is a data compression device adopted as a prototype (RU No. 2622878 C1, IPC Н03М 7/30, announced on 08/01/2016, published on 06/20/2017, Bull. No. 17), containing N input characters D1, D2, ..., DN of k bits connected to the input data register 1, a group of L character analyzers 2 ₁ , 2 ₂ , ..., 2 _L , each of which contains the first group of w elements OR 3, the first group of w elements And 4 and a unit for counting the number of units 5 (L is the number of groups of w characters from k digits, m N = L * w), a group of (L-1) adders 6 _1, 6 _2, ... 6, _L-1, a group of (L-1) comparing circuits 7 _1, 7 _2, ..., 7, _L-1 , a group of (L-1) D-flip-flops 8 ₁ , 8 ₂ , ..., 8 _L-1 with a CE enable input, an asynchronous CLR and synchronous R zero-setting inputs, a second group of (L-1) AND elements 9 ₁ , 9 ₂ , ..., 9 _L-1 , third element AND 10, fourth element AND 11, second element OR 12, multi-output priority block 13, data switch block 14, output buffer 15, external inputs for setting the number of characters w in the group 16, external input EN work permit 17, external input C clock 18, external input C LR zeroing 19, the external outputs of the device Q 20, as well as the internal data bus DD of N characters of k bits, the internal N bit bus of the symbol mask M, the internal L bit bus of the pointers of the symbol groups U, and the external input CLR of the setting to zero state 19 is connected to the inputs of the zero state of the input register 1 and the output buffer 15, as well as the CLR inputs of the asynchronous zero state of all triggers 8 ₁ , 8 ₂ , ..., 8 _L-1 , the external synchronization input 18 is connected to the synchronization inputs C triggers 8 ₁ , 8 ₂ , ..., 8 _L-1 , the input register 1 and the output buffer 15, the external EN input of the operation permit 17 is connected to the operation enable inputs CE of the triggers 8 ₁ , 8 ₂ , ..., 8 _L-1 and the output buffer 15, and the outputs of the input data register 1 are connected to an internal data bus DD, from which groups of w symbols from k bits are connected to the corresponding inputs of the first groups of w elements OR 3 symbol analyzers 2 ₁ , 2 ₂ , ..., 2 _L , in each of which the outputs of the first groups of w elements OR 3 connected to the second inputs of the corresponding first groups of w elements AND 4, the outputs of which x are the internal bus of the symbol mask M and are connected to the inputs of the counting unit of the number of units 5, the outputs of which are the outputs of the symbol analyzers 2 ₁ , 2 ₂ , ..., 2 _L , the output of the first symbol analyzer 2 _{1 is} connected to the first group of inputs of the first adder 6 ₁ , the outputs of the symbol analyzers, starting from the second 2 ₂ to the last 2 _{L of the} analyzer, are connected to the second groups of inputs of the corresponding adders 6 ₁ , 6 ₂ , ..., 6 _L-1 , the outputs of the adders, starting in the first 2 ₁ to the penultimate 6 _L-2 adder connected to the first group of inputs of the subsequent su Matora from the second 2 ₂ to the last 2 _L of the adder and outputs (L-1) adders 6 _1, 6 _2, ... 6, _L-1 connected to the second input groups corresponding to (L-1) comparison circuit 7 ₁ 7 ₂ , ..., 7 _L-1 , the first groups of inputs of which are interconnected and connected to external inputs 16 to specify the number of characters w in the group, the outputs of the comparison circuits, starting from the first 7 ₁ to the penultimate 7 _L-2 comparison circuits, are connected to information inputs D of the corresponding triggers, starting from the second 8 ₂ to the last 8 _{L-1 of the} trigger, and with the first inputs of the corresponding elements Comrade And the second group, starting from the second 9 ₂ to the penultimate 9 _L-2 of the And element, and the information input D of the first trigger 8 _{1 is} connected to the first input of the first element 9 ₁ from the second group of And elements and is connected to a logical unit, the inverse outputs NT ₁ , NT ₂ , ..., NT _L-1 triggers 8 ₁ , 8 ₂ , ..., 8 _{L-1 are} connected to the first inputs of the first groups of w elements AND 4 corresponding (L-1) first character analyzers 2 ₁ , 2 ₂ , ... 2 _L-1 and the second inputs of respective aND gates of the second group 9 _1, 9 _2, ..., 9 _L-1, the first inputs of the first group of elements and w 4 of the last analyzer mvolov 2 _L connected to the final circuit yield comparison 7 _L-1, which is also connected to a first input of the third AND gate 10 and to a second input of the fourth AND gate 11, whose output is connected to the enable input of operation the CE input of register 1, the third inputs of all the elements of the second groups of elements And 9 ₁ , 9 ₂ , ..., 9 _L-1 are interconnected, connected to the second input of the third element And 10 and connected to the output of the third element OR 12, the inputs of which are connected to all N bits of the internal bus of the symbol mask M, which also connected to the second groups of the inputs of the output buffer 15 and with the inputs of the multi-output priority block 13, in which w output groups are connected to the control inputs of the data switch block 14, the information inputs of which are connected to the internal data bus DD, and the outputs of the data switch block 14 are connected to the third group of outputs of the output buffer 15, the outputs of the second group of aND gates 9 _1, 9 _2, ..., _L-1 9 and the output of the third aND gate 10 are internal bus pointers symbol groups U and connected to the first group of inputs of the output buffer 15, the outputs Q of which are external and output device 20.

The disadvantages of this device are the circuit complexity associated with the implementation of L blocks counting the number of units 5 (L is the number of groups of w characters from k bits, with N = L * w), groups of (L-1) adders 6 ₁ , 6 ₂ , ..., 6 _L-1 , groups from (L-1) comparison schemes 7 ₁ , 7 ₂ , ..., 7 _L-1 , hardware costs for storing pointers to groups of U symbols and time spent on generating and transmitting compressed groups when the sum is nonzero characters in three neighboring groups are less than the double dimension of w groups, and in two neighboring groups it exceeds the dimension of w groups, for example, when in neighboring groups contains two, three, and two non-zero symbols with groups of dimension w = 4, the required transfer of the three groups of despread symbols.

The reasons that impede the achievement of the technical result indicated below include high hardware costs and communication between them, which leads to a decrease in reliability and complication of the device.

The technical result of the invention is the simplicity of implementation while reducing data transfer time, increasing information capacity without loss of information by reducing the required amount of memory for storing a sequence of binary characters.

The specified technical result in the implementation of the invention is achieved by the fact that in a device for data compression containing

N input characters D1, D2, ..., DN of k bits connected to the input data register 1, the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N , the first group of N elements AND 3 ₁ , 3 ₂ , ... , 3 _N , group of N synchronous D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N with CE enable input, asynchronous CLR and synchronous R zero-setting inputs, multi-output priority block 4, data switch block 11, output buffer 12, external input With synchronization 15, external input CLR of asynchronous zeroing 14, external outputs Q of device 16, as well as internal data bus DD of N characters in k bits and the internal N bit bus of the character mask M,

moreover, the external input CLR of the asynchronous zeroing 14 is connected to the inputs of the CLR of the asynchronous zeroing of the input register 1 and the output buffer 12, as well as the inputs of the CLR of the asynchronous zeroing of all triggers 10 ₁ , 10 ₂ , ..., 10 _N ,

external synchronization input C 15 is connected to synchronization inputs C of all triggers 10 ₁ , 10 ₂ , ..., 10 _N , input register 1 and output buffer 12,

the outputs of the input data register 1 are connected to the internal data bus DD, from which groups of k bits by symbols are connected to the corresponding inputs of the same name to the elements of the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N , the outputs of which are connected to the second inputs elements of the same name in the first group of elements AND 3 ₁ , 3 ₂ , ..., 3 _N , the outputs of which are bits of the internal bus of the mask of symbols M, which are also connected to the first group of inputs of the output buffer 12,

additionally introduced an OR-NOT 8 element, a second group of (N-1) OR elements 9 ₁ , 9 ₂ , ..., 9 _(N-1) , as well as an internal N bit output bus of the triggers T and a group of W internal indicator buses the highest characters U1, U2, ..., UW, W switches 11 ₁ , 11 ₂ , ..., 11 _W are entered into the data switch block, and W stages 4 ₁ , 4 ₂ , ..., 4 _{W are} entered into the multi-output priority block, with each i the 4th cascade 4 _i (i = 1, 2, ..., W, where W is the number of output symbols) contains a group of (N-1-i) elements OR 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} , a group of (Ni) prohibition elements AND with one inverse input 6 _i1 , 6 _i2 , 6 _{i (N-1)} and g a group of (Ni) elements And 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} , as well as each i-th cascade 4 _i contains a group of (N + 1-i) request inputs in the i-th cascade A _i1 , And _i2 , ..., A _{i (N + 1-i)} , the bus Ui from the (N + 1-i) bits of the outputs of the pointers of the highest characters of the i-th rank (1st rank has the highest priority, and the highest bit has the highest priority) and a group of (Ni) query outputs S _i1 , S _i2 , ..., S _{i (Ni)} to the next (i + 1) th cascade,

moreover, the digits of the internal bus of the symbol mask M are connected to the corresponding inputs of the request A ₁₁ , A ₁₂ , ..., A _{1N of the} first stage 4 ₁ , and in the first (W-1) stages 4 ₁ , 4 ₂ , ..., 4 _(W-1) except for the last Wth cascade of 4 _W , (Ni) query outputs to the next (i + 1) th cascade S _i1 , S _i2 , ..., S _{i (Ni) are} connected to the corresponding (Ni) request inputs of the next (i + 1) th cascade A _{(i + 1) 1,} A _{(i + 1) 2} , ..., A _{(i + 1) (Ni)} ,

in the multi-output priority block 4 in each i-th cascade 4 _{i the} first (Ni) inputs A _i1 , A _i2 , ..., A _{i (Ni)} from the group of request inputs, except for the last request input A _{i (N-i + 1)} , connected to the first direct inputs of the corresponding elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of prohibition elements AND with one inverse input, the outputs of all elements of the group of (Ni-1) elements OR 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1} ) are connected to the second inverse inputs of the corresponding first (Ni-1) elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni-1) of the} group of inhibition elements AND with one inverse input, except for the last element 6 _{i (Ni)} which о the second inverse input is connected to the last (N-i + 1) input A _{i (N-i + 1)} of the request group of the i-th cascade and the second input of the last element 5 _{i (Ni-1)} from the group of OR elements, in addition to each i-th cascade 4 _{i the} first inputs (Ni-1) of the elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} from the group of elements OR are connected to the corresponding (Ni-1) inputs A _i2 , A _i2 , ... , A _{i (Ni) of the} request to the i-th cascade, starting from the second input of the request, except for the last input of the request A _{i (N-i + 1)} , and the second inputs of the first (Ni-2) elements 5 _i1 , 5 _i2 , ... , 5 _{i (Ni-2)} from the group of elements OR are connected to the outputs of the corresponding subsequent elements 5 _i2 , 5 _i3 , ..., 5 _{i (Ni-2)} from the group of OR elements, and in the first (W-1) cascades, except for the last Wth cascade, the second inputs (Ni) of the elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are connected to the corresponding first (Ni) inputs of the request in the i-th cascade A _i1 , A _i2 , ..., A _{i (Ni)} , except for the last input of the request A _{i (N-i + 1)} , the first inputs of the first (Ni-1) elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are connected to the outputs of the corresponding (Ni-1) elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1 )} from the group of elements OR, the first input of the last element 7 _{i (Ni)} from the group of elements AND is connected to the last input of the request A _{i ( N-i + 1)} , and the outputs (Ni) of the elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are the group of (Ni) outputs of the request S _i1 , S _i2 , ..., S _{i (Ni )} to the next (i + 1) th stage, in addition, in each i-th stage 4 _{i the} outputs (Ni) of elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of inhibit elements AND with one inverse input are the first (Ni) bits of the corresponding internal bus of the i-th rank U _i1 , U _i2 , ..., U _{i (Ni)} from W of the internal bus pointers of the highest symbols, and the last (N-i + 1) bit U _{i (N + 1 -i) is} connected to the last (N-i + 1) input of the request in the i-th cascade A _{i (N-i + 1)} ,

query outputs S _w1 , S _w2 , ..., S _{w (Ni)} to the next (i + 1) th stage of the last Wth stage 4w are connected to the inputs of the OR-NOT 8 element, the output of which is connected to the synchronous inputs of the zero setting R of all triggers 10 ₁ , 10 ₂ , ..., 10 _N and the operation enable input CE of the input data register 1,

moreover, the corresponding discharges of the same name from a group of W internal bus pointers of higher symbols U1, U2, ..., UW are connected to the corresponding inputs of the same elements from the second group of (N-1) elements OR 9 ₁ , 9 ₂ , ..., 9 _(N-1) the outputs of which are connected to the CE enable inputs of the corresponding triggers 10 ₁ , 10 ₂ , ..., 10 _(N-1) , and the CE enable input of the last N-th trigger 10 _{N is} connected to the last high-order bit U _{1N of the} first internal bus U1 high pointers

the inverse outputs of all triggers 10 ₁ , 10 ₂ , ..., 10 _{N are} connected to the information inputs D of the corresponding triggers 10 ₁ , 10 ₂ , ..., 10 _N , and are also bits of the internal N bit of the output bus of the triggers T, which is bitwise connected to the first the inputs of the corresponding elements of the same name And the first group of N elements And 3 ₁ , 3 ₂ , ..., 3 _N ,

information inputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the internal data bus DD, and the control inputs of each i-th switch 11 _{i are} connected to the corresponding i-th internal bus Ui of the most significant symbol pointers, the outputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the corresponding W groups of inputs from k bits, starting from the second group of inputs, the output buffer 12, the outputs Q of which are the external outputs of the device 16.

In FIG. 1 is a diagram of the proposed device for data compression with N = 6 input symbols of k bits and the number of output symbols W = 3 of k bits. In FIG. 2 shows the formats of the input data and the internal bus of the mask M. FIG. 3 shows the output format.

The following notation is accepted in the device:

A _i1 , A _i2 , ..., A _{i (N + 1-i)} - a group of (N + 1-i) request inputs in the i-th cascade (i = 1, 2, ..., W) of the multi-output priority block,

CE - work permit input,

CLR - input installation to zero state,

D - trigger information input,

D1, D2, ..., D6 (DN) - N input characters of k bits,

DD - internal data bus of N characters in k bits,

FZ - flag of zero characters (flag of zero),

k is the character length,

M - internal N bit bus character mask

Q - output bus bit capacity N + W * k,

QD - output bits of the data W characters for k bits,

QM - output N bits of a mask of characters,

R - input synchronous installation of the trigger in a zero state,

S _i1 , S _i2 , ..., S _{i (Ni)} - a group of (Ni) outputs of the request in the next (i + 1) -th cascade,

T is the internal N discharge bus of the outputs of the triggers,

U1, U2, ..., UW - a group of W internal bus pointers of the most significant characters in (N-i + 1) bits,

W is the number of output symbols in k bits,

1 - input data register,

2 ₁ , 2 ₂ , ..., 2 _N - the first group of N elements OR,

3 ₁ , 3 ₂ , ..., 3 _B - the first group of N elements And,

4 ₁ , 4 ₂ , ..., 4 _W - W stages of the multi-output priority block,

5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} - a group of (Ni-1) elements OR of each i-th cascade of a multi-output priority block,

6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} - a group of (Ni) prohibition elements AND with one inverse input of each i-th cascade of a multi-output priority block,

7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} - a group of (Ni) elements And of each i-th cascade of a multi-output priority block,

8 - element OR NOT,

9 _i1 , 9 _i2 , ..., 5 _(N-1) - the second group of (N-1) elements OR,

10 ₁ , 10 ₂ , ..., 10 _N - a group of N synchronous D-flip-flops with CE operation enable input, asynchronous and synchronous zero-setting inputs,

11 ₁ , 11 ₂ , ..., 11 _W - W switches of the data switch block,

12 - output buffer

13 - external data inputs D1, D2, ..., D6 (DN),

14 - external input CLR asynchronous installation in a zero state,

15 - external input With synchronization,

16 - external outputs Q.

The device for data compression contains N input characters D1, D2, ..., DN of k bits connected to the input data register 1, the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N , the first group of N elements AND 3 ₁ , 3 ₂ , ..., 3 _N , multi-output priority block 4, element OR NOT 8, the second group of (N-1) elements OR 9 ₁ , 9 ₂ , ..., 9 _(N-1) , a group of N synchronous D -triggerov 10 _1, 10 _2, ... 10 _N, the data block of switches 11, output buffer 12 and also introduced an external input sync 15 C, the external asynchronous set input CLR in the null state 14, external device 16 outputs Q, VNU The front data bus DD of N characters of k bits, the internal N bit bus of the mask of the symbols M, the internal N bit bus of the outputs of the triggers T, and the group of W internal bus pointers of the highest characters U1, U2, ..., UW, and W is entered into the data switch block switches 11 ₁ , 11 ₂ , ..., 11 _W , and W stages 4 ₁ , 4 ₂ , 4 _{W are} entered in the multi-output priority block, and each i-th stage 4 _i (i = 1, 2, ..., W, where W number of output symbols), contains a group of (N-1-i) elements OR 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} , a group of (Ni) elements of the inhibit AND with one inverse input 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} group and y of (Ni) and elements 7 _i1, 7 _i2, ..., 7 _{i (Ni).}

The input data register 1 contains N * k information bits and is designed to store the current array of N input characters D1, D2, DN of k bits, and also contains a CE write enable input, a synchronization input C, and an installation input to the zero state CLR. The outputs of the input data register 1 are the internal data bus DD.

In a group of N synchronous D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N, each trigger also contains a synchronization input C, a CE enable input, an asynchronous CLR, and synchronous R zero-state inputs.

The output buffer 12 contains (W + 1) a group of information inputs, a synchronization input C, and a zero input of the CLR.

The external input CLR of the zero state 14 is connected to the inputs of the zero state of the input register 1 and the output buffer 12, as well as the CLR inputs of the asynchronous zero state of all triggers 10 ₁ , 10 ₂ , ..., 10.

External input C synchronization 15 is connected to the synchronization inputs C of all triggers 10 ₁ , 10 ₂ , ..., 10, input register 1 and output buffer 12.

The bits of the internal data bus DD by groups of k bits by symbols are connected to the corresponding inputs of the same name to the elements of the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N , the outputs of which are connected to the second inputs of the same elements of the first group of elements And 3 ₁ , 3 ₂ , ..., 3 _N , the outputs of which are the bits of the internal bus of the symbol mask M, which are also connected to the first group of inputs of the output buffer 12.

Each i-th stage 4 _{i of the} multi-output priority block contains a group of (N + 1-i) request inputs in the i-th stage A _i1 , А _i2 , ..., A _{i (N + 1-i)} , the bus Ui from (N + 1-i) bits of the outputs of the pointers of the highest characters of the i-th rank (1st rank has the highest priority, and the highest bit has the highest priority) and a group of (Ni) query outputs S _i1 , S _i2 , ..., S _{i (Ni )} to the next (i + 1) th cascade.

The digits of the internal bus of the symbol mask M are connected to the corresponding inputs of the request A ₁₁ , A ₁₂ , ..., A _{1N of the} first stage 4 ₁ , and in the first (W-1) stages 4 ₁ , 4 ₂ , ..., 4 _(W-1) , in addition to the last Wth stage, 4 _W , (Ni) request outputs to the next (i + 1) th stage S _i1 , S _i2 , ..., S _{i (N-1) are} connected to the corresponding (Ni) request inputs of the following (i +1) cascade A _{(i + 1) 1} , A _{(i + 1) 2} , ..., A _{(i + 1) (Ni)} .

In the multi-output block of priority 4 in each i-th cascade 4 _{i the} first (Ni) inputs A _i1 , A _i2 , ..., A _{i (Ni)} from the group of request inputs, except for the last request input A _{i (N-i + 1)} , connected to the first direct inputs of the corresponding elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of prohibition elements AND with one inverse input. The outputs of all elements of the group of (Ni-1) elements OR 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1) are} connected to the second inverse inputs of the corresponding first (Ni-1) elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni-1)} groups of prohibition elements AND with one inverse input, except for the last element 6 _{i (Ni)} , in which the second inverse input is connected to the last (N-i + 1) input A _{i (N-i + 1) of the} group request the i-th cascade and the second input of the last element 5 _{i (Ni-1)} from the group of OR elements. In addition, in each i-th cascade 4 _{i, the} first inputs (Ni-1) of the elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} from the group of OR elements are connected to the corresponding (Ni-1) inputs A _i1 , A _i2 , ..., A _{i (Ni) of the} request to the i-th cascade, starting from the second input of the request, except for the last input of the request A _{i (N-i + 1)} , and the second inputs of the first (Ni-2) elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-2)} from the group of OR elements are connected to the outputs of the corresponding subsequent elements 5 _i2 , 5 _i3 , ..., 5 _{i (Ni-2)} from the group of OR elements. Moreover, in the first (W-1) cascades, in addition to the last Wth cascade, the second inputs (Ni) of the elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are connected to the corresponding first (Ni) request inputs in i-th cascade A _i1 , A _i2 , ..., A _{i (Ni)} , except for the last input of the request A _{i (N-i + 1)} , the first inputs of the first (Ni-1) elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} , from the group of elements AND are connected to the outputs of the corresponding (Ni-1) elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} from the group of OR elements, the first input of the last element 7 _{i (Ni)} from the group elements And is connected to the last input of the request A _{i (N-i + 1)} . The outputs (Ni) of elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are the group of (Ni) outputs of the request S _i1 , S _i2 , ..., S _{i (Ni)} to the next (i + 1) cascade. In addition, in each i-th cascade 4i, the outputs (Ni) of the elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of prohibition elements And with one inverse input are the first (Ni) bits of the corresponding internal bus of the i-th rank U _i1 , U _i2 , ..., U _{i (Ni)} from W internal buses of the upper character pointers, and the last (N-i + 1) bit U _{i (N + 1-i) is} connected to the last (N-i + 1) request input to the i-th cascade A _{i (N-i + 1)} .

The request outputs S _w1 , S _w2 , ..., S _{w (Ni)} to the next (i + 1) th stage of the last Wth stage 4 _{W are} connected to the inputs of the OR-NOT 8 element, the output of which is connected to the synchronous inputs of the zero setting the state R of all triggers 10 ₁ , 10 ₂ , ..., 10 _N and the operation enable input CE of the input data register 1.

Moreover, the corresponding discharges of the same name from a group of W internal bus pointers of higher symbols U1, U2, ..., UW are connected to the corresponding inputs of the same elements from the second group of (N-1) elements OR 9 ₁ , 9 ₂ , ..., 9 _{i (N-1 )} , the outputs of which are connected to the CE enable inputs of the corresponding triggers 10 ₁ , 10 ₂ , ..., 10 _(N-1) , and the CE enable input of the last N-th trigger 10 _{N is} connected to the last high-order bit U _{1N of the} first internal bus U1 pointers to high characters.

The inverse outputs of all triggers 10 ₁ , 10 ₂ , ..., 10 _{N are} connected to the information inputs D of the corresponding triggers 10 ₁ , 10 ₂ , ..., 10 _N , and they are also bits of the internal N bit of the output bus of the triggers T, which is bitwise connected to the first the inputs of the corresponding elements of the same name And the first group of N elements And 3 ₁ , 3 ₂ , ..., 3 _N.

The information inputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the internal data bus DD, and the control inputs of each i-th switch 11 _{i are} connected to the corresponding i-th internal bus Ui of the highest symbol pointers. The outputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the corresponding W groups of inputs from k bits, starting from the second group of inputs, the output buffer 12, the outputs of Q which are the external outputs of the device 16.

The principle of operation of the device is as follows.

The input data array D1, D2, ..., DN contains N characters of k bits (Fig. 2). Non-zero characters are determined (in the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N ) and a symbol mask M of N digits is formed. Each digit of the symbol mask M takes a single value if the corresponding symbol is non-zero, or zero if the corresponding symbol is zero, and also depending on the state of the corresponding D-flip-flop from the group 10 ₁ , 10 ₂ , ..., 10 _N (in the first a group of N elements AND 3 ₁ , 3 ₂ , ..., 3 _N ).

Further, according to the values of the digits of the symbol mask M in W stages 4 ₁ , 4 ₂ , ..., 4 _{W of the} multi-output priority block, W groups of the corresponding priority rank are formed (the group with the lower number has the highest priority, and the senior bit in the group has the highest priority), which are received to the bits of a group of W internal bus pointers of high characters U1, U2, ..., UW by (N-i + 1) bits. On each bus Ui of the high-order pointers, a value is set in unit coding in the code “1 of N”. In accordance with the priority W of the switches of the block of data switches 11 ₁ , 11 ₂ , ..., 11 _W transmit no more than W of the corresponding senior nonzero characters of the input data D1, D2, ..., DN to the corresponding input groups of the output buffer 12 (nonzero characters arrive in the reverse order - the senior non-zero symbol enters the lower group of inputs), the first group of inputs of which also receive the values of the mask of symbols M (Fig. 3). Writing to the output buffer 12 is performed by a clock signal C.

At the same time, in accordance with the unit values of the digits of the internal buses U1, U2, ..., UW of the upper character pointers, unit values are formed at the outputs of the second group of (N-1) elements OR 9 ₁ , 9 ₂ , ..., 9 _(N-1) corresponding to the selected non-zero characters that go to the CE enable inputs of synchronous D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N , which, according to the clock signal C, switch to the single state, with the unit value CE = 1, or save the state at the zero value CE = 0. At the same time, at the outputs of the triggers 10 ₁ , 10 ₂ , ..., 10 _N, at the next step, the selected and transmitted symbols are blocked - the corresponding digits in the symbol mask M are reset (in the first group of N elements And 3 ₁ , 3 ₂ , ..., 3 _N ) and the following W non-zero symbols are sampled for transmission to the output buffer 12.

If at the outputs S _W1 , S _W2 , ..., S _{W (Ni) of the} request zero values are set to the next stage of the Wth stage of UW, which corresponds to the absence of non-selected non-zero characters, then a single value will be generated at the output of the OR-NOT 8 element the zero flag (flag of zero characters) FZ = 1, according to which clock C synchronously sets all triggers 10 ₁ , 10 ₂ , ..., 10 _N to the zero state and allows the next array of input data D1, D2, ..., DN to be received input register 1.

For all zero characters of the input data D1, D2, ..., DN, the device also generates zero values on all bits of the pointers of the highest characters U1, U2, ..., UW, the zero flag FZ = 1 is formed at the output of the OR-NOT 8 element, and reception is also allowed the next array of input data D1, D2, ..., DN to input register 1.

The proposed device operates as follows.

When a single CLR signal is applied to the input of the initial installation of the device 14 to the zero state, the input register 1, a group of D-triggers 10 ₁ , 10 ₂ , ..., 10 _N and the output buffer 12 are set. At the same time, the inverted outputs of the triggers 10 ₁ , 10 ₂ , ..., 10 _N , single values will be set, zero values will be set at the outputs of register 1, zero values will be generated on all bits of the internal bus of the symbol mask M and on all bits of the pointers of the highest symbols U1, U2, ..., UW, and the flag will be zero takes a single value FZ = 1.

By a clock signal C at the external input 15, the first input data D1, D2, ..., DN is recorded in register 1, the outputs of which form the internal data bus DD, to which the corresponding inputs of the first group of elements OR 2 ₁ , 2 ₂ , ... are connected by symbols , 2 _N. Next, the outputs of the first group of elements OR 2 ₁ , 2 ₂ , ..., 2 _N will be set to single values for non-zero characters, and since the inverse outputs of triggers 10 ₁ , 10 ₂ , ..., 10 _{N are} also set to single values, then on the internal bus masks M, unit values will be formed corresponding to all nonzero characters of the input array (at the outputs of the first group of N elements AND 3 ₁ , 3 ₂ , ..., 3 _N ).

The signals from the outputs of the internal bus of the mask M are the request inputs for the multi-output priority block 4, which makes it possible to determine among the N input of the request not only the signal with the highest priority, but also to determine the signals with the second, third, and W-th priorities in priority.

In accordance with the values of the N digits of the symbol mask M in W stages 4 ₁ , 4 ₂ , ..., 4 _{W of the} multi-output priority block, W groups of the corresponding priority rank are formed on W internal buses of the upper symbol pointers U1, U2, ..., UW according to (N-i +1) bits in each i-th bus Ui. In this case, in each bus Ui, a unit coding value will be set in the form of a unitary code “1 of N” in accordance with the priority of non-zero characters, starting with the most significant characters. The outputs of the group with the lower number have the highest priority, and the highest bit in the group has the highest priority.

The signals from the internal bus of the mask of symbols M are supplied to the inputs of the request A ₁₁ , A ₁₂ , ..., A ₁₆ (A _1N ) of the first stage 4 ₁ . In the first stage 4 ₁ at the outputs of the group of elements OR 5 ₁₁ , 5 ₁₂ , ..., 5 ₁₄ (5 _{1 (N-2)} ), combined in a chain, the input request code is converted to the code "00 ... 011..1", where the left (highest) unit corresponds to the highest priority (the oldest non-zero character). Then, at the output of only one inhibit element AND with one inverse input 6 ₁₁ , 6 ₁₂ , ..., 6 ₁₅ (6 _{1 (N-1)} ), the inputs of which are given the values “01”, a single value is generated, indicating a request with a higher priority (leading non-zero character), and the remaining outputs will be set to zero. If a request with the highest priority A ₁₆ (A _1N ) is set, then a single value is set at the output of the highest pointer U ₁₆ (U _1N ). Thus, the outputs U ₁₁ , U ₁₂ , ..., U ₁₆ will be set to a single coding value in the form of a unitary code “1 of N” corresponding to the query with the highest priority (the first highest non-zero character).

Further, since the first inputs of the elements AND 7 ₁₁ , 7 ₁₂ , ..., 7 ₁₅ from the outputs of the elements OR 5 ₁₁ , 5 ₁₂ , ..., 5 ₁₄ and the senior request A ₁₆ receive the code "00 ... 011..1", and the second inputs are input signals of the request A ₁₁ , A ₁₂ , ..., A ₁₅ , except for the senior request A ₁₆ , then the outputs S ₁₁ , S ₁₂ , ..., S _{15 of the} request in the next second stage 4 ₂ will be set to request with the "excluded" request with top priority. Further, the request signals S ₁₁ , S ₁₂ , ..., S ₁₅ are received at the inputs of the request A ₂₁ , A ₂₂ , ..., A _{25 of the} second stage 4 ₂ , in which, similarly, at the outputs U ₂₁ , U ₂₂ , ..., U ₂₅ in unit coding in the form of a unitary code “1 of N” corresponding to a query with a second priority (second highest non-zero character). Then the result is formed in the form of a unitary code “1 of N” in the third, fourth, Wth cascades corresponding to the following non-zero characters in order of precedence.

Further, in accordance with the priorities on the W internal buses U1, U2, ..., UW of the high symbol pointers W of the switches of the data switch block 11 ₁ , 11 ₂ , ..., 11 _W , up to W nonzero symbols of k bits are selected and transmitted to the inputs of the output buffer 12 .

At the same time, at the outputs of the second group of (N-1) elements OR 9 ₁ , 9 ₂ , ..., 9 _(N-1) , unit values are formed corresponding to the selected non-zero characters, which are fed to the CE enable inputs of synchronous D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N.

According to the next clock signal C, the selected W non-zero characters are recorded in the output buffer 12 and output to the external outputs Q of the device, as well as the change in the state of the D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N by a unit value with the corresponding unit signal of operation permit CE = 1.

Further, at the zero values at the outputs of the triggers 10 ₁ , 10 ₂ , ..., 10 _N , the selected and transmitted symbols are blocked - the corresponding digits in the symbol mask M are reset to zero (in the first group of N elements And 3 ₁ , 3 ₂ , ..., 3 _N ) and similarly, the following W non-zero symbols are sampled for transmission to the output buffer 12 and output to the external outputs Q of the device.

Then, similarly, for each clock signal C, the selected next W non-zero characters are recorded in the output buffer 12, as well as the state of the D-triggers 10 ₁ , 10 ₂ , ..., 10 _{N is} changed to a unit value with the corresponding unit work enable signal CE = 1.

At the same time, depending on the presence of non-selected non-zero characters or their absence, a zero flag is generated respectively FZ = 0 or FZ = 1 (at the output of the OR-NOT 8 element). In the absence of non-selected non-zero characters and the generated single value of the zero flag FZ = 1, all triggers 10 ₁ , 10 ₂ , ..., 10 _N are synchronously set to zero and the next "new" input data array D1 is recorded by the next clock signal C, D2, ..., DN in input register 1.

Next, groups of W nonzero characters of k bits are formed in accordance with the above algorithm for the “new” data array.

The formation of groups of W non-zero k bit characters and the corresponding values of N bit masks M, write to the output buffer 12 and output to the external outputs Q of the device is carried out for the number of ticks multiple of the number W of non-zero characters in the input data array.

Thus, in the transmission channel to the external outputs of the device 16 are:

- N bits of the QM character mask,

- data bits of selected priority W non-zero symbols in k bits of QD.

The output buffer 12 may be implemented as a register or as a FIFO buffer. The block of data switches 14 can be implemented on a matrix of multiplexers.

The device for data compression can be effectively used in systems for recording, collecting and processing data without loss of information in real time in physical experiments.

As a result, the proposed device allows to save the amount of memory, increase the efficiency of resource use while reducing data transfer time, by eliminating zero characters from the input data.

Thus, the above information allows us to conclude that the proposed device provides compression of input data without loss, has a regularity of nodes and connections, while simplifying the design and, therefore, the device meets the claimed technical result - ease of implementation while reducing data transfer time, increasing information lossless storage capacity by reducing the required memory capacity for storing a sequence of binary characters.

Claims (1)

A device for data compression containing N input characters D1, D2, ..., DN of k bits connected to the input data register 1, the first group of N elements OR 2 ₁ , 2 ₂ , ..., 2 _N , the first group of N elements AND 3 ₁ , 3 ₂ , ..., 3 _N , a group of N synchronous D-flip-flops 10 ₁ , 10 ₂ , ..., 10 _N with CE operation enable input, asynchronous CLR and synchronous R zero-setting inputs, priority multi-output block 4, block of data switches 11, output buffer 12, external input With synchronization 15, external input CLR of asynchronous zero setting 14, external output Q of device 16, as well as an internal data bus DD of N characters of k bits and an internal N-bit character mask bus M, and the external input CLR of the asynchronous zero setting 14 is connected to the inputs CLR of the asynchronous zero setting of the input register 1 and the output buffer 12, as well as the CLR inputs of asynchronous zeroing of all triggers 10 ₁ , 10 ₂ , ..., 10 _N , external input С synchronization 15 is connected to synchronization inputs С of all triggers 10 ₁ , 10 ₂ , ... 10 _N , input register 1 and output buffer 12, outputs the input register Data 1 are connected to an internal bus DD data, of which the groups of k bits of the symbols are connected to respective inputs of like symbols of the elements of the first group of N elements, OR 2 _1, 2 _2, ..., 2 _N, whose outputs are connected to second inputs of like elements of the first groups of elements AND 3 ₁ , 3 ₂ , ..., 3 _N , the outputs of which are bits of the internal bus of the mask of symbols M, which are also connected to the first group of inputs of the output buffer 12, characterized in that the element OR-NOT 8 is additionally inserted into it, the second group of (N-1) eleme comrade OR 9 _1, 9 _2, ..., 9 _(N-1), and the introduced internal N-bit bus output triggers T and the group of W internal buses pointers older U1 symbols, U2, ..., UW, a data block switch administered W switches 11 ₁ , 11 ₂ , ..., 11 _W , and W stages 4 ₁ , 4 ₂ , ..., 4 _{W are} entered in the multi-output priority block, and each i-th stage 4 _i (i = 1, 2, W, where W number of output symbols) contains a group of (N-1-i) elements OR 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} , a group of (Ni) elements of the inhibit AND with one inverse input 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} and a group of (Ni) elements And 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} , as well as each i-th cascade 4 _i contains a group of (N + 1-i) request inputs to the i-th cascade A _i1 , A _i2 , ..., A _{i (N + 1-i)} , a bus Ui from (N + 1-i) bits of the outputs of the pointers of the most significant symbols i-th rank (1st rank has the highest priority, and the highest rank has the highest priority) and a group of (Ni) query outputs S _i1 , S _i2 , ..., S _{i (Ni)} to the next (i + l) th cascade, and the bits of the internal bus of the symbol mask M are connected to the corresponding request inputs A ₁₁ , A ₁₂ , ... A _{1N of the} first cascade 4 ₁ , and in the first (W-1) cascades 4 ₁ , 4 ₂ , ..., 4 _{(W-1 )} , in addition to the last Wth stage of 4 _W , (Ni) outputs of the request to the next (i + 1) th stage S _i1 , S _i2 , S _{i (Ni) are} connected to corresponding (Ni) inputs of the request of the next (i + 1) -th cascade A _{(i + 1) 1} , A _{(i + 1) 2} , ..., A _{(i + 1) (Ni)} , in the multi-output priority block 4 in each i-th cascade of 4 _i first (Ni) inputs A _i1 , A _i2 , ..., A _{i (Ni)} from the group of request inputs, in addition to the last request input A _{i (N-i + 1)} , are connected to the first direct inputs of the corresponding elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of prohibition elements AND with one inverse input, the outputs of all elements of the group of (Ni-1) elements OR 5 _i1 , 5 _i2 , ... 5 _{i (Ni-1) are} connected with the second inverted inputs of the corresponding first (Ni-1) of the elements 6, _i1, 6 _i2, ..., 6 _{i (Ni-1)} a group of e-mail, And prohibition cops with one inverted input, except the last element 6 _{i (Ni),} whose second inverting input is connected with the latter (Ni + 1) input A _{i (Ni + 1)} request group i-th stage and the second by the input of the last element 5 _{i (Ni-1)} from the group of elements OR, in addition, in each i-th cascade 4 _{i the} first inputs (Ni-1) of elements 5 _i1 , 5 _i2 , ..., 5 _{i (N + 1)} from the group OR elements are connected to the corresponding (Ni-1) inputs A _i2 , A _i2 , ..., A _{i (Ni) of the} request in the i-th cascade, starting from the second input of the request, except for the last input of the request A _{i (N-i + 1)} and the second inputs of the first (Ni-2) elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-2)} from g groups of OR elements are connected to the outputs of the corresponding subsequent elements 5 _i2 , 5 _i3 , ..., 5 _{i (Ni-2)} from the group of OR elements, and in the first (W-1) stages, except for the last W-th stage, the second inputs (Ni ) elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are connected to the corresponding first (Ni) inputs of the request in the i-th cascade A _i1 , A _i2 , ..., A _{i (Ni)} , except for the last input request A _{i (N-i + 1)} , the first inputs of the first (Ni-1) elements 7 _i1 , 7 _i2 ..., 7 _{i (Ni)} from the group of elements And are connected to the outputs of the corresponding (Ni-1) elements 5 _i1 , 5 _i2 , ..., 5 _{i (Ni-1)} from the group of elements OR, first input last one element 7 _{i (Ni)} from the group of elements And is connected to the last input of the request A _{i (N-i + 1)} , and the outputs (Ni) of elements 7 _i1 , 7 _i2 , ..., 7 _{i (Ni)} from the group of elements And are a group of (Ni) outputs of the request S _i1 , S _i2 , ..., S _{i (Ni)} to the next (i + 1) th stage, in addition, in each i-th stage 4 _i outputs (Ni) of the elements 6 _i1 , 6 _i2 , ..., 6 _{i (Ni)} from the group of prohibition elements And with one inverse input are the first (Ni) bits of the corresponding internal bus of the i-th rank U _i1 , U _i2 , ..., U _{i (Ni)} from W internal indicator buses high characters, and the last (N-i + 1) bit U _{i (N + 1-i) is} connected to the last (N-i + 1) input request to the i-th cascade A _{i (N-i + 1)} , the request outputs S _w1 , S _w2 , ..., S _{w (Ni)} to the next (i + 1) -th cascade of the last W-th cascade 4 _{W are} connected to the inputs of the OR-NOT element 8, the output of which is connected to the synchronous inputs of the zero state R of all triggers 10 ₁ , 10 ₂ , ..., 10 _N and the operation enable input CE of the input data register 1, the corresponding bits of the same group of W internal index buses older symbols U1, U2, ..., UW are connected to respective inputs of similar elements of the second group of the (N-1) OR element 9 _1, 9 _2, ..., 9 _(N-1) outputs of which oedineny with the enable input CE of similar flip-flops 10 _1, 10 _2, ... 10 _(N-1) and the enable input CE of the last N-th flip-flop 10 _N is connected with the last significant bit U _1N first internal bus U1 pointers older symbols, the inverse outputs of all triggers 10 ₁ , 10 ₂ , ..., 10 _{N are} connected to the information inputs D of the corresponding triggers 10 ₁ , 10 ₂ , ..., 10 _N , and are also bits of the internal N-bit bus of the outputs of the triggers T, which is bitwise connected to the first inputs of the corresponding elements of the same name comrade And the first group of N elements And 3 ₁ , 3 ₂ , ..., 3 _N , the information inputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the internal data bus DD, and the control inputs of each i-th switch 11 _{i are} connected to the corresponding ith internal bus Ui of the most significant symbol pointers, the outputs of all W switches 11 ₁ , 11 ₂ , ..., 11 _{W are} connected to the corresponding W groups of inputs from k bits, starting from the second group of inputs, output buffer 12, outputs Q which are the external outputs of the device 16.

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