PT96482A - Processador de endereco para um processador de sinal - Google Patents

Processador de endereco para um processador de sinal

Info

Publication number
PT96482A
PT96482A PT96482A PT9648291A PT96482A PT 96482 A PT96482 A PT 96482A PT 96482 A PT96482 A PT 96482A PT 9648291 A PT9648291 A PT 9648291A PT 96482 A PT96482 A PT 96482A
Authority
PT
Portugal
Prior art keywords
processor
router
signal
signal processor
router processor
Prior art date
Application number
PT96482A
Other languages
English (en)
Other versions
PT96482B (pt
Inventor
Tore Mikael Andre
Karl-Gunnar Andersson Rojas
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of PT96482A publication Critical patent/PT96482A/pt
Publication of PT96482B publication Critical patent/PT96482B/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/066—User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Debugging And Monitoring (AREA)
PT96482A 1990-01-16 1991-01-15 Processador de endereco para um processador de sinal PT96482B (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9000155A SE465393B (sv) 1990-01-16 1990-01-16 Adressprocessor foer en signalprocessor

Publications (2)

Publication Number Publication Date
PT96482A true PT96482A (pt) 1991-10-31
PT96482B PT96482B (pt) 1998-07-31

Family

ID=20378264

Family Applications (1)

Application Number Title Priority Date Filing Date
PT96482A PT96482B (pt) 1990-01-16 1991-01-15 Processador de endereco para um processador de sinal

Country Status (20)

Country Link
US (1) US5282275A (pt)
EP (1) EP0438991B1 (pt)
JP (1) JPH05506735A (pt)
KR (1) KR970008186B1 (pt)
CN (1) CN1022591C (pt)
AU (1) AU644848B2 (pt)
BR (1) BR9007978A (pt)
CA (1) CA2070668C (pt)
DE (1) DE69029796T2 (pt)
DK (1) DK0438991T3 (pt)
DZ (1) DZ1478A1 (pt)
ES (1) ES2096583T3 (pt)
FI (1) FI98326C (pt)
GR (1) GR3022380T3 (pt)
IE (1) IE77511B1 (pt)
NO (1) NO301951B1 (pt)
PT (1) PT96482B (pt)
SE (1) SE465393B (pt)
TN (1) TNSN91002A1 (pt)
WO (1) WO1991010955A1 (pt)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448706A (en) * 1992-05-13 1995-09-05 Sharp Microelectronics Technology, Inc. Address generator for multi-channel circular-buffer style processing
DE69325207T2 (de) * 1992-06-15 1999-12-09 Koninkl Philips Electronics Nv Prozessor zur Verarbeitung zeitdiskreter Signale
US5463749A (en) * 1993-01-13 1995-10-31 Dsp Semiconductors Ltd Simplified cyclical buffer
JPH07244649A (ja) * 1994-03-08 1995-09-19 Fujitsu Ltd 割込処理分散方式
FR2718262B1 (fr) * 1994-03-31 1996-05-24 Sgs Thomson Microelectronics Mémoire tampon à adressage modulo.
JP2820048B2 (ja) * 1995-01-18 1998-11-05 日本電気株式会社 画像処理システムとその記憶装置およびそのアクセス方法
US5764939A (en) * 1995-10-06 1998-06-09 Lsi Logic Corporation RISC processor having coprocessor for executing circular mask instruction
JPH11109911A (ja) * 1997-09-30 1999-04-23 Fuurie Kk 表示装置
GB2386485B (en) * 2002-03-12 2004-06-23 Toshiba Res Europ Ltd Modulo addressing apparatus and methods
US8117248B2 (en) 2005-02-28 2012-02-14 Hitachi Global Storage Technologies Netherlands B.V. Digital filter instruction and filter implementing the filter instruction
US8051090B2 (en) * 2007-12-28 2011-11-01 Realtek Semiconductor Corp. File management method of a ring buffer and related file management apparatus
US8219782B2 (en) * 2008-09-18 2012-07-10 Xilinx, Inc. Address generation
KR102244613B1 (ko) 2013-10-28 2021-04-26 삼성전자주식회사 Ｑｍｆ 필터링 방법 및 이를 수행하는 장치
CN109408276A (zh) * 2018-10-25 2019-03-01 江苏华存电子科技有限公司 一种纠正码中规律交错器低延迟平行化架构位址绕线机制

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0042452B1 (en) * 1980-06-24 1984-03-14 International Business Machines Corporation Signal processor computing arrangement and method of operating said arrangement
SU1223346A1 (ru) * 1984-08-25 1986-04-07 Предприятие П/Я А-1811 Нерекурсивный цифровой фильтр
US4722067A (en) * 1985-03-25 1988-01-26 Motorola, Inc. Method and apparatus for implementing modulo arithmetic calculations
US4800524A (en) * 1985-12-20 1989-01-24 Analog Devices, Inc. Modulo address generator
US4908748A (en) * 1987-07-28 1990-03-13 Texas Instruments Incorporated Data processing device with parallel circular addressing hardware

Also Published As

Publication number Publication date
CN1022591C (zh) 1993-10-27
EP0438991B1 (en) 1997-01-22
EP0438991A1 (en) 1991-07-31
AU7188291A (en) 1991-08-05
CA2070668A1 (en) 1991-07-17
FI98326B (fi) 1997-02-14
DE69029796D1 (de) 1997-03-06
NO922568L (no) 1992-06-29
GR3022380T3 (en) 1997-04-30
JPH05506735A (ja) 1993-09-30
PT96482B (pt) 1998-07-31
FI923253A (fi) 1992-07-15
KR970008186B1 (ko) 1997-05-21
SE9000155D0 (sv) 1990-01-16
NO301951B1 (no) 1997-12-29
SE9000155L (sv) 1991-07-17
TNSN91002A1 (fr) 1992-10-25
BR9007978A (pt) 1992-12-01
AU644848B2 (en) 1993-12-23
ES2096583T3 (es) 1997-03-16
DE69029796T2 (de) 1997-05-07
CN1053693A (zh) 1991-08-07
DZ1478A1 (fr) 2004-09-13
FI98326C (fi) 1997-05-26
IE77511B1 (en) 1997-12-17
US5282275A (en) 1994-01-25
FI923253A0 (fi) 1992-07-15
CA2070668C (en) 1996-06-18
NO922568D0 (no) 1992-06-29
WO1991010955A1 (en) 1991-07-25
SE465393B (sv) 1991-09-02
IE910023A1 (en) 1991-07-17
DK0438991T3 (da) 1997-02-10

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Legal Events

Date Code Title Description
BB1A Laying open of patent application

Effective date: 19910725

FG3A Patent granted, date of granting

Effective date: 19980409

MM3A Annulment or lapse

Free format text: LAPSE DUE TO NON-PAYMENT OF FEES

Effective date: 20001031