PT79224B - Electronic contacts and associated devices - Google Patents

Description

DESCRIPTION OF THE INVENTION

that INTERNATIONAL STANDARD ELECTRIC CORPORATION, North American, in. with its registered office at 320 Park Avenue, New York, New York 10022, United States of America, wishes to obtain in Portu- gal, paras

«ELECTRONIC CONTACTS AND DISPOSAL. THESE ASSETS THAT ARE ASSOCIATED ".

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The present invention relates to electronic contacts that allow to establish a low or high impedance between first and second terminals, under control of a circuit that provides a control signal between a third and a fourth terminals.

Such electronic contacts are used, for example, in Belgian patent No. 896 388, in particular with respect to a capacitively controlled capacitive circuit which allows to positively or negatively charge a capacitance which, according to the signal of said load, opens or closes a contact electronic circuit consisting of two oppositely coupled DMOS transistors, in such a way that their discharges form respectively the two terminals of the electronic contact, while their sources are each connected to the same capacitance terminal and their respective capacitors. ports are both connected to the other terminal of the capacitance, with the possibility of the latter being the parasitic capacitance between these paired terminals. In this way, using transistors capable of withstanding relative stresses

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In this case, an electronic contact can be inserted which can be inserted into a circuit in which one or other of the polarities may arise at the contact terminals. In fact, when the weight of the load in the control capacitance for the contact is such that it does not provide a low resistance passage, i.e., that the two transistors are blocked, the parasitic diodes that appear, for this state of the transistor, between the source and the discharge, are thus also coupled in series, which maintains a high impedance to whatever polarity is applied by the circuit in which the contact is inserted.

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An object of the present invention is to enable the use of a more advantageous type of electronic contact, also capable of being controlled by the polarity of the load of a capacitance, and particularly a thyristor type device, adapted to operate with high burst voltages (300 Volts , for example) as contemplated in the above-mentioned patent but which can only be passed naked. although the transistors of the above-mentioned patent have reverse properties, i.e., they may conduct current in one or other of the directions but only block a voltage polarity.

The general aim of the present invention is

a and 9

permit the use of such electronic contacts while avoiding a complication of the control circuit.

According to a first feature of the invention, the electronic contact defined above is

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since two auxiliary electronic contacts are provided and for allowing the establishment of a low or high impedance, between the. first and third terminals, the conditions of .impedance of these two auxiliary contacts being

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Such an arrangement offers the advantage that two electronic contacts of the thyristor type can be connected top to bottom and controlled with the aid of the same control circuit, and particularly that of the aforementioned patent, which uses a positive or negative charge for a capacitance. close or open the electronic contact. Indeed, with the help of the auxiliary electronic contacts, according to the polarity of the voltage applied to the terminals of the electronic contact consisting of two polarized contacts connected in opposite bypass, it will be possible to automatically obtain a connection between a terminal of the control capacitance and In such a manner, the same capacitance loading circuit, i.e. the AC / DC converter voltage doubler described in the above-mentioned patent, should always be used to close or close the main electronic contact having a given power. open one of the two polarized contacts which is actually inserted in a load circuit and depending on the polarity of the voltage arising at the terminals of those contacts connected in opposite shunt.

On the other hand, the advantage of the thyristor electronic contacts adapted to be controlled in the indicated way and with respect to the connected DMOS transistors in series as opposed to the Belgian patent mentioned above, instead of the proposed end-to-end connection, is that the resistance

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to the closed state of the contact is distinctly to is, below XO ohms instead of 25 + 25 ~ 50 ohms. In addition, for the thyristor solution, the required surface area of an integrated circuit is reduced to one fourth.

The present invention also relates to an electronic device which is part of a circuit which also includes a power source and a load, said device including means for limiting power dissipation.

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Such a device is already known, for example from PCT patent application WO 82/03733. Thereby the energy limiting means are designed so as to produce a current opposite to the voltage or I / V characteristic which, from the origin, rises to a maximum current at a predetermined voltage, remains in that current until a voltage and then drops suddenly to a current practically equal to zero. At the last breaking point of this feature, the energy dissipated in the device is maxima (maximum current and voltage) and in some circumstances this may be inadmissible, i.e., in case the device is to be integrated into an electronic chip.

An object of the present invention is to provide an electronic device of the above type, but with a low dissipation power.

This object is achieved by virtue of the fact that said energy limiting means are designed to produce a current opposite the voltage characteristic which, starting at the origin, crosses the load line

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of the device and thereafter tends to follow the axis of tension without re-crossing the load line defined by the short-circuit current through the device and the open-circuit voltage that crosses it.

3,000 EX. - 03-34

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8

The

The minimum energy dissipated in the device occurs at its working point, ie the point at which the i / V characteristic crosses the load line. Unwanted abnormal signals having various origins, such as lightning striking such a telephone circuit or main source of power accidentally connected and it, could affect the characteristics of the circuit. In fact, such signals are added to the normal signals generated by the power source so that the position of the load line is modulated. The work point then moves along the part of the i / v characteristic that crosses the load line. In the event that these unwanted abnormal signals become very intense, the load line may be displaced in such a way that the working point reaches the upper end of the i / V characteristic. This work point then becomes unstable and shifts to higher voltages. Since the i / v characteristic then follows the charge line, the energy dissipated in the device during this transition from the working point is reduced to a minimum. When the unwanted abnormal signals disappear, the load line returns to the position initially mentioned and due to the fact that the part of the I / V characteristic that follows the load line does not cross the load line, the working point moves from the highest tensions to their starting position. This would not be the same if there were a cross between this part of the characteristic i / see load line. In fact, such a crossing would create a different working point from the one mentioned above and

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would affect the normal operation of the electronic device,

. Another object of the present invention is per. for relatively small voltages, currents which are much larger than the short-circuit current flowing through the electronic device, while maintaining the advantages mentioned above for the higher voltages.

MOO. 71 - 3,000 EX. - 03-34

This object is obtained because the part of that current contrary to the voltage characteristic crossing said charge line has a first portion which extends for voltages which are relatively much smaller than said open circuit voltage, for a relatively much stronger current than said short circuit run and a second portion which is joined to said first portion referred to the part of the characteristic following the load line.

The working point of the device can thus move along the first portion of the 1 / V characteristic so that the current in this device can reach said relatively high value for the small voltages without activating the energy limiting means. For higher voltage values the device operates as described above.

Another object of the present invention is also to use such electronic contacts in telecommunication systems and particularly in telephone line circuits, in order to enable the accomplishment of various supervisory and control operations, including the provision of a

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* »

which previously were usually performed by relay contact means even at central stations where the rest of the equipment was electronic

Thus, the invention is also related to a line circuit of a communication system comprising a series of impedances on each of the two line conductors and contacts on either side of these two impedances, allowing selectively to connect its terminals on the side from the central or the line respectively or alternatively to the auxiliary circuits.

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Such a system can be found, for example, in the article published on pages 316 to 324 of the IEEE Journal of Solid State Circuits of June 1983 and more particularly on pages 317. It can be seen that the two sets of resistors serve to power the telephone line of a subscriber and also to measure the voltage that appears to cross these resistances and this for supervision and control operations. On the side of the central of these resistors, a bell current can be injected by means of the corresponding contacts and by measuring the voltages across the resistors, one can thus monitor the operation of the bell ring. On the other hand, on the other side of the resistors, the counts on the subscriber line side allow access to bars for carrying out tests, both internal (towards the exchange and through the series of resistors) and interned in the direction of the subscriber line. Hitherto, such contacts were generally accomplished by means of the exchange contact of three relays which automatically implied that when the fixed element of the contact was closed in relation to one of the

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by-pass control circuits, the severing member in series with one of the resistors was automatically opened and vice versa.

According to another aspect of the present invention, these contacts are constituted by four electronic contact pairs, the first connecting the line to the impedances, the second connecting them to the exchange, the third pair. by providing the line-side impedances to a first auxiliary circuit and the fourth by connecting them from the central side to a second auxiliary circuit.

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According to yet another feature of the present invention, only the first pair of electronic contacts is equipped with energy limiting means as described above.

According to a further feature of the present invention the eight electronic contacts, which are always driven in pairs, are further controlled in such a way that only eight combinations among the possible sixteen for the four pairs are permitted.

According to yet another further feature of the present invention, the control device of the four electronic contact pairs comprises a decoder adapted to be powered by three binary signals in parallel and which provide four output binary signals to control the four pairs of contacts.

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1

MOD. 71 - 3,000 EX- - O3-E4

In this way, it is particularly possible to realize, in the form of a single integrated circuit, not only a series of eight electronic contacts capable of withstanding relatively high voltages and operational pairs, but also the control of the operation of these electronic contacts, with the aid of a code comprising only three binary elements, such as directly by means of a signal corresponding to the pairs of electronic contacts. This versatility can also be increased by incorporating into such an electronic circuit a watch enabling the control circuits of the electronic contacts to be operated in a manner described in the above-mentioned patent, thus avoiding relying on a separate clock circuit.

The present invention will be better understood and other features thereof appearing in the claims will be better delineated from the following detailed description of preferred embodiments to be read in conjunction with the examination of the drawings accompanying said disclosure and which represent:

Fig. 1, the circuit of an electronic contact according to the invention

Fig. 2, the electronic contact control circuit of the above-mentioned and modified patent according to the present invention

Fig. 3, the telephone line circuit element incorporating eight electronic contacts according to the invention

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Fig. 4, the set of circuits

the eight electronic contacts, represent a single block in Fig. 3j

control

two in the form

Fig. 5, an input protection circuit shown in block in Fig. 4J

MOD. 71 - 3,000 EX. - 03-34

Fig. 6, an electron port shown was block in Fig. 4j

FIG. _T 7 a double electronic gate controlled by clock pulses and shown as a block in FIG. 4}

Fig, 8f is the clock pulse producing circuit and is shown in block in Fig. 4;

Fig. 9, a first logic circuit used to realize the block decoder in Fig. 4j and

Fig. 10, a second logic circuit used in said decoder;

Fig. 11, another embodiment of the electronic contact circuit of Fig. 1, including power protection circuitry according to the invention; Fig.

FIGS. 12 and 13, characteristics of the current contrary to the voltage of the power protection circuits of Fig. 11,

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Fig. 14, features of a force opposite to the voltage of the electronic contact shown in Fig. 11, the characteristic not being drawn to scale

Fig. 15, an FC fault indication circuit associated with the power protection circuits shown in Fig. 11 and also shown in Fig.

MOD. 71 - 3,000 EX. - 03 * 84

The electronic contact capable of withstanding substantially high voltages and shown in Fig. 1 may be part of a set of eight identical electronic contacts (Fig. 3) arranged in the form of four pairs of contacts, the two contacts of a pair being simultaneously open or closed, said combination being adapted to be used in a telephone line circuit and particularly as described in Belgian Patent δδ 896 468. In addition to the eight electronic contacts corresponding to that of Fig. 1 and to the eight circuits for such contacts shown in Fig. 2, corresponding essentially to the controlled capacitive load circuit of the Belgian patent NS, 896 388, Fig. 4 shows a decoder adapted to be activated by either three or four signals binaries. In the first case, the hi-possible combinations of the three binary signals are decoded into four output terminals respectively used to control the four pairs of electronic controls. In the second case, the enabling signal allows this time the four input binary signals to be applied respectively to the four electronic ports while the same signal inhibits the operation of the decoder. In addition, Fig. 4 comprises, at the output of the decoder, a con-1155,737

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which is adapted to produce signals appropriate to the capacitive load circuit of FIG. 2 and this with the aid of an oscillator which produces complementary clock pulses.

MOO. 71 - 3,000 EX. - 03-84

The five elements identified above, i.e. _f electronic contacts, the control circuit, the decoder, the converter and the clock oscillator may es tar associated in a same integrated circuit combining a logical contact low DCMOS voltage and TRIMOS contact The manufacturing technique used may particularly employ the process described in Belgian patent 897 139

The assembly then provides four pairs of electronic contacts adapted to lock in both directions, voltages of 300 Volts and having a dynamic resistance of 10 Ohms when conductive, the two terminals of each electronic contact floating relative to the control circuit. The four contact pins can be operated according to the 16 possible combinations, with the help of four binary signals or according to eight predetermined conditions by means of three binary signals.

Turning to Fig. 1, it is seen that the electronic control comprises two identical elements S and S ', such that only the first was shown in detail. Depending on the control signal, the circuit S may have an impedance either low or high, between its two

output terminals S and S to which they are connected, respectively.

respectively, the corresponding terminals S 'and S * of S', the two circuits thus being connected in anti-derivation. This allows them to be operated under three different conditions: both S and S 'have a high impedance between their terminals, S

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has a low impedance for a polarity of teas at the terminals of the contact, while S 'may also exhibit this low impedance but for the other polarity.

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The S circuit is of the TRIMOS type essentially consisting of a T transistor of the PNP type associated with a transistor T ₀ of the NPN type so as to form a thyristor between terminals and S ^. The manufacture of such a device generally leads to the emergence of a PNP-type parasitic transistor T which is connected in parallel to the first two. This thyristor combination is controlled by the transistor N of the DMOS type associated with the transistor P of the PMOS type and whose ports interconnected to the same terminal S ^ has a capacitance C directed to the terminal S% of the contact at which the discharge of the transistor P and the source of the transistor N are alloyed.

Thus, assuming that the capacitance C has been positively charged at its terminal connected to the two ports of the transistors P and N with respect to the terminal S, and that on the other hand, the voltage at the terminal S is

X * 1

more positive than that of S, transistor N becomes

which allows the current to flow from the terminal to the

terminal S through transistor T due to transistor NZX

if short-circuited by its discharge / source passage to the base of the

transistor T to which this discharge is connected, the transmitter being connected to S *. The effect of this

T is to pump current to the base of the transistor T which 1 A

is directly connected to the T manifold so that T, which is of the NPN type, begins to pump current into the baJH

T is connected directly to the collector of the T whose 1

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emitter is directly connected to Sp Thus, by this cumulative effect, the two transistors T and T are co_

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located in a saturation mode, providing a low impedance between S and S, transistor T which is of the same PNP 1 Z type j

that Τ, with the bases and the emitters of these two transis

respectively, while the manifold

of T is in the potential of S, it becomes also conductive but, 3 2

as indicated, this refers to a parasitic element without influence on the main operation of the circuit.

Offering the polarized contact S a low resistance between and S ^, it can now be reset to its high impedance condition by means of a negative charge or capacitance C, dragging this negative potential on the ports of the transistors P and N, relative to S ₂ , the conduction of the transistor P which is of the FMOS type. While the transistor N of the type NMOS has its discharge connected to the base of Tp the source of P is connected to the collector Τ, in such a way that P extracts current from the collector Tp so that the current of the base of becomes condutabilidade insufficient to maintain this NPN transistor which, by cumulative effect, drags its locking and T ^ e, tornando_se the tirostor ICJ / 2 ^ ⁿ ° conductive. It will further be appreciated, on the basis of Fig. 1, that the substrates P and N are connected to the outlet N and the source of P, respectively.

The other contact S>, only shown as a block in Fig. 1, functions exactly as described, but this time under the control of a positive or negative charge on the capacitance C *, and more particularly,

at its S terminal. with respect to its S terminal. But 4 z

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these operations of the contacting medium S 'will occur this time when the polarity of the circuit in which the switches are inserted in anti-tapping is positive in S ¹ with respect to S _2. It should be noted that the realization of S / S 'in a single circuit. to-one draws a link between the common base of T * and T for the two contacts S *.

MOD. 71 - 3,000 EX. - 03-84

As already indicated in the Belgian patent Nô. 896 388, capacitances such as C and C 'may be comprised of parasitic capacitances, particularly those appearing at the ports of transistors P and N, in the case of capacitance C. Both C and C' can be charged with a desired pority by intermediate circuit of the control circuit shown in Fig. 2 and corresponding essentially to a

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already described in the Belgian patent mentioned last.

In fact, the transistors NA and NB, which are both of the type NMOS, are represented in Fig. 1 as having their sources directly connected to the S-terminal, while the discharges of NA and NB are respectively connected to S and S. On the other hand, NA's door is

X

linked to S while NB is bound to S. Such a setup X

As a consequence, if the potential of S is, for example, higher than that of S, that of S can not be outside that limit, and the transistors NB and NA are as respectively conductive and which in fact implies that the terminal S is substantially (0.7 Volt) connected to the terminal S and with reference to Fig. 2 it is seen that it is in fact the capacitance C that is effectively connected between the terminals S, and S_ of the loading device shown in Fig. 2,

4 3

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The parasitic diodes between the source and the discharge of the transistors NA and NB, i.e., DA and DB as shown in Fig. 1, are polarized in such a way that they play an analogous role in enabling the terminal to be aligned with the potency at the terminal when the latter is less positive than the terminal S

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Of course, in view of the symmetry of the circuit constituted by the transistors NA and NB, when the potential of is higher than that of S *, the conditions are inverted and following the conductability of NA or DA, the terminal S is now practically connected to the terminal In such cases,

In such circumstances, it is the capacitance C 'which is effectively connected to the output terminals and the control circuit of Fig. 2,

In this manner, a single control circuit can close or will automatically open the electronic contact means S or S 'depending on the polarity of the voltage applied in between terminal S ^ / S * on the one hand and S ^ / S * ^ P ^and ^ - ° another.

As already indicated, the circuit of Fig. 2 is essentially described in Belgian patent No. 896 388 and particularly with respect to Fig. 6 of that patent which is very similar to Fig. 2. The latter constitutes an AC / DC converter in the form of a full-wave cascade voltage doubler and symmetrically supplied by complementary polarity pulses. The polarity control of the circuit of Fig. 2 is effected by the DC signal applied to the series of capacitances C, while the complementary regulatory signals

CL and CL are permanently applied to the other two

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input capacitances series and C ^ respectively the same manner as for the output capacitance C / C * (Fig LJ present between the terminals and ^s 2 / ^s' y ^{the three} ® ^are input capacitances are not necessarily constituted by discrete physical elements, the first voltage doubler rectifier consists essentially of a series of capillaries C * followed by a series diode D *, the transistor P of the type PMOS to reach the capacitance of the C / C branch between the terminals S and S, the diode of derivation of this voltage doubler D _{2 being} connected as indicated, between the junction of D *, on the one hand, and that of C ^ and the port of P, on the other, When the control potential DC applied to series capacitance C corresponds to the regulatory impulses

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CL applied to the C ₂ series capacitance is the described load circuit which is effective at securing a capacitance load C / C ', such that the potential at the S-terminal will be

(I.e.

more positive than that of the S ^ terminal,

In the reverse case, when the DC control signal applied to the series capacitance corresponds to the regulator pulses CL applied permanently to the series capacitance C ^ the output capacitance C / C 'will be charged,

with S being more negative than S. with the elements of this 4 3

voltage transformers to negatively charge the output tap capacitance to be C ^, D ^, N * and Dwh corresponding respectively to Cp D *, P * and D ₂ , as shown in Fig. transistor N * of the type NMOS,

As in Belgian patent N2, 896 388, the positive charge circuit utilizing the conductivity of the trans

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MOO. 71 - 9,000 EX. - 03 * 94

sistor P is completed by the transistor N of the type NMOâ,

is connected to S and its source to the capacitance C for 3

means of a D-series diode, the N port being connected to 5 &

S . This connection thus allows to complete the return circuit. not to the positive charge, providing a passage between the "ground" output terminal S and the "ground" input terminal constituted by the right-hand electrode of the series capacitance C ^. Similarly, under a negative load of the output capacitance between S and S, the return pass is this time

4 3

carried out by means of the PMOS transistor P 2 in series with the diode D, these two elements corresponding to N 2 and D 2 respectively as indicated by the circuit which is practically identical to that of Fig. 6 of Belgian patent N2896 388 with other than the dxodes and D which at this time may be on the source side of the transistors F and N, respectively, instead of being located on the discharge side as in the prior patent. Another version of this circuit, representing that in Fig. 4 of this prior patent, already places the diodes and

on the side of the sources of the transistors P ^ and Np but in this circuit the ports of the transistors P ₂ and N ₂ were interconnected to another circuit and not connected to the discharges of the transistors

P and N (S) in such a way that the diodes D and D are from. 114, 5th

the discharge side of the transistors and? On the other hand, in the version of Fig. 2, the four diodes Dp D2 and D4 are all located on the source side of the transistors, to which they are associated in such a way that, with the diodes Dp D4 and

all are arranged on the side of the three input capacitances ^ j / 2/3 * θ The last diode directly connects the capacitances C and C in the same way as in the previous patent

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and the Zener diodes D, D and D in parallel, respectively, 7,89

with the terminals ^and P £ ^{bakes a} source / discharging of transistor ..

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N and P are also connected in the same manner as before

mind.

MOD. 71 - 9,000 EX. - 03-94

The integrated circuit IC which may incorporate eight electronic contacts as shown in Fig. 1, as well as eight control circuits as shown in Fig. 2, appears in the form of a block in Fig. 3 corresponding essentially to a part of Fig (1) of the Belgian Pat. 896 468, which leads to a line circuit for an electronic telephone system. As shown in Fig. 3, a subscriber line (not shown) may terminate at the terminals LT and LT, preferably through a

X x *

overvoltage protection circuit, such as that which is

Belgian patent Ne 896 468. By means of the first

electronic touch S * part of integrated circuit TC, the termi

can be connected to the series resistor R * and then,

by means of a second emectronic contact in series, that is,

S 1, for the SLIC circuit containing other cirz elements

electronic line. The circuit between the second input terminal LT and the SLIC circuit is exactly like

z

S, R ", S corresponding to S, R, S, respectively. xzz ZZXXXZX

In addition to the series contacts that allow the connection of the grids.

tions between ^C ° ^c ^ ^rcu; * - ^{to S} LIC, these resistors

can also be connected via four branch contacts

The test circuits TC (S for R4 and S4 for R4) of the

subscriber side (LT.), on the one hand, and for the

ringer RC (S for R. and S for R) on the center side 41 x 4 *

(SLIC) on the other. The connections (not shown) from the feed resistor terminals P to ⁰ SLIC

enables the latter to monitor the potentials that appear through these resistances.

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The operation of the eight contacts is

controlled from the SLIC through four

undermine the terminal IC ^ / 2/3/4 ^con ^ t ° ^c s a pair as

already being controlled by the same signals so that

11/1 «

the two wires of the connection are switched simultaneously. The conductor which reaches IC50 is, however, indicated with dashed lines, since such a control can be performed according to a control model which uses only three binary signals, a select signal pattern applied to the terminal IC that determines whether three or four binary signals are used to control the four pairs of contacts S

H / 12

MOD. 71 - 3,000 EX. - 03-84

^S 2l / 22 ' ^S 3l / 32 ® ^S 4l / 42 *

This versatility of the IC circuit

is in the fact that the location of these four contact pairs,

directly on each side of the resistors R and R "enable ax

ensure adequate control with a number of linking states that do not exceed eight. Consequently, when the four contact pairs of the IC circuit are used for any application, line circuit or other, requiring between 9 and 16 possible conditions for the combination of these 4 pairs in their open or closed conditions, each of which signals ^^ binary terminals 1/2/3/4 ^con l ^R l di ^air ··

the status of a pair of contacts. On the other hand, particularly in the case of telecommunication line circuits. which will be described in more detail, can satisfy us with a maximum of eight conditions and the selection signal at the IC terminal will indicate this time that only the three binary signals at the terminals must be taken into account

and the eight possible combinations of these signals will be transformed with the aid of a DEC decoder in four

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binary signals each of which can control a pair of contacts.

This appears in the form of a block in Fig. 4, which represents the constituent elements of the IC circuit of Fig. 3, except for the electronic contacts and their capacitive charge control cir- cuits already described with respect to Figs. 1 and 2, respectively.

In Fig. 4, each of the IC2 / 3/4/5 inputs coupled to the input of a corresponding inverter

2/4 / $ θ ^C ° ^{m exception} in case of IC em where the connection is direct, through a protection circuit identical to PC

1/2 /

The PC circuit shown in Fig. 5 is shown.

The latter shows that the IC ^ terminal is

is directly connected to the output terminal A, the code

input torque for IC identified by ABCD, terminals 3

output B, C, D corresponding to terminals - ^^ P ^{and res} ~ 2/3/4

ctively. The input terminal IC is connected to the poles

V and V of a DC source through the diodes D and D respectively 111 /

the potential at IC50 / V between those applied at V and V, the latter potential being 0 Volt for example, being more negative than that of V, 15 Volts, for example. On the other hand the transistor P of PMOS type has its source link

from the V, its discharge to A and its door to V in such a way that it is continuously conductive. The transistor T ^, shown in dashed lines as being of the NFN type and having its junction bonded to IC e and its emitter at V,, may be used to bring a binary control signal to IC.. If your base has the potential of V *, it is conductive and leaves the

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current goes from V to V, through P and T in series, A ι Λ j 4

impedance of this last transistor being smaller than of the F,

terminal A remains at the potential of VFor the other side, if

the base of T _t is the potential of V in order to float T 4 2

terminal A is at the potential of V transmitted through

V

MOD. 7t - 3,000 EX. - 03-34

Fig. 4 indicates that the four potentials

(ABCD) at the outputs of ^^ 1/2/3/4 ° P ^ ^s ^^ ° ^CA is such terminals ^sa

such as D from a GD port, through inverters such as IV,

4

in such a way that a complementary binary code ABCD appears on the inputs of these ports (ports identical to GT, provided for signals at terminals A, B and C) with respect to the binary code ABCD at the outputs ^^ j / 2/3/4 ^{r s} * ^ ® these binary signals ABC are on the other hand applied to decoder DEC, as the concrete two signals a and B complementary to a and B

and obtained by inverters IV and IV in cascade with IV and IV, 0 7 1

respectively.

Before explaining with the aid of Figs. 9 and 10, how the DEC decoder can advantageously transform the eight combinations of three binary ABC signals into particular combinations of four binary signals in their EFG II outputs, the description of the other elements of Fig. 4 will be completed, starting with the above GD port, which is connected to an identical GH port powered by the output H of the DEC decoder, three identical ports (not shown) being used and similarly connected to the outputs EF G.

Ports such as GD and GH are contro-2255.737

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are determined from the IC terminal terminal which determines the mode of IC operation, with or without decoding by the DEC, the binary signal being IC.. applied to all ports such as GD / GH, as well as the complementary binary signal obtained by the inverter IV

ΜΟΒ. 71 - 3,000 EX. - 03-84

Fig. 6 repeats the circuit of a transmission port such as GD and GH, which connects the terminal

mm j

input D or H to the output terminal DH through the source / discharge passage of the transistors Ν 'and F', which are connected in anti-derivation and which are respectively of the types NMOS and PMOS. Its ports are respectively connected to IV and IC ^ to GD and vice versa to GH, in such a way that one of these ports is conductive and the other one blocked in function of the IC ^ selection signal which allows to choose for such terminals as DH, both the D signal and part of a binary code of four elements each identifying a pair of contacts such as (Fig. 3), as the H signal, i.e., one of the four

binary elements decoded by DEC from the three binary ABC elements.

As indicated in Fig. 4, the terminal signal such as DH still has to be synchronized by the port such as GC with the regulator pulses provided by the CO oscillator to be applied, such as the complementary regulator signals GL and CL, at three capacitáncxas of entrance of the

symmetrical AC / DC converter (Fig. 2) which serves to positively or negatively charge the C / C 'capacitances that control the S / S * polarized electronic contacts connected in anti-bypass (Fig, 1).

Fig. 7 shows the door circuit

-2355,737

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MOD. 71 - 3,000 EX. - 03-84

of the clock. The binary signal at the terminal as DH and quej determines the open or closed condition of the corresponding contact, and this time applied · to control the GCA and GCB ports identical to those of Fig. 6 but to the inputs from which the complementary regulator pulses CL and CL used by the CO coil. The ports GCA and GCB are controlled in a complementary manner by the signal ΒΠ and its complement, produced by the inverter IV, in such a way that the output signal DC of the port GC is either a pulse CL or a pulse C1. complementary, according to the value of the binary signal in DII.

8 shows the clock oscillator CO and comprises three inverters in a circuit which also comprises the resistors in series and R ^ on each side of the inverter IV * the output of IVj, feeding a second series of three inverters

in the cascade, the latter of which provides the regulating pulses CL and IV the complementary pulses CL. The oscillator

A "

CO is also fed by voltages (not shown) and Vp latter being connected to the inlet IVU / _12/13 Eve I ^attraction of the capacitances respectively. These can be

of 6 peak and R4 of 20 km to produce oscillations at a frequency of the order of 1.2 MHz.

As indicated by the multiple arrows of Fig. 4, the oscillator CO feeds the four ports such as GC whose output terminal controls two load circuits such as those of Fig. 2 to control a pair of contacts such as that of Fig. 1 This last link is performed by the inverter IV "that provides the DC signal so that the three other ⁸

tional reach the capacitances ^C j / _2/3 ^{of Fig 2} * ^im P ^{and through} -2455,737

Remmerie 2-2X

output power of an inverter.

The DEC decoder of Fig. 4 will finally be described, also with reference to Figs. 9 and 10, which represent the type of logic circuits advantageously used for their realization.

MOD. 71 - 3,000 EX. - 03-84

To this end, the eight conditions of a telephone line circuit which can be characterized by a combination of input signals ABC of the DEC decoder should first be defined. These eight conditions are identified by the following table of compliance:

^S / 12 ^S 2l / 22 ^S 3l / 32 ^S 4l / 42 ABCYE FGH

Isolated

Rehearsal Rehearsal Rehearsal Rehearsal

External test

Internal test

Supervision

Direct switching

0 0 0 1 1

0 0 10 1

0 10 0 0

0 110 0

10 0 10

10 10 1

110 0 0

1110 0

1 1 1

1 0 0

1 0 0

1 1 0

1 0 1

0 0 1

0 0 1

0 1 1

The frame comprises three columns corresponding to the input signals ABC, a fourth column for an intermediate signal Y, the utility of which will appear later, and four other EFGH columns which define the signals at the output of the DEC decoder, each of the latter corresponding columns 2555.737

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MOO. 7,000 - 3,000 SX. - 03-84

'11 / 12 ^{and S} 2l / 22 ° ^S3 ° ^{fechad S} are open. THE

the status of a pair of contacts, for example, E

. The complementary bar above the references identifying these contacts corresponds to the complementary shape of BF 6 H in such a way that the indication 0 identifies a closed contact for the columns in question, with 1 for the open contact. The eight conditions for the line circuit appear in successive series, in ascending order for the binary code, from 000 to 111 for ABC, the latter code corresponding to the direct switching of the line circuit of Fig 3, i.e. the series contacts s

and the fourth-row shunt contacts 31/32 ^and 41/42 provide the code 011 for ABC as ring-tune conditions that allow to connect RC (Fig. 3) to the subscriber line terminals through the resistors

so that the voltages in the latter can also be used for supervision of the ringing operation of the called subscriber ring. The sixth line corresponds to code 101 for ABC and to an internal test (towards the center) permitin of this time, connect the CT test bar to the SLIC through resistors ^ ^{or or} b ^er hand, the external test (in

towards the subscriber) of the fifth line (100 for ABC) produces a connection between TC and terminal LT ^ ₂ without passing through the resistors while campainhada test (001 for ABC) interconnects this time RC and TC through the resistors.

Apart from these five conditions, the line circuit allows the complete isolation of the resistors (000 for ABC), the supervision of the bell (010 for ABC) where the CT is additionally derived by ^ 31 / 3-7 ^{on the} output connection

-2655,737

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a supervision (110 for ABC) in which TC is also derived, but this time, by normal binding.

MOD. 71 - 3,000 EX. - 03-34

The eight codes enabling these various conditions were distributed by the eight contact combinations S _{n / 12} , S _{2j / 22} , S. ₄ , S _{4j / 42} as indicated by the table and this to allow as simple realization as possible by DEC, In fact, the correspondence table indicates that Ε = B and that F = A, 'except for ABC = 10 (1, that G = 0 except for ABC = 000 and BC = 11, and finally that

Mff

H = A except for ABC = 000. The realization of the DEC decoder is facilitated by these simple matrices and by the introduction of Y = 0 except for BC = 00, where Y is an intermediate binary signal appearing in the fourth column of the frame.

Consequently,

corresponding Boolean relations:

can be written

Έ «B (+ + C) = + + BC F = + + Ύ = Λ + BC

G = Ã Y + BC = Ã BC + BC

Η = A + Y = Λ + BC

Y = BC or Y - B + C

in which the second expression for E (Fig. 9) will facilitate a comparison with G (Fig. 10) and those for F, G and H are obtained substi. Y, corresponding to the value indicated, corresponds more directly to the logic circuits used and more precisely to the derivation of Fig. 10 to G.

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3,000 EX. - 03-34

Fig. 9 shows the CMOS logic circuit which allows to realize E using three connected PMOS transistors as indicated, between the potential V and the output terminal which provides a. E, as well as three connected NMOS transistors as indicated between the output terminal and the potential V ^. The three transistors are identified by the signals A, B, C applied to their ports for both the PMOS transistors and the NMOS, its source / discharge passages are connected in such a way that B is in series with a parallel AC combination for the PMOS transistors, while the duality of the circuits comprising the NMOS transistors implies that B must be in parallel with the series combination C. Since the signals A, B, and C respectively are the complement of those that intervene in the equation giving E, it is observed in particular that if B is at low potential, transistor B between the PMOS transistors is conductive , whereas the corresponding transistor A and C between the transistors FMOS, replacing them by a short circuit, while by duality the transistors NMOS A and C are replaced by an open circuit, E would be in (V) which ranged from Ε = B, the latter being the first factor of the expression that defines E, and a condition which, as previously indicated, is true for all combinations of ABC, except 100, Mas in the latter combination, with Λ and C at high potential and low potential B, the FMOS transistors controlled by A and C are both blocked while the corresponding NMOS transistors are both conductive. For this particular combination, E is thus a low potential (V) corresponding to E = = B. For the other seven combinations, these four transistors A and C (PMOS and NMOS) are irrelevant because they can not even short-circuit the blocked transistor B (NMOS) nor

-2855,737

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Conductive conductors (PMOS) in an open circuit,

is relevant and that one has Ε = B.

you

put the transistor as only B

WOD. 71 - 3,000 EX. - 03 * 84

Fig. 10 shows the circuit which per. to perform G according to principles identical to those that were. 9, allowing the above-mentioned second form for E a direct comparison with the first one for G. In fact, it is readily observed that there are four variables in. dependent transistors A, B, C and Y for G instead of just three (A, B and C) for E. In this manner, four pairs of PMOS and NMOS connected transistors as indicated are now required and are plotted to the intermediate value variable Y,

To obtain the latter, from B and C, as well as FeHdeAeYedeAeY, respectively, it is sufficient to take each time half of the circuit of Fig. 10, ie transistors B and C, both for the series of PMOS transistors and for the NMOS derivative transistors, by controlling them by appropriate si nes, for example, B instead of B and C instead of C to provide Y.

In this way, the DEC decoder only uses the five signals A, A, Β, B and C saving one inverter to C (Fig. 4), using only 13 PMOS and 13 NMOS transistors. Reference is now made to Fig. 11 which shows the electronic contact S of Fig. 3 in detail, this contact being a modification of that shown in Fig. 1. Although it is still of the TRIMOS type, the thyristor TRX formed between the terminals S It differs slightly from that shown schematically in Fig. 1, in that the PNP transistor T ^ is now replaced by a PNP transistor which

-2955,737

Remmerie 2-2Χ

has two separate manifold electrodes connected, respectively, to the gate electrodes of two NPN transistors Q and

jit

Q which replace the NPN transistor T,

of the transistor T ^. In addition, the individual power protection circuits, described below in more detail, are associated with the TRX,

3,000 EX. - 03-34

It should be noted that the contact S is

but the other six contacts do not include

protection. The electronic contact S of Fig. 11

includes two identical switching circuits S and 3 'which are

coupled in anto-derivation. More particularly, the terminal

S of S is connected to terminal S * of S ', while terminating it] X Jb

of S of S is connected to the S * terminal of S '. The circuit of

X

The aforementioned control is linked with both S and S *

via the S ^ terminus. The switching circuits S and S 'are also

both provided with a detection output terminal DT, DT12 '

of which only DT4 is connected to an FC fault indicating circuit, via the DET4 detection terminal. FC is also included in IC integrated circuit and will be described later. Because S and S ¹ are identical only one of them, for example S, is now considered.

As already mentioned above, the transi

tor Q has two distinct collector electrodes

tors attached to the base electrodes of transistors Q and Q,

A 3

respectively. The collector electrodes of the transistors and Q are both connected to the base electrodes of Q.

O ^A

The terminal S, is connected to the emitter electrode of Q, and ter1 1

minai S is connected to the emitter electrode of Q, directly, 2 &

and to the emitter electrode of Q via a sensor resistor

-3055,737

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The Q% base electrode is also connected to the collector electrode of an NPN transistor 0, the emitter electrode of which is

4

to the S terminal. The terminal S is connected to the electrode of Z 1

the cascade connection of a diode D1 to the collector-emitter path of an NPN transistor and a resistor

12 *

MOD. 7J-3,000 EX. - 03-84

The cathode of the diode D is also connected to the emitter electrode of Q via the series connection of a resistor R3 the discharge-source passage of an NMOS transistor N and a resistor R .. The junction point of the re

11 14

R? and the source electrode of N. is connected to it 14 11

the base electrode of an NPN transistor Q whose collecting electrode

is connected to the base electrode of Q and whose electrode emisw

is connected to the S-terminal cathode of the diode D is also connected to the discharge electrode of an NMOS transistor N, the source electrode of which is connected to the base electrode of Q together with the output detection terminal DT- . The N and N port electrodes are both connected to the

11 1 jw

discharge of a DMOS transistor N which has its source electrode connected to the terminal and its gate electrode connected to the S terminal. It should be noted that the DMOS N transistor has a parasitic diode (not shown) whose anode is connected to the N-source electrode whose cathode is connected to the discharge electrode of this transistor, and that N and N NMOS transistors have high capacitances of the gates (not shown)

badas).

The thyristor TRX is ON or OFF by means of MOS transistors (not shown) corresponding to the transistors P and N of Fig. 1, controlled via the terminal

-3155,737

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FR; JL

1

S ^. As already mentioned above, the switching circuit S includes power protection circuits which are also adapted to be controlled.TRX and the operation of which will be described in detail below.

MOD. 71 - 3,000 EX. - 03-84

The thyristor TRX is associated with two separate power protection circuits, respectively called the primary and secondary energy protection circuit. 0 primary power protection circuit comprises the components ^^ D, ^N 12 '5 ^' ^R θ 11% ^{and> ma} ^ ^s P ^c hi ^air ularmente limits the current through TRX when the voltage across the circuit S exceeds a value. The secondary power protection circuit comprises the components D,

£ X

^N ''> Q, R and R. It will be appreciated that in the following description

It is assumed that the voltage at the terminal S is positive with respect to that of the terminal S so that the diode D is biased forward. The same operation is valid for S * in case the voltage at S ' ₉ is positive in relation to that of S ^r ^.

The primary and secondary protection circuits are turned on and off by respective NMOS transistors N and N, which are themselves controlled by the DMOS transistor N, when the thyristor TRX is in the ON state, a positive control voltage of about + 20 Volts applied to the S ^ terminal is transmitted to the N and N gate electrodes via the parasitic diode of the

transistor N. As a result, the transistors N and N,

13 11 ι z

are conductive and the protective circuits are in operation. To turn the TRX thyristor OFF, the control voltage err

S, is decreased from its positive value by about + 20 Volts 4

-3255,737

Remmerie 2_2X

-and

MOD. 7t - 3,000 EX. - 03-34

to a negative value of about - 20 Volts. During this voltage transition the TRX switches OFF when the voltage in S ^ al drops about -3 Volts, while the protection circuits remain in operation, even when the parasitic diode of the DMOS N transistor is blocked. In fact, the transis

A 0

NMOS sensors are still conductive due to the positive voltage coupled to their gate capacitance. When the S-voltage reaches about -8 Volts, transistor N makes * TXU

is conductive, so that this negative control voltage is applied to the N and N gate electrodes ^and blocks them. The power protection circuits are then switched off.

The transistor M coupled to the gate capacitances of the

N and N thus constitutes a retarding circuit XX XM

which shuts off the protection circuits for a time interval after the TRX is locked. Thus, the protection of this device remains operative while the TRX remains in the ON state.

When the TRX is in the ON state, no current flows through the primary power protection circuit, while the voltage across the switching circuit S does not exceed about three diode voltage drops. These three diodes are the diode D, the base-emisA1

of the transistor and the base-emitter path of the transistor

It should be noted that the current flowing through circuit 4

power protection is so small that the voltage drop across resistor R is negligible and that the

XA - «

through the discharge passages to the

Conductive transistor N is also negligible since this XA '

The last voltage drop is proportional to the base current of the transistor Q ^ which is still blocked. When the tension reaches 3355.737

Remmerie 2-2X

Since S increases, the transistor Q becomes conductive and | the Q ₁ current collector is discharged from the base electrode to the terminal S ^. Since the base current of the transistor Q ₂ is reduced, the current of its collector and hence the base current of transistor 0 are also reduced

tions. As a result, the portion β Ά) of thyristor TRX DES_ · 1 "

LIGA6SE, while its β2 / β2 moiety may retain ON as will be described below. During the above operation the main current of the transistor Q is limited by the resistance Reo transistor Q, which itself controls

side by the transistor N ^.

MOO. 71-3000 εχ. - 03-84

Considering only the β / β portion of the 1 x *

the current opposite the voltage characteristic of the switching circuit S would be represented in Fig. 12 where element 1 is the normal i / V characteristic of the forward-biased thyristor TRX. As shown, the voltage V rises to a maximum voltage equal to the voltage drop of the three diodes mentioned above (+ 2.1 Volts) and corresponding to a maximum current I of 320 milli-amps. Than

above, it follows that, the β transistor activates at a 4

which corresponds to the current I so that the OFF TRX following the element 2 of the i / v characteristic shown in Fig. 12. The current in the thyristor TRX and portantc in the switching circuit S is then substantially equal to zero, either is the voltage across this circuit, so that the 1 / V characteristic then coincides almost with the voltage axis for the voltages exceeding V ^. It should be noted that this l / V characteristic is valid for the thyristor TRX as for the switching circuit S.

-3455,737

Remmerie 2-2X

The DC load line 3 device d <

S is also shown in the diagram of the rig. 12,

It is defined by two points corresponding respectively to the

maximum current 1 ^. (70 milli-amps) in the telecommunication line

when the latter is short-circuited and at the maximum voltage

V (70 Volts) when this line is open. This line L

of the DC load 3, passes through the element 1 of the circuit 1 / of the switching circuit S at a stable working point 4.

♦

P

i

3

I

yl

The

3

i

I

s

3

0

I

When unwanted abnormal signals are applied to the telecommunication line, they are added to the normal signals generated by the telecommunication station so that the load line moves in the 1 / V diagram of Fig. 12. Such abnormal signals may have varying origins, such as such as lightning striking telecommunications lines or high voltage cables accidentally connected to these lines. The working point then moves along element 1 of the 1 / V face. When such abnormal undesired signals become very intense the load line may be displaced in such a way that the working portion reaches the upper end of the 1 / V face element 1, This working point then becomes unstable and moves for higher voltages while the TRX is OFF (element 2). However, the maximum voltage across the switching circuit S is limited to about 250 Volts by the overvoltage of the above-mentioned protection circuit (not shown), so that the working point is then located at point V on the voltage axis .

When the abnormal signals disappear, the DC load line returns to the position shown in Fig. 12 ç the working point moves from V (250 Volts) to V (70 Vol-35

55,737

Remmerie 2_2X

MOD. 71 ~ 3,000 EX. - 03-04

ts) where the element of the i / V characteristic of the TRX that coincides with the voltage axis, passes through the DC load line 3. The working point thus becomes stable at this voltage and since the primary power protection circuit is still active then it is impossible to I.IGAR the thyristor TRX. To allow the TRX to be ON again, element 2 and the part of an i / V characteristic of the switching circuit S that coincides with the voltage axis should not cross DC load line 3, so that no stable work, such as, should exist between and the normal working point 4. One solution is to use the secondary pro circuit. described below.

Considering only this secondary energy protection circuit, when the switching circuit S is in the state of IT, the current flows from S2 (Fig. 11), not only via TRX, but also via diode D,

Μ 1

resistance R ^, discharge-source passage of the NMOS transistor

and resistors R and R 2 in series. While the tension between

the terminals S e is relatively so small that the voltage drop produced by the above-mentioned currents through R and R in series is less than the base saturation voltage 11

- V signal of 0, the latter remains locked. The current I flowing through TRX then varies as a function of the voltage V measured through the switching circuit S, according to the element 5 of the I / V characteristic shown in Fig. 13. It should be noted that due to the values of the resistors which will be given later, the current I (Fig. 11) flowing through the TRX is much more intense than the current flowing through the secondary protection circuit. Thus, current I can be considered to be the current flowing through the circuit

3655.737

Remmerie 2-2X

and, as for Fig. 12, the i / V characteristic

MOD. 71 - 3,000 EX. - 03-84

of Fig. 13 is valid for the thyristor TRX as for the switching circuit. S. When the voltage between the terminals and S is so high that the voltage drop produced through

ít

R 2 and R 3 in series, by the above-mentioned chains, becomes

greater than V__ of O., the latter becomes conductive and forbe 6

therefore a branch for S * for the current collector

of Q · Thus the current of the base of Q "is reduced in result 1 3

than the impedance of TRX increases', so that current I

which flows through it varies as a function of V,

element 6 of characteristic i / v of Fig. 13.

is a function of the energy dissipated in the TRX because of

voltage drop across the switching circuit

S, not only depends on I because R is connected in series with

TRX, but also V, since an additional current that is

function of V flows through R _< . R 2 and R 2 are as defined above.

ii 1314 1314

current I would remain constant and would be equal to current

maximum value X, as shown by element 7 of the characteristic

Fig. 13. In this case, the energy dissipated in the circuit

the switching function S may become excessive since element 7 crosses the maximum energy dissipation line 8 of the circuit S. For the above reasons, the element 6 of the i / V characteristic should not cross the DC load line 3 For another due to the minimum dissipated energy in the switching circuit occurs at the working point of this circuit, i.e. at the crossing point of the element 5 of the i / V characteristic and the DC load line 3, the element 6 of the characteristic i / V must be chosen as close as possible to the DC load line 3 in order to obtain a minimum of energy dissipation in the switching circuit S. For that reason, the abrupt part of the element 6 of the i / V characteristic is chosen if-3755.737

Remmerie 2-2X

the abrupt part of the DC load line 3. The slope is a function of the R / R ratio. In fact, when it begins to drive, its base-emitter saturation voltage V can be defined by the following expression:

V ^V BE- ¹

R + R + R 11 14 13

Where V 1 is respectively the voltage across and the current flowing through the switching circuit S, This pressure immediately leads to

MOD. 71 - 3,000 EX. - 03-84

^ ll-HJ- ^V BE <h ⁺ W - ^{V (R} 11 ⁺ 1 *?

according to the values of the resistances that are

R = 7.6 ohms 11

R = $ 00 ohms 1 £

R "- = 145 Kilo-ohms

13

R ", - 1 Kilo-ohms

14

the following conclusions can be drawn:

* 13 »

* 14 ^

R.

11

the final expression is

= ^V BE · ^R U - ^V ' ^R 14

so that

I - - (v.

^R 14 - ^V)

Be

11 13

-38 It is clear from the above that the current I is dependent on the voltage R

14, V.

13

MOO. 71 - 3,000 EX. - 03-84

Since the element 6 of the i / V characteristic is chosen as close as possible to the DC load line 3 in order to limit the dissipated energy in the switching circuit S the maximum current I has to be selected lightly &

above I and the maximum voltage V must be chosen

(I.e.

slightly above V ^. In the present example and with the values of the resistances given above, 10000-400 amperes and about 100 Volts. However, according to requirements which are conventional for a telecommunication system, the protection circuit should only be activated for a current exceeding 300 milli-amps. If, for this reason, I is chosen to be higher than the required 300 milli-amps, and element 6 of the characteristic must be modified and a portion thereof may be located above the maximum energy dissipation line 8. In this case, when circuitry becomes active, the energy dissipated in S may be so high that the latter is destroyed.

The disadvantages of the two separately taken power protection circuits can be eliminated by combining these two circuits, this combination providing the general i / V characteristic of the switching circuit S shown in Fig. 14. This feature has element 1 and partially the element 2 of the I / V characteristic related to the primary power protection circuit and the element 6 of the i / V characteristic related to the secondary power protection circuit. From this figure it is clear that the

-3955 * 737

Remmerie 2_2X

the characteristic 1 / V crosses the aforementioned DC load line 3 in a single stable working point and that the energy dissipated in the switching circuit S is reduced to its given number as the element. 6 is very close to line 3 of DC load.

MOD. 7) - 3,000 EX. - 03-84

An FC fault indication circuit

is shown in Fig. 15, the FC has input terminals

DET and DET, terminals LT and LT, output terminal F and ter1 Z xzu

(-33 Volts) and V (-48 Volts). The fault indication circuit FC is only associated with the protection circuit S of the switching unit Sn (Fig, 11) and for the corresponding protection circuit of the switching unit S (not shown). This is sufficient to detect abnormal signals of any polarity in the

ring of telecommunication line connected between LT and IT *

X 4 /

The input terminal DET ^ of the FC is connected to the detection output terminal with the same designation as the protection circuit S of the switching unit S (Fig. 11), whereas the input terminal DET ^ of the FC is connected to the terminal protection circuit corresponding to S of the switching unit S (not

tated). The LT and LT terminals of the faX z reference circuit

FCs, are respectively connected to the terminals with the same ones as the subscriber line. The output terminal F _Q of the fault indication circuit FC is connected to a digital signal or DSP circuit (not shown) which is also part of the telecommunication line circuit.

The FC fault circuit in.

40-

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MOD. 71 - 3,000 EX. - 03-84

includes an NPN transistor whose base electrode is connected

to the DET input terminal via a resistor R ^ and whose

emitter electrode is connected to the terminal LT2, the terminal of

supply V "is connected to the collector electrode of Q- via DD 7

resistance R3 and diode D1 ₎ connected in series. Another NPN transistor 0 has its base electrode connected to the

8

DET input. via a resistor R .. and its em-

is connected to the LT terminal, while the junction point of the resistor R1 and the diode D2 is connected to the collector electrode of Q via diode D, This junction point is also li

8 * 3

to the gate electrodes of an NMOS N transistor and a PMOS P transistor, the P 2 source electrode being connected to and the N _{1 4} source electrode attached to _Vqq ,

P ^ and N discharge electrodes

14 --- SS

are both connected to the

port electrode of an NMOS N transistor whose electrode

source is connected to V via a resistor R. 0 termibb 1 (5

output Ρθ is directly connected to the des.

load of transistor N

15 *

The FC fault indication circuit operates as follows. When no abnormal signal is detected by the power protection circuits of the switching circuits S of S and ^or when such protection circuits

are switched off, the voltage at the input terminals DET * and DET is not sufficiently positive, relative to the respective terminals LT and LT, to make the transis conductive

1 cu ·

and Q, which are associated with it. No current 7 8

then flows through the diodes D ^ β and, consequently, through the resistance R ^ so that the voltage ( ^V pp) applied to the gate electrode of N is more positive than the voltage (V) at its source electrode. The N transistor is in

□ O * t · ™

-4155,737

Remmerie 2-2X

so conductive, while the transistor P is blocked,

MOD. 71 ~ 3,000 EX. - 03-64

once it has the same voltage (V ^) at its source and port electrodes. As a result, the transistor is also blocked and no signal is transmitted to the output terminal θ. Alternatively, when an abnormal signal is detected by the energy protection circuits of a switching circuit S a voltage, positive over that of the terminal LT ^ (LT ^), appears at the input terminal DET ^ (DET ^) of FC, It should be noted that the voltage at the LT-terminal

than the voltage at terminal V. The transistor Q (Q) becomes /

is then conductive and a current can flow from to LT

(LT) via resistance R diode D (D) and cross-section

ctor-emitter of transistor Q_ (Q _O ). As a result, the

7th

transistor N,. blocks and the transistor P becomes conductive 14 11

so that the voltage V appears at the gate electrode of the resistor N which also becomes conductive. The N ₁ / R ₁ O circuit then generates a current which is transmitted via terminal F ^ to the DSP circuit, the latter being adapted to take the appropriate actions.

Although the principles of the present invention have been described above with reference to a specific device, it should be clearly understood that this description is made by way of example only and not as a limitation to the scope of the invention.

The deposit of the corresponding order! 1 for the above-described invention was carried out in Belgium on September 19, 1983 under No. 2/60208 (Patent 897772) and as European Patent was August 22, 1984 under No. 84201211.4

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-

Claims (22)

However, MOD. 7t - 3,000 EX. - 03-8 * - Electronic contact (S / S ') that allows to establish a low or high impedance between a first (S / S *) and a second (S / S') terminal, under control A Z Z 1 of a circuit (ΝΑ / NB) providing a control signal between a third (3)) ^and a fourth (S) terminal, characterized in that two auxiliary electronic contacts are provided which enable the establishment of a low or high impedance between the first and third terminals (NA) and between the second and the third terminals (NB), the impedance conditions of these two auxiliary contacts being counteracted. 2§. _ Electronic contact according to according to claim 1, characterized in that it comprises a first (S) polarized contact capable of providing a low impedance to a predetermined voltage polarity between the first (S) and the second (S) terminals, in parallel A i with a second polarized contact (S ') capable of providing a low impedance to the opposing polarity. The electronic contact according to claim 2, characterized in that the polarized contacts are identical and are connected in an anti-parallel fashion (S ^ / S ' ₂ , / S' *). _ 42. Electronic contact according to claim 2, characterized by having a bias contact type thyristor (T / ₂₎ ^with R ^reen two control terminals, which enable it to be placed respectively under the conditions of low or high impedance by the si-43Remmerie 2-2X control. 5®. The electronic contact according to claim 4, characterized in that the two control terminals are each connected to the second terminal (S) by a MOS transistor, the ports of these complementary polarity transistors being interconnected with the fourth terminal (S) while the entrance of a tran_ 4 (N) and the discharge of the other (E) are interconnected with the second terminal. MOD. 71 - 3,000 EX. - 03-34 An electronic device (S / S) associated with the electronic contact according to the preceding claims, and forming part of a circuit which also includes an energy source and a load, said device including means for limiting the dissipation of energy at that point, characterized in that said energy limiting means (RJ R, R, R, R) are designed in FIG. 11 13 14 6 to produce a current characteristic that is contrary to the (FIG. 13) for the device starting at the origin, (5) crosses the loading line (3) of the device and moves therefrom and thereafter (6) said load line in the direction to the tensioning axis (V) without re-crossing load line z defined by the short circuit current (1 ^) through the device and by the open circuit voltage (V) which crosses it. JL> The electronic device according to claim 6, characterized in that it comprises switching means (Qj / g) capable of establishing between the first (S / S) and the second (S / S) terminal an impedance ι z z 1 low or high, defined by said running characteristic -4,455,737 Remmerie 2-2X (I.e. against the tension. 8 ·. 7. The electronic device according to claim 7, wherein said energy limiting means (R 1, R 2, R 3, R 4) are associated with said switching means and comprises first sensor means (R 1) , coupled in series with said switching means, second sensor means (R), coupled in parallel with said switching means and regulating means (Q '), controlled by said first and second sensor means and controlling said means means of switching, so as to produce said voltage characteristic contrary to the voltage. 9 ^? . An electronic device according to claim 8, characterized in that said first (R4) ^and second (R4) sensing means are are connected in series and said regulating means includes an active device (Qp) with ^an input element coupled so as to cross said first sensor means and a portion of said second sensor means and an output element connected to said sensor means; switching ^(Q l / 3 ^{) w} 102. An electronic device according to claim 9, characterized in that the said first sensor means comprises a resistor Said second sensor means ⁰³ comprise at least two resistors (R ^, ^R p 1 in series and said regulating means includes a transistor (Q). O -4555,737 Remmerie 2-2X MOO. 71 - 3,000 EX. - 03-84 11§. An electronic device according to claim 7, 8 and any of claims 1 to 5, characterized in that said switching means are part of said electronic contact (S / S «) and said energy limiting means (R) R J Q,) are coupled to disconnection means (N, Ν ') 146. 1113 controlled by said control signal and capable of operating said energy limiting means and withdrawing them after said switching means have established said high impedance. 12. An electronic device according to claim 6, characterized in that the element (5) of the anti-stress current characteristic (FIG, 14) which crosses said loading line (3) has a first portion (1) extending for voltages (VD) which are relatively much smaller than the voltage of said open circuit (V2), to a current (I2) relatively much larger than said short circuit current (I1) ^The second portion (2) joining said first portion (1) to the feature member (6) of the feature following the ^loading line (3). 13-. The electronic device according to claims 8 and 12, further comprising second energy limiting means (D ^{9 δ} 5 ' 21 R. _and 2.) comprising third sensor means (D, η, 1Z 4 21 5 R; Q,) to detect the voltage across said device ZJ · ( ^f ) and second control means (Q), controlled by said third sensor means and controlling said switching means (Î'j / g) t in order to pro-4655,737 Remmerie 2-2X * 5 said first (1) and second (2) portions of the voltage profile being counter to the voltage. 14-. - Electronic action device? of claim 13, wherein said third sensor means (D: Q, R: Q) and the re-3000 EX. "03-84 12 21 The second wounding means (Q.) includes a first M common active device (Q) whose output element is li * T to said switching means 15§. _ Electronic electronic device * of claims 7, 13 and any of the claims 1 to 5, characterized in that said communication means such electronic contact (S / S ') and said second energy limiting means (D: f _r , 2) are coupled to the disconnection means Z1 or A Z4 (Nos. Controlled by said control signal and jacket 12 ' said second energy limiting means being turned on and off after said switching means (2 ') has established said high impedance. 16-. 5. An electronic device according to claim 7, characterized in that said switching means (2 ^ y ^) are constituted by second (Q), third (Q) and fourth (Q) active devices; 1 Z j first output terminals of the third and fourth active devices are coupled to the control terminal of the second active device, the second output terminals of the third and fourth active devices are coupled to the second active device. said second terminal (S / S), the first terminal of Z 1 -47 & 55,737 Remmerie 2- 2X . coupled to the pjrimei. output of the second active device is (S / S ¹ ) and the second active device has two 1 z second output terminals, coupled to the control terminals of the third and fourth active devices, respectively. MOD. 7t - 3,000 EX. - 03-8 « 173, of claim 16, wherein said second active device (Q ') is constituted by an FNP transistor, the first output and second output control terminals of which are the base, emitter and collector electrodes, respectively and said third (Q) and fourth (Q) active devices are each constituted by O by means of an NFN transistor whose control terminals, first and second, are respectively the base, collector and emitter electrodes. 18s. - Electronic switching contact associated with the electronic contact according to claim 1. (1) and a second (S ^) terminals on the one hand, and a third terminal (S ^) Ρ ^{θΓ on the} other, the impedance conditions being complementary for the first and second terminals, characterized in that the voltage polarity applied between the first and second terminals determines the impedance conditions. 19. An electronic contact according to claim 18, characterized in that the switching contact is constituted by two transistors of the same polarity, the first terminal ( ^S j) is coupled to the first one. -4855,737 Remmerie 2_2X the first transistor output terminal (NO) and the second control terminal (NB), the second terminal (S) is is coupled to the first output terminal of the second transistor and to the control terminal of the first and further that the third terminal (S ^) is coupled to the second output terminals of the transistors. MOD. 71 - 3,000 EX. - 03-84 209 *. The electronic contact according to claim 19, characterized in that the transistors are of the type NMOS. 21 '. The electronic switching contact according to claim 18, which allows to establish low or high impedances between a first (V, FIG 5) and a second (V) terminals on the one hand, and a third terminal (A) on the other, the impedance conditions being complementary to the first and second terminals, characterized in that the first, second and third terminals are coupled respectively to the origin, port and discharge of a MOS transistor (P), and that the polarity of the voltage applied between the first and second terminals is such that they are conductive, the second and third terminals being additionally coupled to the transmitter and the collector one the impedance between the first and third terminals is obtained, whereas when it is conductive a low impedance is obtained between the second and third terminals. bipolar transistor (T ^), such that when the latter is present. _ Controlled charge capacitor circuit, associated with the electronic contact according to the -4- 55,737 Remmerie 2_2X MOD. 71 - 3,000 EX. - 03-84 characterized in that a third series of input capacitors (C) having a plurality of input capacitors are connected to a plurality of input capacitors, at the input of a rectifier circuit. the input terminal coupled to said source, has its output terminal also connected to the input of said rectifier circuit comprising a first (D, D) and one second (D, D) elements, respectively 1 Z J 4 capable of producing either a first or a second output DC polarity, thereby allowing the output capacitors (C / C ^J ) to be charged to a first or second polarity by control means (IC), wherein the first and second the second element of the rectifying circuit are decoupled by the 1st transistors complementary MOS (P ^ N) whose gates are coupled to the third input capacitor (Oj) ^and comprises second MOS transistors (N, Pt ^res pectively complementary to the former, two complementary transistors in the first (P, N ₂ ) and the second (Ν, Γ ₂ ) element to be installed on both sides of the output capacitor (C / C '), the second transistors having its port coupled to the downloading of the first transistor of the same polarity, while the sources of both transistors (P? ₂₎ of ^a first polarity (P coupled p each have the primeirc input capacitor (cp by a diode (D ^, θ the sources of the two transistors of the second polarity (Np being each coupled to a second input capacitor (C ₂ ) by a diode (D 2, D 2, Linear circuit for telecommunications systems associated with the electronic contact of claim 1, comprising a series of impe-5055,737 Remmerie 2-2X MOD. 71 - 3,000 EX. - 03 * 34 (R; R ") on each of the two conductors and contacts 12 I (S _n S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S (SLIC) or to the line (LT J LT "), respectively or alternatively, for (TC, RC), characterized in that said contacts consist of four pairs of electronic contacts, the first (S, S) connecting the impedance line 11 1 λ the second (S, S) connected to the telephone exchange, 21 the third (S, S) connecting the line side impedances 313 to a first auxiliary circuit (TC) and the fourth (S, S) li 41 42 by turning them on the central side to a second auxiliary circuit (RC). 24§. Linear circuit according to claim 23, characterized in that the eight electronic contacts, which are always coupled, are further controlled, such that only eight combinations out of the sixteen possible are allowed in the four pairs. 25-. A linear circuit according to claim 24, characterized in that the eight closed and open combinations of four pairs of contacts are defined by the eight binary codes 1111, 1100, 0100, 0110, 0101, 1001; 0001 and 0011, with the first, second, third and fourth digits of the left to correspond, respectively. 12 and fourth ^{numbers and 05} digits 0 and 1 indicating the closing and opening of the pair of contacts respectively, the first (S 11 / ), second ( ^s 2j / ₂₂ ), third ^ ^S 31/32 -5155,737 Remmerie 2-2X 26-. - A circuit comprising plurality of electronic contacts adapted to be operated according to different combinations by binary control signals characterized by the existence of a decoder (DEC) inserted in the circuit and suitable to be controlled by at least a part of the signals ( ^^ iC / g) T ^o to provide output binary signals to a set of gates (GH |.) which also receive directly (GD) the bi nary control signals, a selection signal (iC ^) which allows to control the doors , in such a way as to allow and inhibit, respectively, the control flow and the output signals or vice versa. MOO. 71 - 3,000 EX, - 03-84 27-. The linear circuit according to claim 25 and 26, characterized in that the input binary signals (ABC) DOO, 001, 010, 011, 100, 101, 110 and 111 which control (iC ^^ g) (DEC) correspond respectively to the eight binary output combinations (E, F, G, II), binary signals 1111, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 provided by the decoder. 28s. Linear circuit according to claim 27, characterized in that the binary output codes of the decoder are obtained as a function of the input binary codes by five logic circuits respectively defined by the Boolean equations, Έ = B (+ + C) F = Ã + F G = ÃY + BC ϊϊ = A + Y Y == B + C respectively, in which Y is an intermediate signal and wherein A, -5255,737 Remmerie 2_2X B, and Y are the complements of A, B and Y, respectively. 299. A circuit according to claim 26, characterized in that the arrangement of the ports (GI / GD) provides an output signal controlling two clock ports, opposing such that either one or both. transmits either a clock signal or its complement. MOO. 71 - 3,000 EX. - 03-8 * Circuit according to claim 29, characterized in that the clock signal and its complement are produced by a clock oscillator element of the same integrated circuit as the set of doors, the decoder, the electronic contacts and their control circuits. 319. _ Linear circuit for system associated with the contact in accordance with the Claim 23, which comprises a series of impedances (R, R ") on each of the two linear conductors (LT, LT) 1 Z 1 z and contacts (3 ^, S ^, θ ^ ₂ 2 ^{ca <* The} side of these two impedances enabling to selectively connect their terminals towards the exchange (SIIC) or the line (LT J LT), respectively, characterized in that es1 2 (S, S) connecting the line to the impedances and the second (S, S) connecting these to the telephone exchange (SLIC) and only said pair of electronic contacts (S , S) is provided with energy limiting means 11 (R..J R <Q-) according to claim 8. 1113146 329. _ Linear circuit for system -5355,737 Remmerie 2_ 2X MOD. 71 - 3,000 EX. - 03-84 according to claim 3, characterized in that said first pair of electronic contacts (3, S) is also provided with second energy limiting means (Q ,, Q) according to 21 '5 12 4 Claim 13. A linear circuit for a telecommunications system according to any one of claims 31 or 32, characterized in that it also includes detection means (FC) coupled to said first pair of electronic contacts (S, S) and adapted to provide a signal indicative that the voltage across at least one of said electronic contacts exceeds a predetermined value. 34-. - Linear circuit for systems according to claims 2 and 33, characterized in that said detection means (FC) includes a detection circuit & / $ ^{'D 22/23>} PJP ^ 14/15 ^ ^{with 1X111} first input element (R ^ _R, Q?) coupled with said first polarized contact (S) of the first electronic contact (S) of said first pair (S, S), a second coupled input element to said first polarized contact of the second contact (S) of said first pair and an element of 1 Z the output ^circuit (Qy / g, ^D 22/23 ' ^R 17 ^ ¹⁾ (p. ₎ also included in said means of 11 14/15 lo and is adapted to provide at an output terminal (Fq) said signal indicative that is a function of the voltage across at least one of said polarized (S) contacts, 35-. - Linear circuit for system -5455.737 Remmerie 2-2X telecommunications apparatus according to claim 34, characterized in that MOD. 71 - 3,000 EX. - Ο3-β * (R, Qy) ^and second (R, Q) input elements of said delta circuit tection 2y / _g> 22/23 ^{D 'R} ii> ^ 4/15 ^consist ^ each of them by the base and meter electrodes of an NPN transistor (Q; Q) respectively coupled between the reactants (S), said output member is constituted by the collector electrodes of said NPN transistors, to which a first DC power terminator (V) is connected via a first (R), in series with the respective diodes (D j 1/2 Z D ^^) of said indicator circuit (P ^ w ^ 14/15 * ^R g) ⁿ * "clude one PMOS transistor (P ^) and a first NMOS transistor (N) whose gate electrodes are both connected to the junction point of said first resistor (R ^) ^{θ to} said diode (D ^^, ^ 23 ^ ^{'s cu} jth discharge electrodes are interconnected and whose input electrodes are attached respeetivamente to said first terminal (V ) and to a second DC power terminal (V) and the said common discharge electrodes of said FMOS and first NMOS transistors are connected to an electrode of of a second NMOS transistor (N) whose electrode of 15 input is connected to said second DC supply terminal (VGG) ^{111 713} via second resistor ^(R g) θ cu. The discharge electrode is connected to said output terminal ( ^F q). 362. A linear circuit for a telecommunications system according to any one of claims 31 to 35, characterized in that it includes a third and a fourth 55,737 Remmerie 2-2X to pairs of electronic contacts, additional connecting the third (S, S) the impedances (R $ R ") on the line side 31 3 ζ ι z (LT: LT) to a first auxiliary circuit (TC) and the fourth (S ^ p S) linking them, on the side of the telephone exchange (SLIC), to a second auxiliary circuit (RC).