DD228402A5 - ELECTRONIC CONTACTS AND ASSOCIATED COMPONENTS - Google Patents

Abstract

The aim and object of the invention is to provide a more advantageous type of electronic contact, which can also be controlled by the polarity of the charge of a capacitance, and in particular a Thyristorausfuehrungsart working with high breakdown voltages. The object is achieved in that two electronic reserve contacts are provided, which make it possible to form a low and a high impedance between the first and the third terminals and between the second and the third terminals, the impedance states of these two reserve contacts are opposite. Fig. 1

Description

Berlin, 21.2.1985 64 374/13

Electronic contacts and related components Field of application of the invention

The invention relates to electronic contacts which can form a low or high impedance between a first and a second terminal in accordance with the control of a circuit which provides a control signal between a third and a fourth terminal.

Characteristic of the known technical solutions

Such electronic contacts are used, for example, in 8E-PS 896,388, which relates in part to a capacitively controlled charge circuit and which makes it possible to positively or negatively charge a capacitor which, depending on the sign of this charge, opens an electronic contact or which is formed by two DMOS transistors arranged in opposite series in such a manner that their drain electrodes respectively form the two terminals of the electronic contact, while their source electrodes are respectively connected to the same terminal of the capacitance and their gate electrodes are both connected to the other terminal of the capacitor, which in the latter case is formed by the parasitic capacitance between these paired terminals. In this way, relatively high voltages can be withstood by the use of transistors * by forming an electronic contact which can be inserted into a circuit in which one or the other polarity at the contact terminals is formed.

9 ζ ECQ

can occur. In fact, if the polarity of the charge on the control capacitance for the contact is such that it does not offer a low resistance path, i. that is, the two transistors are off, then the parasitic diodes which appear for this transistor state between the source and drain electrodes are consequently also connected in series cross-connection which maintains a high impedance, which polarity may also be applied by the circuit the contact is used. The transistors in the above-mentioned patent have inverse characteristics, i. that is, they can conduct current in one direction or the other, but inhibit voltage polarity.

From the PCT application VVO 82/03733 an electronic sowing element is known in which the means for power limiting are intended to generate a current-voltage or I / V characteristic which, starting from the zero point, up to a maximum current rises at a predetermined voltage, remains at that current until a maximum voltage is reached, and then suddenly drops to a current that is nearly zero. At the last break point of this curve, the power dissipation of the device reaches a maximum (maximum current and voltage), and under some circumstances this may be inadmissible, for example, when the device is to be integrated into an electronic chip.

Object of the invention

The aim of the invention is to enable the use of such electronic contacts while simultaneously

a complication of the control circuit should be avoided. Another 2SeI is to provide an electronic device with a reduced power dissipation.

Explanation of the essence of the invention

The object of the present invention is to provide a more advantageous type of electronic contact, which can also be controlled by the polarity of the charge of a capacitor, and in particular a Thyristorausführungsart which operates at high breakdown voltages, for example 300 V, but the current only in one direction while voltages of one polarity or the other can be blocked.

In accordance with a first feature of the invention, the above-defined electronic contact is characterized in that two reserve electronic contacts are provided and the provision of a low or high impedance between the first and third terminals and between the second and third terminals the impedance conditions of these two reserve contacts are opposite.

According to another characteristic of the electronic contact is characterized in that it comprises a first biassed contact which is adapted to provide a low impedance at a predetermined voltage polarity between the first and second terminals, in parallel with a second biassed contact, of the Forming a low impedance for the opposite polarity

suitable is.

The preloaded contacts are identical and connected in anti-parallel. The electronic contact is characterized by a biassed contact of the Thyristorart containing two control terminals "that allow it to turn on the low or high Iropedanzzustand by the control signal. The two control terminals are respectively connected to the second terminal through a MOS transistor, the gates of these transistors of complementary polarity being connected to the fourth terminal, while the source of one transistor and the drain of the other transistor are connected to the second Connection are connected.

Such an arrangement offers the advantage that the two electronic contacts of the thyristor type can be connected at the top to the bottom like a triac and controlled by means of the same control circuit, and in particular that according to the above-mentioned patent uses a positive or negative charge for a capacitor to close or open the electronic contact. Indeed, it is by means of the electronic reserve contacts in accordance with the polarity of the voltage gelegtjist to the terminals of the electronic contact, which may be automatically by the two biassed contacts connected in parallel counter circuit possible a connection between a terminal aer control capacity and the To achieve connection of the main electronic contact with a given polarity. In this way, always the same capacitance charging circuit should be used, d, h, the voltage

doubler-to-AC converter described in the above-mentioned patent for closing or opening that of the two polarized contacts which is effectively inserted in a load current circuit and depends on the polarity of the voltage appearing at the terminals of these contacts, which are connected in parallel countercurrent connection.

On the other hand, the advantage of the electronic thyristor contacts is that they can be controlled in the manner shown, and with respect to the DMOS transistors connected in series opposition, as in the above-mentioned Belgian patent instead of the proposed top against bottom connection, the Advantage in that the resistance for the closed state of the contact is significantly lower, d, h, below 10 ohms instead of 25 + 25 = 50 ohms. In addition, the required area in an integrated circuit is reduced to one quarter for the thyristor solution.

The present invention also relates to an electronic component which forms part of a circuit and which also contains a current source and a load. The component comprises means for limiting the power loss. This component is created by generating a current-voltage characteristic for the component which, starting from the zero point, crosses the load characteristic of the component and then follows said load characteristic to the voltage axis without crossing the load characteristic determined by the short circuit current through the component and its open circuit voltage.

The minimum of the power that is lost in the device is at its operating point, i. H. at the point where the I / V characteristic crosses the load characteristic. Unwanted, abnormal signals have various causes, such as a lightning strike in the voice path or a main power supply, that are incidentally connected to the device, and could affect the characteristics of the circuit. In fact, such signals are added to the normal signals generated by the power source so that the location of the load characteristic is modified. The operating point then moves along the portion of the I / V characteristic that crosses the cte load characteristic. In the event that these unwanted, abnormal signals become very large, the load characteristic could be shifted in such a manner that the operating point reaches the upper end of that part of the I / V characteristic. This operating point then becomes unstable and moves to higher voltages.

Since the I / V characteristic then follows the load characteristic, the power consumed in the component is reduced to a minimum during this transition of the operating point af. If the undesired abnormal signals do not occur, the load characteristic returns to the initially mentioned position due to the fact that the part of the I / V characteristic following the load characteristic does not cross the latter; the working point moves from the higher voltages to its original position. This would not be the same if there was an intersection between the part of the I / V characteristic and the load characteristic. Such

Intersection would actually produce an operating point remote from the one mentioned above and affect the normal functioning of the electronic component.

Another object of the present invention is to allow at relatively low voltages those currents which are substantially greater than the short circuit current and flow through the electronic device while maintaining the above-mentioned advantages for higher voltages.

This object is achieved by the fact that the part of said current-voltage characteristic crossing said load characteristic has a first range extending for such voltages substantially less than said open circuit voltage with respect to a current that is significant is greater than said short-circuit current, and a second area connecting the first area with the part of the characteristic which follows the load line.

The operating point of the device can therefore move along the first range of the I / V characteristic so that the current in this device can reach said relatively large value at low voltages without activating the power limiting device. At higher voltages, the device operates as described above.

Another object of the present invention is to provide such electronic contacts in telecommunications systems, and in particular in subscriber telephone circuits.

These are functions that were previously generally met by relay contacts, even in main offices where the remainder of the system is electronically constructed.

Therefore, the invention also relates to a telecommunications subscriber circuit consisting of a series impedance in each of the two lines and contacts on each side of these two impedances to allow for selective connection of their two terminals to the office or line or alternatively to the backup circuits.

Such a system has been found, for example, in the article published on pages 315 to 324 of the IEEE Journal of Solid State Cireuits, Duni 1983, and more particularly on page 317. It can be seen there that these two series resistors feed a telephone subscriber line serve and also to measure the voltage applied to these resistors, for the monitoring and control operations. On the official side of these resistors can be fed by means of the corresponding contacts a ringing current, and by measuring the voltages across the resistors can thus monitor the call operation.

On the other hand, on the side of these resistors, the contacts on the subscriber line side allow access to the buses to perform tests, either internally (for

Office and through the series resistors) or externally to the subscriber line. So far, these contacts have generally been realized by means of three relay switching contacts, which automatically show that, when the working part of the contact is closed, which is connected in parallel with one of the control circuits, then the rest part connected to one of the resistors in Row is switched on, automatically opened and vice versa.

According to another feature of the invention, these contacts are formed by four pairs of electronic contacts, the first being the line with the impedances, the second with the office, the third the line side impedances with a fourth reserve circuit and the fourth pair on the office side connects to a second reserve circuit.

According to still another feature of the invention, only the first pair of electronic contacts are equipped with a power limiting device such as described above.

In addition, according to an additional feature of the invention, the eight electronic contacts, which always operate in pairs, are controlled in such a way that only eight combinations among the sixteen possible ones are allowed for the four pairs.

According to another additional feature of the invention, the control device of the four electronic contact pairs' includes a decoder, suitably three binary ones

In addition, a binary selection circuit is provided to enable or disable the decoder outputs, and in this latter case the connections to the four binary input signals are allowed, in which case the connections to the four binary input signals are allowed, to control the four electronic contact pairs. In this way not only is it possible to realize, in particular in the form of a single integrated circuit of eight series electronic contacts which withstand relatively high voltages and operate in pairs, but also to control the operation of these electronic contacts either by means of a code only contains three binary elements, or directly by a signal corresponding to these electronic contact pairs. "This versatility can still be increased by incorporation into such an electronic clock circuit, which allows the operation of the control circuits of the electronic K.ontakte in the manner described in the above-mentioned patent is described; Consequently, it is thus avoided that one relies on a separate clock circuit.

Working Example

Qb invention will be explained in more detail below with reference to the accompanying drawings, in which:

Figure _# 1: the circuit of an electronic contact in accordance with the invention;

Fig. 2: the electronic contact control circuit of the above mentioned patent modified according to the invention;

Fig. 3: the part of a telephone line circuit incorporating eight electronic contacts according to the invention;

Fig. 4 shows the entirety of the circuits enabling control of the eight electronic contacts, shown alone in the form of a single block in Fig. 3;

Fig. 5: an input protection circuit, shown as a block in Fig. 4;

Fig. 6: an electronic gate, shown as a block in Fig. 4;

Fig. 7 is a two-electron electronic clock controlled by clock pulses and shown as a block in Fig. 4;

Fig. 8: the circuit which generates the clock pulses and is shown as a block in Fig. 4;

Fig. 9: a first logic circuit used to implement the decoder and shown as a block in Fig. 4; and

Fig. 10: a second logic circuit used in this decoder;

FIG. 11 is another embodiment of the circuit of an electronic contact of Fig, 1, the power protection circuits according to the invention includes;

Figs. 12 and 13 are current-voltage characteristics of the power evaluation circuits of Fig. 11; the characteristics are not drawn to scale;

FIG. 14 shows current-voltage characteristics of the electronic contact illustrated in FIG. 11; FIG. the characteristics are not drawn to scale;

FIG. 15 shows an error indication circuit FC, which is connected to the power protection circuits shown in FIG. 11 and also in FIG.

The electronic contact resists relatively high voltages and, as shown in Figure 1, may be part of an array of eight identical electronic contacts (Figure 3) arranged as four pairs of contacts; the two contacts of a couple are always open or closed at the same time. This combination can be used in a telephone line circuit and is partially described in the BE-PS 896 468. With the exception of the eight electronic contacts corresponding to those of Fig. 1 and the eight circuits for such contacts appearing in Fig. 2, which correspond substantially to the capacitively controlled charging circuit of BE-PS 896,383, Fig. 4 illustrates Decoder circuit, which can be activated by either three or four binary signals. In the first case, the eight possible combinations of the three binary signals are decoded to four output terminals or used to control the four pairs of electronic contacts. In the second case, this time the control signal allows the

four binary input signals are applied to the four electronic ports, while the same signal prohibits the decoder operation. In addition, the circuit of Fig. 4 includes at the decoder output a transducer which is intended to generate suitable signals for the capacitive charging circuit of Fig. 2 by means of an oscillator which generates complementary clock pulses.

The five parts mentioned above, d. h _# the electronic contacts, the control circuit, the decoder, the converter and the clock oscillator may be combined in the same integrated circuit by combining a DCMOS low voltage logic and TRIMOS high voltage contacts. In the manufacturing technology used, in particular, the method described in BE-PS 897 139 can be used. The whole then provides four pairs of electronic contacts which block voltages of 300 V in both directions and have a dynamic resistance of 10 ohms when conducting, the two terminals of each electronic contact being freely movable with respect to the control circuit. The four contact pairs can be operated in accordance with the sixteen possible combinations by means of four binary signals or in accordance with eight predetermined states by means of three binary signals.

From Fig. 1 shows that the electronic contact contains two identical parts S and S *, in such a way that only the first part is shown in detail. Depending on the control signal, the circuit S can either a low

or have a high impedance between their two output terminals S ₁ and S ₂ , to which the corresponding terminals S 'and S' of the part S 'are connected in this order *. The two circuits are therefore connected in anti-parallel. Thus, they can be operated under three different conditions: both S and S ^f provide high impedance at their terminals, S provides high impedance for the one voltage polarity at the contact terminals, while S "can also provide this low impedance but for the other polarity.

The circuit S is of the TRIMOS type which is substantially connected to a transistor T_ of the NPN type so as to form a thyristor between the terminals S ₁ and S ₂ . The fabrication of such a device generally results in the occurrence of a parasitic transistor T_ of the PNP type connected in parallel with the first two. This thyristor combination is controlled by the DMOS-type transistor N connected to the PMOS-type transistor P, and their gate electrodes connected to each other at the same terminal S provide a capacitance C to the terminal S _{2 of} the contact. to which the drain electrode of the transistor P and the source electrode of the transistor N are connected.

In this way, the transistor N is turned on, provided that the capacitance C is positively charged at its terminal, which is connected to the two gate electrodes of the transistors P and N with respect to the terminal S ₂ , and that other-

on the other hand, the voltage at terminal S _{1 is} more positive than that at terminal S ₂ . Thus, a current from the terminal S ₁ to the terminal S ₂ through the transistor T ₁ due to the short circuit of the transistor N by its drain-source path, the base of the transistor T ₁ , to which the drain electrode is connected, and the emitter of the transistor T-, which is connected to the terminal S ₁ , flow. The effect of this conductivity of the transistor T ₁ is to pump into the base of the transistor T ₂ current which is directly connected to the collector of the transistor T ₁ in such a way that the transistor T ", which is of the NPN type, starts. To pump current into the base of the transistor T, which is connected directly to the collector of the transistor T ", whose emitter is in turn connected directly to the terminal S ₂ . In this way, the two transistors T ₁ and T ₂ , which are arranged in a saturation mode, bring about a low impedance due to the cumulative effect between the terminals S ₁ and S ₂ . The transistor T, which is also like the transistor T _{1 of} the PNP type, is connected to the transistor T ₁ , that in each case the base and emitter terminals are connected together, while the collector of the transistor T_ at the potential of the terminal S ^, lies. The

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Transistor T_ also becomes conductive, but, as indicated, this affects a parasitic element without affecting the main mode of operation of the circuit.

The biased contact S, which produces a low resistance between the terminals S ₁ and S ₂ , can be returned to the capacitor C in its high impedance state by means of a negative charge. This negative po-

With respect to the gate electrodes of the transistors P and N, the connection of the terminal S ₂ results in the conduction of the transistor P which is of the PMOS type. While in the NMOS type transistor N, the drain electrode is connected to the base of the transistor T, the source electrode of the transistor P is connected to the collector of the transistor T ₁ in such a manner that the transistor P is output from the collector of the transistor T ₁ draws current so that the base current of transistor T _{2 is} insufficient to maintain the conductivity of this NPN transistor, resulting in a cumulative effect that it blocks and transistors T and T and thyristor T ₁ "become nonconductive , From Fig. It is also noted that the P and N substrates are connected to the N-drain and P-source, respectively.

The other contact S ¹ , which is shown in FIG. 1 solely in the form of a block, operates exactly in the manner described, but this time in accordance with the control of a positive or negative charge on the capacitor C and in particular on its connection S. with reference to its terminal S * ₂ . But these operations of a half contact S 'are now caused when the polarity of the circuit in which the switches are installed in antiparallel, at terminal S ^ is positive with respect to terminal S * ₂ . It should be noted that the realization of the contacts S / S "in a single integrated circuit requires a connection between the common base terminals of the transistors T ₁ and T ₃ for the two contacts S and S '.

As already stated in the BE-PS 895 388, the

Capacities such as C and C * may be formed by parasitic capacitances. Particularly, those appear at the gates of the transistors P and N in the case dsr of capacitance C. Both capacitances C and C * may have a desired polarity via the control circuit shown in FIG and, more particularly, according to an embodiment already described in the last mentioned Belgian patent.

In fact, the source electrodes of the transistors NA and NB shown in Fig. 1, both of the NMOS type, are directly connected to the terminal S_, while the drain electrodes of the transistors NA and NB are connected in this order to the terminals S * and S " On the other hand, the Gaieslektrode of the transistor NA is connected to the terminal S ₂ , while that of the transistor NB is connected to the terminal S ₂ . Such a circuit arrangement results in that when the potential of the terminal S _{1 is,} for example, higher than that of the terminal S ", the potential of the terminal S may not be outside this range, and the transistors NB and NA are turned on and off; this actually means that the terminal S, practically (0.7 volts) is connected to the terminal S ₂ , and by referring to Fig. 2 it can be seen that it is in fact the capacitance C which is effectively between the terminals S and S, which is connected to the charging device shown in Fig. 2. The parasitic diodes between the source and drain of the transistors NA and NB, ie, the diodes DA and DB shown in, for example, FIG. 1, are biased in such a manner as to play an analogous role through the control terminal S even the potential at the connection

S ₂ »if the latter is less positive than the one at S *.

In view of the symmetry of the circuit formed by the transistors NA and NB, when the potential of the terminal S _{2 is} higher than that of the terminal S, the states are naturally reversed, and the conductivity of the transistor NA and the diode DA following, the terminal S, is now practically connected to the terminal S ' ₂ in such a way that under these circumstances it is the capacitance C which is effectively connected to the output terminals S and S of the control circuit of Fig. 2.

In this way, a single control circuit can close or open half of the electronic contact S or S ¹ , depending on the polarity of the applied voltage between the terminals S 1 / S '' on the one hand and the terminals S ₂ / S * on the other hand ,

As already indicated, the circuit of Fig. 2 is described substantially in the BE-PS 896 388 and particularly with reference to Fig. 6 of this patent, which is very similar to Fig. 2. »The latter forms an AC-to-DC converter in the mold a full-wave voltage doubling circuit and operates in push-pull by clock pulses of complementary polarity. The polarity control of the circuit in Fig. 2 is effected by the signal DC applied to the series capacitance C, while the complementary clock signals UL and CL are constantly applied to the two other series input capacitances C and C _0, respectively. In the same way as

for the output there is the capacitance C / C (Figure 1) between the terminals S. and S ₂ / S ' ₂ , the three input capacitances formed by discrete physical elements are not necessary. The first voltage doubling rectifier circuit is essentially constituted by a series capacitance C., followed by a series connected diode D, a PMOS type transistor P ₁ , to achieve a shunt capacitance C / C between the terminals S and S i. The parallel-connected diode of this voltage doubler, the diode D ₂ , as indicated, connected between the connection of the capacitor C ₁ and the diode D ₁ on the one hand and between the connection of the capacitance C and the gate electrode of the transistor P ₁ on the other. When the control potential DC applied to the series capacitance C ₃ corresponds to the clock pulse CL applied to the series capacitance C ₂ , it is the charging circuit described which provides the guarantee of effective charging of the capacitance C / C in such a manner in that the potential at terminal S is more positive than that at terminal S ₃ .

Conversely, if the control signal D ~ C applied to the series capacitance C corresponds to the clock pulses CC constantly applied to the series capacitance C ₁ , the output capacitance C / C at the terminal S is now charged more negatively than at the terminal S, where the elements of this voltage doubler actually receive a negative charge. The parallel output capacitance consists of the elements C-, D, N ₁ and D corresponding to the elements C ₁ , DP ₁ and D-, respectively, as shown in Fig. 2; the transistor N ₁ is of the NMOS type.

As in the Belgian patent 896388, the charge circuit is completed by utilizing the conductivity of the transistor P. through the transistor N "of the NMOS type having its drain electrode connected to the terminal S, and its source electrode connected to the capacitor C ₂ by means of the series connected diode D is connected, and the gate electrode is connected to the terminal S. This connection thus permits _t the return circuit for the positive charge by disconnecting a path between the ^w Erd "-AusgangsanschluS S ₃ and the input" ground "is formed by the right-hand electrode of series capacitance C ₂ to complete -connection." In Similarly, with a negative charge on the output capacitance between terminals S and S, the return path this time is by means of the PMOS-type transistor P _{2 connected} in series with the diode D 1 _, these two elements correspond to the transistor N ₂ respectively of the diode D, as indicated by the circuit which is virtually identical to that of Fig. 6 of the BE * -PS 896388, except for the diodes D and D "located on the source side of the transistors P ^ instead of on the drain side, as in the known patent Another embodiment of this circuit is shown in Fig. 4 of the known patent, in which the diodes D and D are already a n are the source sides of the transistors P and N, but in this circuit the gate electrodes of the transistors P ₂ and N ₂ are connected together in another circuit; they are not connected to the drain electrodes of the transistors P ₁ and N ₂ (S ₄ ) in such a way that the diodes D_ and D- in this case at the

D D

Drain side of the transistors N ₂ and P ₂ are located. on the other hand

are the four diodes D ". D_, D_ and D- in the version of Fig. 2 are located wholly on the source side of the transistors to which they are connected in such a way as to be entirely on the side of the three input capacitances with the diodes D ₂ , D and D _Q. ^c i / 2/3 are arranged. This latter diode D _ directly connects the capacitances CL and C, in the same way as in the known patent, and the Zener diodes D_, D _Q and D are in parallel with the output terminals S 1, and the source / drain path of the transistors N "and P ₂ are also connected in the same way as before.

The integrated circuit IC, which, as shown in Fig. 1, can accommodate both eight electronic contacts, and, as shown in Fig. 2, eight control circuits, appears in Fig. 3 in the form of a block, which is a part of the Fig. 1 corresponds to the BE-PS 896 468, which relates to a subscriber circuit for an electronic telephone system. As shown in Fig. 3, a subscriber line (not shown) may be connected to the terminals LT. and LT _{2 be} limited, preferably by an overvoltage protection circuit of the type such. B. that which is the aim of BE-PS 896 468. By means of the first electronic contact S ^ ₁ , which is a part of the integrated circuit IC, the terminal LT. with the series resistance R ₁ and then by means of a second, series-connected electronic contact, d, h. S _{21 are} connected to the SLIC circuit containing other elements of the electronic subscriber circuit. The circuit between the second input terminal LT ₂ and the SLIC circuit is exactly

the same, that is to ^say , the elements S ^ ₂ , ^ ₂ ' ^S 22 ^{correspond to} elements S ₁₁ , ^ ₁ * S ₂₁ '. Except the series contacts, a connection of the resistors between the terminals LT. ., And the SLIC circuit, these resistors can also have four parallel contacts to the control circuit TC (contact S ₃₁ for resistor i ^ and contact S ₃₂ for resistor R ₂ ) on the subscriber side CT Jz ₂ ) on the one hand and to the call circuit RC (S ₄₁ for "r., and S ₂ for _R2) on the exchange side (SLIC) on the other hand are connected. the connections (not shown) run from the terminals of the Zuf ührungsvviderstände R. _{/ 2} to the circuit SLIC, the potentials of the monitored at these resistors.

The operation of the eight contacts is controlled by the circuit SLIC through four conductors connected to the terminals ^ <\ / 2./-t/A , whereby the contacts of a pair, for example ^ 11/12, are controlled ^{by the} same signals, so that the two wires of the connection are switched simultaneously. However, the fourth conductor arriving at IC is shown, since this control can be effected according to a control mode in which only three binary signals are used in sub- 'rupted lines, a type selection signal is applied to the terminal IC _5, This determines when three or four binary signals are used to control the four contact pairs ^S ll / 12V ^S 21/22 * ^S 31/32 ^{and S} 41/42 ^2U .

This versatility of the integrated circuit is due to the fact that the position of these four pairs of contacts directly on each side of the resistors R 1 and R ₂ allows corresponding control with a number of connection states

secure that does not go beyond eight. Thus, when the four pairs of contacts of the circuit IC are used for any application, subscriber circuit or otherwise, between 9 and 16 possible states are required for the combination of these four pairs in their open or closed states, each of the four binary signals at the terminals ¹ C ₁ ^ ₂ , _ ,. can directly control the state of a contact pair. On the other hand, one can, in particular, in the case of the telecommunication line circuit satisfied with a maximum of eight conditions and the selection signal at terminal IC will indicate this time that only the three binary signals at terminals ^IC j / _2/3 must be taken ^into consideration and the eight possible combinations of these signals are converted by means of a decoder DEC into four binary signals, each of which can control a pair of contacts.

This becomes apparent in the form of a block diagram in Fig. 4 which illustrates the elements used in the circuit IC of Fig. 3, except for the electronic contacts and their capacitive charge control circuits already described with reference to Figs.

In Fig. 4, each of the inputs ^IC i / ^{2/3/4/5 is coupled to} a corresponding inverter ^Iv i / ^2/3/4/5 by an identical protection circuit ^pc i / ^2/3/4 except in the case the input IC_ _# at which the connection takes place directly. The protection circuit PC. is shown in detail in Fig. 5.

The latter shows that the input terminal IC _{1 is} connected directly to the output terminal A, the binary input

code for the circuit IC is characterized by ABCD, the output terminals B, C, D correspond to the terminals in the order ^IC 2/3/4 * ^The input terminal of IC. is connected to the poles V. and V _{2 of} a DC voltage source through the diodes D ₁ ,. or D _ connected. These limit the voltage at the terminals IC./A, between which the potentials V ₁ and V_ are present. This last potential, for example 0 volts, is more negative than the potential V., for example 15 volts. On the other hand, the source electrode of the transistor P which is ₃₁ of the PMOS type, with the potential V. _t whose drain electrode is connected to the output terminal A and its gate electrode connected to the potential V "in such a manner connected that it is continuously conductive.

The NPN-type transistor T shown in broken lines has its collector connected to the input terminal IC. and with its emitter on the potential V ₂ . This transistor T may be used to generate a binary control signal located at the input terminal IC ₁ . If the base of the transistor is at the potential V ₁ , it is conductive and allows a passage of current from the potential V. to the potential V_ through the series-connected transistors P, and T. The impedance of the latter transistor £ t lower than that of the transistor P ,, the terminal A is at the potential V ₂ . On the other hand, if the base of the transistor T. is at the potential V ₂ , so that the transistor T is turned off, the terminal A is at the potential V ₁ , which is passed through the transistor P.

In Fig. 4 it is shown that the four potentials (ABCD) to the

Outputs of the protective circuits ^p Ct / 2 / - * / 4 ^to ° ^ ^θ terminals, such as G ", a gate GD via inverter, B. B. ^IV ₄ " are placed in such a way that a complementary binary code Ä "B * C D at the inputs of these gates (the gates are identical to GD, which is provided for the signals at terminals A, E3 and C ) with respect to the binary code ABCD appearing at the outputs of the protective circuits ^p Ci / 2 / -? / 4. On the other hand, three of these binary signals A "BC are applied to the decoder DEC, the same as the two signals A and B, which are complementary to the signals A" and B, and through the inverters IV ₅ and IV ₇ connected in series with the inverters IV. or IV ₂ are formed.

Before explaining how the decoder DEC can advantageously convert the eight combinations of the three binary signals ABC into the individual combinations of the four binary signals at its outputs E ^- F Ο " H , the description of the other elements of FIG 4, beginning with the above TorGD, whose output is connected to that of an identical gate GH, to which the Hf output of the decoder DEC is fed, three identical gates (not shown) are used, which operate in the same way connected to the outputs EFG.

The gates, for example GD and GH, are controlled by a terminal IC_ which determines the operation of the circuit IC, with or without decoding by the decoder DEC. The binary signal at terminal IC_ is applied to all gates, for example GD / GH as well as the complementary binary signal formed by inverter IV.

Fig. 6 shows the circuit of a transfer gate such as GD and GH connecting the input terminal D or FT to the output terminal DH through the source-drain path of the transistors N and P. connected in anti-parallel and the NMOS and PMOS types, respectively belong. Their gate electrodes are connected to IV and IC for the gate GD and vice versa for the gate GH in such a manner that one of these gates is conductive and the other is blocked, depending on the drive signal of the terminal IC _n ., allowing for the terminals, for example DH, either the signal D and a part of a binary 4-element code, each of which identifies a Kon.taktpaar, for example ^S ll / 12 (^ ^3- S * ^) * or the signal H. * select one of the four binary elements decoded by decoder DEC from the three binary elements ^ .BC.

As indicated in Fig. 4, the signal on the terminal, for example DH, must still be synchronized by the gate, for example GC, with the clock pulses supplied by the connected oscillator CO. Similarly, the complementary clock signals CL and CL ~ are applied to the three input capacitances Ci / jw of the AC-DC balanced converter (FIG. 2) which serves to positively or negatively charge the capacitances C / C which are the biased, antiparallel control interconnected electronic contacts S / S ¹ (Fig. 1).

Fig. 7 shows the circuit of a clock gate. The binary signal at the terminal, for example DH, which determines the contact corresponding to the open or closed state dss,

is now applied to the control gates GCA and GCB, which are identical to those of Fig. 6, but to the inputs to which the complementary clock pulses CL and CTT are applied, which are used by the oscillator CO. The gates GCA and GCB are complementarily controlled by the signal DH and its compliment generated by the inverter IV such that the output DC of the gate GC is either a CL pulse or a complementary CTT pulse according to the value of the Binary signal at the terminal DH is.

Fig. 8 shows the clock oscillator CO, the Senior Citizen the three inverters "^ io / n / 12 ^ENTN, the * ⁿ a loop cascade-connected and includes the resistors connected in series R_ and R on each side of the inverter IV.. Monitoring output of the inverter IV ₁₂ drives a second series of three cascaded inverters IV,.,., the latter providing the clock pulses CL and the inverter IV ₁₄ providing the complementary pulses CL ". The oscillator CO is also driven by the voltages Vp (not shown) and V, the latter being connected to the inputs of the inverters ^{11/12/11 U, and} the capacitances C ^1, C ² . These may be 5 pF and the resistors 20 kJl. to generate vibrations with a frequency of the order of 1.2 MHz «

As indicated by the multiple arrows in Figure 4, the oscillator CO drives the four gates, for example GC, whose output port controls two charge circuits, for example those of Figure 2, to control a pair of contacts, such as that of Figure 1. The latter link, which is executed by the inverter IV _Q , the signal D ~ c

is of the type that the three signals at the capacitances' C ₁ ._. of Fig. 2 arrive through the output impedance of an inverter.

Finally, the decoder DEC of Fig. 4 will also be described by reference to Figs. 9 and 10, which illustrate the type of logic circuits which may be used to their advantage.

Finally, first the eight states of the telephone subscriber circuit are to be defined, which can be characterized by a combination of the input signals ABC the decoder DEC. These eight states are determined by the following truth table:

A  1/ '12 > Y ΓΠ | ^S 21/22 ^S 31/32 ^S 41/42 0 B C 1 1 f " G H interrupted 0 0 0 0 1 1 J * 1 Rufprüfung 0 0 1 0 0 1 0 0 Restraint 0 1 0 0 0 1 0 0 call 1 1 1 1 0 J * 1 0 audit 1 0 0 0 1 1 0 1 internal audit 1 0 1 0 0 0 0 1 monitoring 1 1 0 0 0 O 0 1 by circuit 1 1 0 J * 1

The table contains three columns corresponding to the input signals ABC, a fourth column for an intermediate signal Y, the usefulness of which will become visible later, and four other columns.

th FT "f" θ "FT , which identify the signals at the output of the decoder DEC, each of these latter columns, as indicated, corresponding to the state of a contact pair, for example E" for

The complement bar over the comparison values determines these contacts according to the complementary form of E: F GH in such a way that the display 0 indicates a closed contact, whereas a 1 indicates an open contact. The eight states for the subscriber circuit appear in the following lines in increasing order for the binary code from 000 to 111 for cfe signals ABC; this latter code corresponds to the connection of the subscriber circuit in Fig. 3, ie, the series-connected contacts S ₁₁ ^ ₁₂ and S ₂₁ , ₂ 2 ^sinci closed, and the parallel-connected contacts S ₃₁ ,, ₂ ^unc '^ ^{41/42 s :} * - ^nc * open · ^the fourth row represents the code 011 for the signals ABC as Rufbedingung is, which allows the circuit RC (Fig. 3) to the terminals LT ₁ "^ ^he subscriber line via the resistors R ₁ Z ₂ such that the voltages at the latter can also be used for monitoring the calling process of the called party. The sixth line corresponds to code 101 for ABC dfe signals and an internal test (towards the Office), which now makes it possible to test bus to the test circuit TC to the SLIC circuit through resistors ^to connect ^ Z _{1. 2} On the other hand, the external test (to the subscriber) of the fifth line (100 for the signals ABC) generates a connection between the test circuit TC and the terminal LT ._ without passing the resistors, while the call test (001) for

the signals ABC this time the call circuit RC and the test circuit TC by the resistors together.

Apart from these five states, the subscriber circuit still allows a complete separation of the resistors (000 for the signals ABC) and call monitoring (010 for ABC), the test circuit TC also ^en through the contacts ^s? .I / 32 ^{on the 0di} 9 starting compound is branched , and finally the monitor (110 for ABC), the check circuit TC is also branched, but this time at the normal connection.

The eight ABC codes that make these different states possible are assigned to the eight contact combinations S **. ^, S ₀ . / 22 '. ®71 / ' * P * ' ^ 41/42 ^2U 9 ^ew i ^esen * as indicated by the table; this allows a simple realization of the decoder DEC. In fact, the correspondence table states that £ = B "and that F" = Ä ", except for ABC = 100, that G = O, except for ABC = 000 and BC = 11, and finally FT = A, except for ABC The realization of the decoder DEC is facilitated by these simple correspondence relationships and by the introduction of Y = O, except for BC = 00, where Y is an interbinary signal appearing in the four columns of the table.

The Boolean correspondence relationships can therefore be written as follows:

E = B (A + C) = A * B + B C

F = Ά "+ 7 = a" + "b c *

S = "" 7 + BC = Πϋ + BC ΪΗ = Α + = = A + 3 C "7 = Ε c or Y = B + C,

the second term for E "(FIG. 9) will facilitate comparison with g [(FIG. 10) and those for F, G and H are formed by replacing Y by the displayed value, the Y with respect to FIG 2 is more accurate and accurate in derivation from that of FIG. 10 for G.

Fig. 9 shows the CMOS logic circuit which is the formation of Έ through the use of both three PMOS transistors, which, as shown, are between the potential V. and the output terminal which outputs the function E " , as well as three NMOS transistors, which are connected in the manner indicated between the output terminal and the potential V ^ The three transistors are characterized by the signals A "ß Ü, which are at their gate electrodes, both at the PMOS as well as the NMOS transistors. Their source-drain paths are connected in such a manner that B is in series with a parallel combination AC for the PMOS transistors, while the duality of the circuit containing the NMOS transistors means that B is connected to the Therefore, the signals A, "B, Ü, which are the compliment of those of the intermediate values in the equation, give the signal E *. In particular, it can be seen that when B is at the lower potential, the transistor B under the PMOS transistors is conducting while the corresponding NMOS transistor is off. If one neglects the transistors A and Ü and the PMOS transistors by replacing them with a short circuit, while due to the duality the NMOS transistors A and C "are replaced by an open circuit, then

t 'would be at high potential (V *) such that E * = Έ . This latter is the first factor of the term which denotes E and a state which, as indicated, is preferred for all combinations of ABC except 100, However, for this last combination, with A and C ~ at high potential and B at low potential, both PMOS transistors controlled by A and c "are disabled while the corresponding NWOS transistors are both conducting. In this particular combination E * is consequently at the low potential (V ") which corresponds to E * = B. For the seven other combinations, these four transistors A and C "(PMOS and NMOS) are irrelevant because they neither short the disabled transistor 3 (NMOS) nor insert the conducting transistor B (PMOS) into an open circuit such that only B is relevant, and that E "= Έ results.

Fig. 10 shows the circuit enabling the formation of G "following the principles which are identical to those outlined in Fig. 9. The second form given above for E * allows a direct comparison with the first one for G ^-. In fact, it is readily apparent that for G * four independent variables A, B, C, and Y, instead of three (A, B and E ") is 1" indicates In this way, this time four pairs of NMOS. - and PMOS transistors, which are connected as indicated, necessary, and it is called with the intermediate variable Y »

To form the latter from B and C, as well as F and Ή from A and Y and from A and Y respectively, it is sufficient to use half the circuit of FIG

Transistors "Β and Ü, both for the PMOS transistors connected in series and for the NMOS transistors connected in parallel, by their control with suitable signals, for example B instead of" B and C instead of C, to provide Y.

In this way, for the decoder DEC, which only gets the five signals A, A ", 3, 's and C by saving an inverter for C (Figure 4), only 13 PMOS and 13 NMOS transistors are used used.

Reference is now made to Fig. 11, which shows the electronic contact S ₁₁ of Fig. 3 in detail; this contact represents a modification of that shown in Fig. 1. While still of the TRIMOS type, the thyristor TRX located between the terminals S and S ₂ is slightly different from that shown schematically in Fig. 1 in that the PNIP Transistor T. is now replaced by a PNP transistor Q ₁ having two separate collector electrodes, which are connected to the gate electrodes of the two NPN transistors Q ₂ and Q, which the NPN transistor T ₂ and the transistor T, not shown replace. In addition, individual power protection circuits described in detail below are connected to the thyristor TRX.

It should be noted that the contact S _{12 is} identical to the contact S 1, but that the other six contacts do not include any power protection circuits. The electronic contact S ₁₁ in FIG. 11 contains two identical switching devices S and S ¹ , which are coupled in anti-parallel. par-

In addition, the connection S of the switching device S is connected to the connection S'_ of the switching device S '* while the connection S _{2 of} the switching device S to the connection S ¹ . the switching device S connected 'is · The above-mentioned control circuit is connected to both of the switching device S, as well as to the switching device S ¹ via the terminal p. The switching devices S and S 'are each equipped with a detection output terminal DT ₁ , DT, of which only the terminal DT. is connected to a fault indication circuit FC via a detection terminal DET ₁ . The fault indication circuit FC is also included in the integrated circuit IC and will be described later. Since the switching devices S and S 'are identical, only one of them, for example the circuit S, will be considered below.

As already mentioned above, the transistor Q _{1 of} the thyristor TRX has two separate collector electrodes which are connected to the base electrodes of the transistors Q ₂ and Q, respectively. The collector electrodes of the transistors Q "and Q are both connected to the base electrode of the transistor Q ₁ . The terminal S ₁ is connected to the emitter electrode of the transistor Q ₁ , and the terminal S ₂ is connected to the emitter electrode of the transistor Q ₂ directly and to the emitter electrode of the transistor Q via a measuring resistor R ₁₁ . The base electrode of the transistor Q ₂ is also connected to the collector electrode of an NPN transistor Q ₄ whose emitter electrode is connected to the terminal S ₂ , the terminal S ₁ is connected to the base electrode of the transistor Q. Via the series connection of a diode D ₂₁ , the collector-emitter path

of an NPN transistor Q ₆ . and a resistor R ₁₂ connected The cathode of the diode D-. is also connected to the emitter electrode of the transistor Q ₃ via the series connection of a resistor R--, »the drain-source path of an NMOS transistor N ₁₁ and a resistor R ₁₄ . The connection point of the resistance R.. and the source electrode of the transistor N ₁₁ is connected to the base electrode of an NPN transistor Q, the collector electrode is connected to the base electrode of transistor Q, and an emitter electrode connected to the terminal _S2. The cathode of the diode D ₂₁ is also connected to the drain of an NMOS transistor N ₁₂ whose source is connected to the base of the transistor Q_ together with the detection output DT. connected is. The gate electrodes of the transistors N ₁₁ and N ₁₂ are both connected to the drain of a DMOS transistor N ₁ , whose source electrode is connected to the terminal S and whose gate electrode is connected to the terminal S ₂ . It should be noted that the DMOS transistor N _{13 has} a parasitic diode (not shown) whose anode is connected to the source electrode of the transistor N ₁₃ and whose cathode is connected to the drain electrode of this transistor, and that the NMOS transistors N ₁₁ and N _{12 have} high gate capacitances (not shown).

The thyristor TRX is turned on and off by MOS transistors (not shown) corresponding to the transistors P and N of FIG. The control is carried out via the terminal S .. As already mentioned above, the switching device S includes power protection circuits, which are also suitable for controlling the thyristor TRX whose operation in the following

- 36 detailed will be described.

The thyristor TRX is connected to two separate power protection circuits, the so-called / primary and secondary power protection circuits. The primary power protection circuit includes the components ^D _{21 #} N. _{2 #} Q, R ^ ₂ and Q. and, in particular, limits the current through the thyristor TRX when the voltage on the circuit S exceeds a predetermined value. The secondary power protection circuit contains the components ^D 2i ' ^R l3 * ^N ll * ^ s' ^R 14 ^unc * ^R ll * ^{It should be} noted that in the following description of the operation of the protective circuits is assumed that the voltage at terminal S ₁ with respect to Voltage at the terminal Sp is positive, so that the diode D _{21 is} biased forward. The same operation is valid for the switching device S * in the case that the voltage at the terminal S ' ₂ is positive with respect to the voltage at the terminal S' ^.

The primary and secondary protection circuits are taken in and out of operation by the respective NMOS transistors N .. and N ₁₂ which are controlled by the DMOS transistor N ₁ itself. When the thyristor TRX is in the on state, a positive control voltage of about + 20 volts applied to the terminal S ₄ is transferred to the gate clocks of the transistors N ₁₁ and N ₁₂ via the parasitic diode of the transistor N ₁₃ . Finally, the transistors N ** and N ^ _{2 are} conductive and the protection circuits are in operation. To turn off the thyristor TRX, the control voltage at terminal S becomes from its positive VVert of approximately + 20 volts to a negative value of approximately

- 20 volts reduced. During this voltage transition, thyristor TRX is turned off when the voltage at terminal S reaches approximately -3 volts, while the protection circuits remain in operation, even when the parasitic diode of DMOS transistor N._ is turned off. The NMOS transistors are actually conductive due to the positive voltage being latched by their gate capacitance. When the voltage at terminal S reaches approximately -8 volts, transistor N ₁ becomes conductive so that this negative control voltage is applied to and blocks the gates of transistors N ₁₁ and N ₁₂ . The power protection circuits are then out of service. The transistor N ,. which is coupled to the gate capacitances of the transistors N ₁₁ and N ₁₂ thus forms a delay circuit which shuts down the protection circuits one time interval after the thyristor TRX is turned off. Consequently, the protection circuit of this device remains in operation; how the thyristor TRX is switched on.

When the thyristor TRX is in the on state, no current flows through the primary power protection circuit as long as the voltage on the protection circuit S does not exceed approximately three diode voltage drops. These three diodes are the diode D ₂₁ , dia base-emitter path of the transistor Q_ and the base-emitter path of the transistor Q. It should be noted that the current flow through the primary power protection circuit is so small that the voltage drop across the resistor R _{2 is} negligible, and that the voltage drop across the drain-source paths of the conducting transistor N _{12 is} also negligible

this latter voltage drop is proportional to the base current of the transistor Q, which is still locked. When the voltage across the switching device S increases, transistor Q is conducting and the collector current of the transistor Q ₁ is derived from the base electrode of the transistor Q ₂ to the terminal S ". When the base current of the transistor Q _{2 is} reduced, its collector current and hence the base current of the transistor Q _{1 are} also reduced. Finally, the part Q ₁ ZQ _{2 of} the thyristor TRX is turned off during which part Q ₁ ZQt can remain on, as will be described later.

During the above operation, the main current in the transistor Q ₄ is limited by the resistor R ₁₂ and the transistor Q _g , which itself is controlled by the transistor N ₁₂ .

If only the part Q ₁ ZQ _{2 of} ^the thyristor TRX is considered, the current-voltage characteristic of the switching device S would be the characteristic shown in Fig. 12, where part 1 is the normal I / V characteristic of the forward biased thyristor TRX. As shown, the voltage V rises to a maximum voltage V_ which is equal to the above-mentioned three diode voltage drops (+2.1 volts) and corresponds to a maximum current I of 320 milliamps. It follows from the above that the transistor Q. at the maximum voltage V_ the current I ₁ is accordingly effective so that derThyristor TRX turns off, in accordance with Part 2 of the I / V characteristic shown in Fig. 12. The current in the thyristor TRX and thus in the switching device S is then almost equal to zero, as

high, the voltage across this circuit may also be such that the I / V characteristic then coincides with the voltage axis for the voltages exceeding the voltage V ~. It should be noted that this I / V characteristic is valid for the thyristor TRX as well as for the switching device S.

The DC load characteristic curve 3 of the switching device S is also shown in the diagram of FIG. 12. It is indicated by two dots corresponding to the maximum current I, (70 milliamperes) in the telecommunications line, when the latter is shorted, and the maximum voltage V, (70 volts), when this line is open. This DC load characteristic curve 3 crosses part 1 of the I / V characteristic of the switching device S at a fixed operating point 4.

If there are unwanted abnormal signals on the trunk, they are added to the normal signals generated by the central office so that the load curve moves in the I / V diagram of FIG. Such abnormal signals have various causes, similar to a lightning strike in the telecommunication line or main power supply connected to these lines. The operating point then moves along part I of the I / V characteristic. If these unwanted abnormal signals become very large, the resistance line could shift so that the operating point reaches the upper end of the I / V characteristic part 1. The operating point then becomes unstable and moves to higher voltages while the thyristor TRX shuts off (part 2). The maximum voltage V _M across the switching device S, however, is about 250 volts through the

above-mentioned overvoltage protection circuit (not shown) limited so that süi the operating point then at the point V., located on the voltage axis.

When the abnormal signals disappear, the DC load characteristic shifts to the position shown in FIG. 12, and the operating point moves from V (250 volts) to V (70 volts), the portion of the I / V characteristic of the thyristor TRX, which coincides with the voltage axis, crosses the DC load characteristic 3. The operating point thus becomes stable at the voltage V, and since the primary power protection circuit is still active, it is impossible to turn on the thyristor TRX. In order for the thyristor TRX to be turned on again, the part 2 and the part of an I / V characteristic of the switching device S which coincides with the voltage case should not cross the Gle & H load characteristic so that between the voltage V _M and the normal operating point 4 no stable operating point is available. One solution is to use the secondary power protection circuit described below.

First, only this secondary power protection circuit will be considered. When the switching device S is in the on state, the current flowing from the terminal S to the terminal S ₂ (Figure 11) flows not only through the thyristor TRX but also through the diode D, the resistor R -, -, the drain Sou rce St of the NMOS transistor N ₁ .. and the series-connected resistors R. and R ^ .. As long as the voltage between the terminals S and S _{2 is} relatively small, the

voltage drop across the serially connected resistors R ₁₁ and R ₁ caused by the above currents is less than the base-emitter saturation voltage V ₁ - of the transistor T- which remains inhibited. The current I _f flowing through the thyristor TRX then changes in response to the voltage V ₁ measured at the switching device S according to the part 5 of the I / V characteristic shown in FIG.

It should be noted that due to the resistance values to be given later, the current I (Figure 11) flowing through the thyristor TRX is much larger than the current flowing through the secondary protection circuit. Therefore, the current I can be regarded as the current flowing through the switching device S and, as for FIG. 12, the I / V characteristic in FIG. 13 is valid for both the thyristor TRX and the switching device S. If the voltage between the terminals S ₁ and S ^ is so large that the connected via the series resistors R ,,,, and R ,,. generated voltage drop, caused by the above-mentioned currents, greater than the voltage V_ _{c of} the transistor Ch., then the latter becomes conductive, and thus forms for the collector current of the transistor Q ₁ a parallel path to the terminal S ₁ Consequently, the base current of the transistor Q_ is reduced as a result of the sih increasing the impedance of the thyristor TRX, so that the current I flowing through the thyristor will vary depending on the voltage V in the part I of the I / V _T characteristic changed in Fig. 13 manner. This change is a function of the power dissipation in the thyristor TRX because the voltage drop that forms across the switching device S is not

depends only on the current I, since the resistor R is connected in series with the thyristor TRX, but also from the voltage V ₁ because an additional current, which is a function of the voltage V, through the resistor R ^ ₁ via the resistors R ", And R". flows. Without the resistors R., and R ". wür-

Xo XA- Xo XA

de the current I remain constant and equal to the maximum current I ₀ , as shown by the part 7 of the I / V characteristic in Fig. 13. In this case, the power consumed in the switching device may become unusual because the part 7 crosses the maximum power dissipation characteristic of the switching device S. For the reason mentioned above, the I / V characteristic part 6 should have the DC load characteristic 3. On the other hand, the part 6 of the I / V characteristic should be as close as possible to the Gleichst roni load curve 3 in order to achieve a minimum power loss in the switching device S, since the minimum power loss in the switching device at the operating point of this Circuit occurs, i.e., at the crossing point of the I / V characteristic part 5 and the DC load characteristic 3. Therefore, the loop of the I / V characteristic part 5 should be selected similarly to the loop of the DC load characteristic 3 This loop is a function of the ratio R "/ R. When the transistor Q 1 starts to conduct, its base-emitter saturation voltage Vgp d be defined by the following expression:

V - R ₁₁ . IV _BE

^R 13 ^{+ R} 14 ^R II ^{+ R} 14

where V and I mean the voltage on and the current through the switching device S. »This expression leads directly to

~ 43 -

· ^R 13 = ^V BE

according to the resistance values

R ₁₁ = 7.6 ohms R ₁₂ = 500 R = 145 Κ R ₁₄ - 1 K "

the following assumptions can be made

^R 13 » ^R 14

the final expression is

* ^R 13 ^{= V} 3E * ^R 13 " ^V * ^R 14

so that

^{11 R} 13

It is clear from this expression that the current I of the voltage

depends.

Since the I / V characteristic part 6 is chosen to be as close as possible to the DC load characteristic curve 3 in order to accommodate the power dissipation in the switching means S.

zen, the maximum current I "must be chosen so that it is slightly above the current I, and the maximum voltage V ₂ must be chosen so that it is slightly above the voltage V. In the present example (and with the values of the resistors given above approximately I ₂ = 100 milliamps and Vp = 100 volts.) According to the traditional requirements for a telecommunications system, the protection circuit should only be activated at a current exceeding 300 milliamps For this reason, if the current I_ is chosen to be higher than the required 300 milliamps, the portion 6 of the kine line should be shifted upwards, and a range of the characteristic may be above the line of maximum power dissipation 8. In this case, when the circuit protection circuit becomes active in that the power consumed in the switching device S is so great that the latter is destroyed.

The disadvantages of the two separate power protection circuits can be eliminated by corrobining these two circuits, this combination forming the I / V total characteristic of the switching device S shown in FIG. This characteristic has part 1 and a section 2 of the I / V characteristic related to the primary power protection circuit, and part 6 of the I / V characteristic related to the secondary power protection circuit. From this Fig. It is clear that the I / V characteristic crosses the above-mentioned DC load characteristic curve 3 at a new stable operating point 4, and the power consumed in the switching device S power is reduced to a minimum, since the part. 6 is very close to the DC load characteristic curve 3.

In Fig. 15 is an error indication circuit FC with the input terminals DET. and DET ₂ , the terminals LT. and LT ₂ , the output terminal F and the power supply terminals V _DD (-33 volts) and V ₃₅ C-48 volts). The fault indication circuit FC is connected only to the protection circuit S of the switching unit S (FIG. 11) and the corresponding protection circuit of the switching unit S ₁₂ (not shown). This is sufficient to detect abnormal signals of arbitrary polarity on the trunk loop connected to terminals CT ₁ and LT ₂ .

The input terminal DET of the fault indication circuit FC is connected to the same designated detection output terminal of the protection circuit S of the switching unit S ₁₁ (FIG. 11), while the input terminal DET _{2 of} the fault indication circuit FC is connected to the detection output terminal of the protection circuit corresponding to S of the switching unit S ₁₂ (FIG. not shown). The terminals LTv and LT _{2 of} the fault indication circuit FC are connected to the same designated line terminals of the subscriber line. The output terminal F of the fault indication circuit FC is connected to a digital signal processing device or DSP circuit (not shown) which also forms part of the telecommunications subscriber circuit.

The fault indication circuit FC includes an NPN transistor Q_ whose base electrode is connected to the input terminal DET ₁ through a resistor R ₁ - and whose emitter electrode is connected to the terminal LT ₁ . The power supply terminal V _DD is connected to the collector electrode of Tran

sistor 0_ via the resistor R._ and connected in series with this diode D ₂₂ . Another NPN transistor Q ₀ is connected to the base electrode via a resistor R "_

O "JLu

connected to the input terminal DET ₂ and to the emitter electrode to the terminal LT ₂ , while the connection point of the resistor R ₁₇ and the diode D _{2 is} connected to the collector electrode of the transistor Q ₀ via diode D__. This connection point is also connected to the gate electrodes of an NMOS Transistor N ₁₄ and a PMOS transistor P ..; the source electrode of the transistor P. is connected to the power supply terminal V _DD, and the source of the transistor N ₁₄ is connected to the power supply terminal V ₃₃ . The drain electrodes of the transistors P "" and N are

11 14

both connected to the gate electrode of an NMOS transistor U., its source electrode connected to the power supply terminal V _ss via a resistor R ₁ - is connected. The output terminal F is directly connected to the drain of the transistor N ₁₅ .

The fault indication circuit FC operates as follows. When an abnormal signal is detected by the power protection circuit of the switching devices S of the switching units S ₁₁ and S ₁₂ , or when these power protection circuits are inoperative, the voltage at the input terminals DET ₁ and DET _{2 is} not sufficiently positive with respect to the corresponding terminals LT and LT ₂ for the connected transistors Q_ and O _{0 to become} conductive. Then no current flows through the diodes D_ and D ₂ and consequently through the resistor R, so that the voltage V_. _nl at the gate electrode

17 ^ou

of the transistor N, is more positive than the voltage

(V_ _s) at its source electrode. N. The transistor is therefore conductive, while the transistor P ^ ₁ is locked, since the same voltage is applied to its source and gate electrodes. Finally, the transistor N ^ _{5 is} disabled, and the output terminal F no signal is transmitted. However, when an abnormal signal is detected by the power protection circuits of a switching device S, a voltage appearing with respect to the voltage at the terminal LT. (1-T ₂ ) is positive at the input terminal DET ^ (DETp) of the false display circuit FC. It should be noted that the voltage at the terminal LT. (LT_) is more negative than the voltage at terminal ^V _D. ^D * f * transistor Q (Q ₈ ) then becomes conductive and from terminal V " _o to terminal LT. (LT _{2), p} via the resistor _R17, the diode D_ (D ") and the collector-emitter path of the transistor Q ₇ (Q ₃₎ a current to flow. Consequently, the transistor N blocks -. * And the transistor ^P ll ^w ^ ^{r (^} conductive so that the voltage V _Q0 appears at the gate electrode of the transistor N ^ _5, which is also conductive, the circuit ^ .- / Rg then generated. a current which is transmitted via the terminal F to the circuit DSP, which in turn is capable of triggering certain effects.

While the principles of the invention in connection with a specific device have been described above by way of example only, it is to be understood that this is not a limitation on the scope of the invention.

Claims (34)

Erfindunqsanspruch 1. An electronic contact for forming a low or high impedance between first and second terminals according to the control of a circuit which provides a control signal between a third and a fourth terminal, characterized in that two electronic reserve contacts are provided, which allow a low and to form a high impedance between the first and the third terminals (NA) and between the second and the third terminals (NB), the impedance states of these two reserve contacts being opposite. " 2. Electronic create contact according to item 1, characterized in that it comprises a first biassed contact (S), which is suitable for a low impedance at a predetermined voltage polarity between the first (S ₁₎ and second (S ₂₎ terminals, in parallel with a second biased contact (S ') suitable for forming a low impedance for the opposite polarity. 3. Electronic contact according to item 2, characterized in that the prestressed contacts are identical and connected in antiparallel form (S ^ / S'p, Sg / S ^1. ). 4. An electronic contact according to item 2, characterized by a thyristor-type biased contact (T-i / p) which includes two control terminals enabling the low or high impedance state to be turned on by the control signal. 5. An electronic contact according to item 4, characterized in that the two Steueranschlüssa each with the second terminal (Sp) are connected by a MOS transistor, wherein the gate electrodes of these transistors of complementary polarity with the fourth terminal (S.) are connected, while the source of one transistor (M) and the drain of the other transistor (P) are connected to the second terminal. An electronic sowing element forming part of a circuit and also including a power source and a load, and said device includes means for. to limit the power dissipation therein, characterized in that said power-limiting device (^ _11; ^ ₁ ι R _14;? Q ₅₎ is designed so as £ a current-voltage characteristic (Fig, 13) is generated for the device, the starting at the zero point crossing the load characteristic (3) of the component (5) and then following said load characteristic (6) in the direction of the voltage axis (V ₂ ) without again crossing the load characteristic passing through the short circuit current (Ij) the component and its open circuit voltage (V) is marked. 7. Electronic device according to item 6, characterized in that it comprises a switching device (Q _1/3 ) arranged between the first (S./S ¹ ) and second (S ^ / S ') terminals to form a low or high impedance defined by said current-voltage characteristic. 8. An electronic component according to item 7, characterized in that said power limiting device (^ ₁₁ ; ^R i3 * ^R i4 ^; ° -g) is ^{connected to} said switching device (Q ₁ / -?) And a first scanning device (R ₁₁ ) connected in series with said switching device, a second scanning device (R ₁ - ,, RJ ₄ ) * which is connected in parallel with said switching device, and a control device
(Qc) controlled by said first and second scanning devices and controlling said switching device so as to form said current-voltage characteristic. 9. Electronic device according to item 8, characterized in that said first (R ₁₁ ) and second
(R ₁₃ , ^ ₁₄ ) scanning devices are connected in series, and that said control device is an active
A device (Q ₆ ) having an input part coupled to said first sampling device and a part of said second sampling device and a
Output part which is connected to said switching device (Q-1 / -5). 10. The electronic sowing element according to item 9, characterized in that said first scanning device includes a resistor (S ₁₁ ), said second scanning device includes at least two resistors ( ^R ₁₃ i RI ₄ ) connected in series, and that the said control device comprises a transistor (Q, -). -Si11. Electronic component according to items 7, 8 and any one of items 1 to 5, characterized in that said switching device (CL, _) forms part of said electronic contact (S, S ¹ ), and in that said power limiting device (RJ ₁ ; ^ 3 "R ₁₄ ; Q, -) is coupled to an interruption device (W ₁₁ * N ₁₇ ) controlled by said control signal and operating and resetting said power limiting device after said switching device (Q ₁ Z ₃ ) has formed said high impedance. 12. The electronic component according to item 6, characterized in that the part (5) of said current-voltage characteristic (FIG. 14) crossing the load characteristic (3) has a first region (1) which is in the range of such voltages (FIG. V ₀ ), which are substantially smaller than said open circuit voltage (V,), based on a current (I ₁ ), which is substantially greater than said short-circuit current (I,), and a second region (2), the connecting the said first area (1) to the part (6) of the characteristic following the load characteristic (3). 13. Electronic device according to points 8 and 12, characterized in that it further holds a second power-limiting device ( ^D ₂ i * ^ 5 ' ^R l2' ^ 4 ^ ^snt ~ holds, which consists of a third scanning device (D »., Q , ^R 12 '^ 4 ^ ^{to ADtastun} 9 the voltage across said electronic component (S; S') and a second Rg- gating device (Q ₄ ) controlled by said third sampling device and controlling said switching device (Q ₁ , _) to produce said first (1) and second (2) regions of said current-voltage characteristic. 14. The electronic component according to item 13, characterized in that said third scanning device ⁽⁰ OI * 0_ # Ri ^£; Q4) included and said control apparatus (Q ₄₎ having a common first active device _(Q4) whose output part with the said switching device is coupled. 15. Electronic device according to points 7, 13 and one of the items 1 to 5, characterized in that said switching device (Q ₁ , -,) forms part of the said 1/0 electronic contact (S; S ¹ ), and in that said second power limiting device ( ^D 2i * Qr * ^ 12 '^ 4 ^ ^{mj t} is coupled to ^a breaker device (hLp * ^N i * *) which is characterized by Control signal is controlled and takes said second power limiting device into operation and decommissioned after said switching device (Q- /,) has formed said high impedance. 16. The electronic device according to item 7, characterized in that said switching device (Q.,) consists of second (Q ₁ ), third (Q ₂ ) and fourth (Q,) active devices, that the first output terminals of the third and fourth active components with the control are coupled to the terminal of the second active device, that the second output terminals of the third and fourth active components are coupled to said second terminal (S ₂ / S '), that the first output terminal of the second active device to the first terminal (% / S' p), and in that the second active device has two separate secondary output terminals coupled to the control terminals of the third and fourth active devices, respectively. 17. The electronic component according to item 16, characterized in that said second active device (Q.) Consists of a PMP transistor whose control, first _t and second output terminals are the base, emitter and collector electrodes, and in that said third (Q ₂ ) and fourth (Q) active devices are each formed by an NPN transistor whose control, first and second output terminals are the base, collector and emitter electrodes, respectively. 18. Electronic change-over contact, which allows the formation of low and high impedances between first and second terminals on the one hand and a third terminal on the other hand, the impedance states for the first and. the second terminal are complementary, characterized in that the polarity of the voltage applied between the first and second terminals determines the impedance states. 19. Electronic contact according to item 18, characterized in that the changeover contact consists of two transistors der- is the same polarity, and that the first terminal (S.) to the second output terminal of the first transistor (NA) and to the control terminal of the second transistor (NS) is coupled, and that the second terminal (S ₂ ) to the first output terminal of the second transistor and coupled to the control terminal of the first transistor, and that the third terminal (S ₃ ) is coupled to the second output terminals of the transistors. 20. Electronic contact according to item 19, characterized in that the transistors are of the NMOS type. 21. An electronic change-over contact, which allows the formation of low and high impedances between a first (V ^, Fig. 5) and a second (V ₂ ) terminal on the one hand and a third (A) terminal on the other hand, wherein the impedance states for the first and second Terminals are complementary, characterized in that the first, second and third terminals are coupled to the source, gate and drain electrodes of a MOS transistor (D), and that the polarity of the voltage applied between the first and second terminals is that the transistor conducts, and that the second and third terminals are additionally coupled to the emitter and to the collector of a bipolar transistor (T ₄ ) in such a manner that, when the latter is disabled, between the first and third terminals low impedance is formed, whereas when this is conductive, a low impedance is formed between the second and third terminals will become. 22. Charging circuit, which is capacitively controlled, consisting of a Gegsntakt-Gleichstromsignalquella by
two row input capacities with the input of one
Rectifier circuit is connected, characterized in that a third series input capacitance (C,), whose input terminal is coupled to said signal source, and whose output ^terminal is also connected to the input of said rectifier circuit, which consists of a first (D- # D ₂ ) ^Dzw A second (D ₃ , D ₄ ) part is provided which allows the formation of either a first or a second DC output polarity such that the charge of the output capacitance (C ₁ C) of a first or a second polarity due to
Control device (IC) corresponds, and that the first
and the second parts of the rectifier circuit
first complementary MOS transistors (P- # N _- .) Are decoupled, the gate electrodes of which are connected to the third input capacitance (C,), and second MOS transistors (N ₂ , P ₂ ), which are complementary to the first
are where the two complementary transistors in the first (P ₁ * N ₂ ) and the second (N ₁ , P ₂ ) part on both sides of the output capacitance (C / C) are arranged, and the gate electrodes of the second transistors with the
Drain electrode of the first transistor of the same polarity are coupled, and daS the source electrodes of the two
Transistors (P, P ₂ ) of a first polarity (P »P ₂ )
each coupled to the first input capacitance (C.) by a diode ( ⁰ ^ * ^D ), and the source electrodes
the two transistors of the second polarity (N, N)
each coupled to the second input capacitance (C ^) through the diode (D, D). 23 »telecommunications system part Nahmer circuit comprising a series impedance in each of the two line wires and out contacts on each side of these two impedances enabling to selectively connect their terminals to the office or the line or, alternatively, to the replacement circuits, characterized in that there © these contacts are constituted by four electronic contact pairs, wherein the first (S _11, p ') the line to the impedances, the second (S ₂ I' ^S 22 ^ these ^mj - ^t office, the third (S_ _{1 #} S ₂ ) the impedances on the Lsitungsseite with a first reserve circuit (TC) and the fourth (S ₄₁ , S ₄₂ ) connects this on the office side with a second reserve circuit (RC) * 24. subscriber circuit according to item 23, characterized in that the eight electronic contacts, which are always in pairs in operation, are additionally controlled in such a way that only eight combinations among the sixteen possible for the four pairs are allowed. 25. Subscriber circuit according to item 24, characterized in that the eight closed and open combinations of the four pairs of contacts are defined by the eight binary codes 1111, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 with the first, second, third and fourth digits from the left corresponding to the first (S ₁ *. * -), second ( ^S 2i / 22 ^ ' third k ^^ l / ZZ ^^ ^fourth ( ^S 4i / 42 ^ ^pairs * where the f Ö Numerals 0 and 1 show the closing or opening of the contact pair. 26. Circuit having a plurality of electronic contacts which can be operated in accordance with different combinations by binary control signals, characterized by a decoder (DEC) which is contained in the circuit and by at least a part of the signals (IC _1/2 , ,) to output binary output signals to an array of gates (GH), which also receives the binary control signals directly (GD), and that a drive signal (IC_) allows control of the gates in such a manner that the Flow of control and output signals is always allowed and prohibited or vice versa. 27. Subscriber circuit according to points 25 and 26, characterized in that the eight binary (ABC) input signals OCO, 001, 010, 011, 100, 101, 110 and 111, the decoder (DEC) corresponding to the eight combinations of the binary ( E *, F ", G ~, FT) control output signals 1111, 1100, 0100, 0110, 0101, 1001, 0001 and 0011 ( ¹ C ₁ Z ₂ Z ₃ ) 'are supplied by the decoder. 28. Subscriber circuit according to item 27, characterized in that the binary decoder output codes, which are formed as a function of the binary input codes by five logic circuits, are given by the Boolean equations E = B (A + C)
F = Ä '+ 7
G = A7 + BC FT = A + 7 Y = 3 + C where Y is an intermediate signal and where A, "b and 7 are the compliments of A, B and Y, respectively. 29. The circuit of item 26, characterized in that the arrangement of the gates (GH / GD) provides an output signal that controls two oppositely connected clock gates in such a manner that either one or the other either a clock signal or its compliment transfers. 30. Circuit according to item 29, characterized in that the clock signal and its compliment are generated by a clock oscillator which is part of the same integrated circuit as the gate assembly, the decoder, the electronic contacts and their control circuits. 31. A telecommunications system subscriber circuit having a series impedance in each of the two line conductors and contacts on each side of these two impedances, which allow selective connection of their terminals to the office or the line, characterized in that these contacts are formed by two pairs of electronic circuits, the first (S ,,,., S ^ ₂ ) connecting the line with the impedances and the second (S ₂₁ , S ₂₂ ) connecting them to the office (SLIC), and that only said first pair of electronic contacts ( ^s _{i ii} ^ 12 ^ "^ ^1" * ^siner power-limiting device ₍₁ RJ; ^ * -tz R _14; Q) is equipped so as claimed in section 8. 32. Fernmeldesystem subscriber circuit according to item 31, characterized in that said first pair of electronic contacts (S ₁₁ , S ₁₂ ) is also equipped with a second power limiting device (D _0. , Q ₅ , ^ ₁₂ ; ^ d) as claimed in item 13. 33. A telecommunication system tachograph circuit according to items 31 or 32, characterized in that it further comprises a detection device (FC), which is coupled to the common first pair of electronic contacts (S ₁₁ , S ₁₂ ), and provides a signal, indicating that the voltage across at least one of said electronic contacts exceeds a predetermined value. 34. telecommunications subscriber circuit according to the points 2 and 33, characterized in that said detection means (FC) a detection circuit (R ₁ CZ ₁ Ot Q7 / R 'D__ _{/ c3} _, P ₁₁ JN _{1. / Λ} _) with a first input part (R ₁ -J Q-) coupled to said first biased contact (S) of the first electronic contact (S ..) of said first pair (S ₁₁ , p. ₂ ), a second input part (R ₁ , - / Qr ^ * ^ ^as " ¹ ^ ^ ^em 9 ^{enann1: s} first pre- ^paired contact of the second electronic contact (S ₁₂ ) of said first pair is coupled and an output part (0 _, _, ^D _{2 2/2} v - ^ 17 ^, which is connected to a display circuit (P ₁₁ IN ₁ .,., R _1S ), which is also contained in said detection device, and which provides at an output terminal (F) said indication signal, the voltage on at least one of said biased contacts (S) depends. 35. Fernmeldesystem subscriber circuit according to item 34, characterized in that said first (^ ₁ Ci Q ₇ ) and second (R ₁₆ * Qo) input _parts of said detection _circuit (R _{1 (; / 1RJ} Q ₇₇₈ , D ₂₂₇₂₃ , P ₁₁ , N ₁₄₇₁₅ ) each _{7 7 7 /} weils through the base and emitter electrodes of an NPN transistor (Q _7, Q ") are formed between the said power-limiting device and one of the two terminals of said biased contact (S) is connected, that said output part is formed by the collector electrodes of said NPN transistors, with which a first DC power _{supply terminal} (V _QD ) via a first resistor ('R ₁₇ ) is connected in series with the respective diodes (D ₂ ? ' ^D 23 ^), and that said indicator circuit (P ₁ * »N. .., .., R ₁₈ ) has a PMOS (P ₁₁ ) and a first NMOS (N ₁₄ ) transistor whose gate electrodes are both connected to the connection point of said first resistor (R ₁₇ ) and said diodes (D ₀ , ^Ώ ο · ζ) whose drain electrodes are linked together, and their source electrodes respectively with said first (V _DD ) and a second (V " _g ) DC power supply terminal, and that said common drain electrodes of said PMOS and first MMOS transistors are connected to the gate eelektrode of a second NMOS Tran- * sistor ( ^N ₁₅ ) are connected, whose source electrode with said second DC power supply terminal (V) via a second resistor (R ₁₈ ) ^and its drain electrode is connected to said output terminal (F). 36. Fernmeldesystem subscriber circuit according to any of the items 31 to 35, characterized in that it contains third and fourth additional pairs of electronic contacts, wherein d_ar third (S ₃₁ , ^s ₃ p) ^ ^ie impedances (R ₁ , R ₃ ) ^au ^ ° * ^ΘΓ line side (LT, LT ₂ ) with a first reserve circuit (TC) and the fourth (S ₄₁ , ^S 42 ^ ^{ies au} ^ the office side (SLIC) with a second reserve circuit (RC) ver binds. For this 8 pages drawings