CA1121926A - Pulse width modulating signal generator and method - Google Patents

Abstract

Abstract of the Disclosure In a telephone switching facility, line circuits are arranged in groups, each including a local ringing battery bus, and a universal high level signal generator (UHLSG) for providing ringing and other high level signals to the line circuits via the local ringing bus. Each generator is responsive to address signals from a controller in the switching facility to generate selected high level signals. The UHLSG includes a switching bridge driven by a width modulated signal stream of periodically occurring pulses having assertion times suitable for developing a high level signal across a network at the output of the switching bridge. The width modulated pulses are generated from period and time signals. The period signal occurs once with each sequence in repetitively generated data byte sequences. The time signal occurs with correspondence between a selected stored data byte and an instant one of the data bytes of the sequence. A plurality of the stored data bytes are arranged in ranges in a storage circuit. One bit in the last data byte in each range causes the storage circuit's next readout to be from the beginning of a range as directed by the controller in the switching facility.

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Description

This specification has been divided from a patent application by R. Hayward et al with Serial Number 330,867 filed on 29 June, 1979.
The invention relates generally to telephone switching systems and more particularly to a universal high leYel signal generator for generating signalling and supervision signals in the operation of subscriber lnops.
Signalling and supervision signals used in the control of subscriber and coin telephone apparatus are almost invariably of the high level type with typical Yoltage e~cursion exceeding 100 volts. These high level signals are compatible with electromechanical switching technology but are not suitable in close association with solid state apparatus of the recent developments in telephony. Hence these signals are typically applied directly to the subscriber loop as required via relay contacts arranged to substantially isolate the switching matrix and any associated solid state interface circuitry from the applied high level signals. These signals are routed across the various relay contacts by way of one or more bus bars typically termed ringing battery buses.
The signals are centr~lly generated in the telephone switching facility either by a group of dedicated signal sources or by a universal generator having a multiple function capability. A recPnt example of a dedicated generator is described by A. Rimardine, G. Balzarini and S. Calende in United States Patent No. 4,152,670 entitled "Signal Generator, Especially for Ringing Current in Telecommunication System" which issued on May 1, 1979.
A universal generator adaptable to providing the required waveforms is described in an article entitled "Digital Waveform Synthesis" by E.T. Powner, D.H. Green and G.T. Taylor, pu~lished in August 1969 in Electronic Engineering.
The output signals of this generator must be amplified to obtain the required high level signals for the ringing battery bus.
In a telephone switching office with a solid state network the routing of these siynals i 5 necessarily restricted. As for example illustrated ~ L~3~

in a paper entitled "Design Techniques which Reduce the Size and Power of the Subscriber Interface to a Local Exchange" given by H.E. Mussan and D.P. Smith, at the 1978 International Zurich Seminar on Digital Communications, high level signalling is preferably restricted to that portion of a subscriber line circuit remote from the switching network. In a more recent paper by R.K. Eisenhart and U.K. Stagg concerning the Bell Laboratories No. lOA Remote Switching System, it is suggested that all of the high level signals be generated in a "universal ser\~ice circuit" (USC) with all the subscriber lines being supplied therefrom. In each case, routing of the ringing battery bus is critical to the operation of the switching facility. Care must be taken to ensure that higher power levels on the ringing battery bus associated with peak traffic periods do not generate stray radiation of a strength that wil1 interfere with the low level signal functions of the switching network and its associated controller.
In a telephone switching facility, the present invention pr~vides an arrangement utilizing a plurality of uniyue universal high level signal generators whereby high level signalling distribution is restricted to individual groups of telephone line appearances and line circuits. Switch means in each of the line circuits provide for alternate c~nnection of a telephone line to either a central talking battery bus or a local ringing battery bus. The local ringing battery bus is restrict~d to a line circuit group and an associated one of the universal high level signal generators.
This arrangement eliminates extensive routing of a ringing battery bus bar and the heavier concentration of high level signalling power. Stray signal radiation is further reduced in that similar signals being generated by two or more generators are inherently randomly phased.
The universal high level signal generator includes a storage means for storing a plurality of data bytes at least one of each relating to each of the predetermined high level signals. A signal generating means ~2~2~

generates a stream of periodically occurring low and high signal states defining width modulated pulses in response to at least one of the data bytes from the storage means and the clcck signals. A switching bridge inc1udes a control input connected to the signal stream generating means, a first pair of opposite terminals for connection to a power source and a second pair of opposite terminals. The switching bridge is responsive to the high and low signal states of the signal stream to alternately connect a potential appearing across the first pair of opposite terminals to the second pair of opposite terminals to provide the high level signal.
The universal high level signal generator is particu1arly adapted to providing the high level signal with reduced harmonic frequency content by the addition of a reactance element in a network, connected across the second pair of opposite terminals, and by the addition of an impulse filter connected in series with one of the first pair of opposite terminals. In this case the high leve1 signal is obtained across the reactance element.
In one embodiment, the switching bridge is provided by a first set of transistor switch circuits and a second set of transistor switch circuits, each being transformer coupled via associated drive means.
The first and second sets of transistor switches are coupled to respond to the signal stream in complementary ~ashion. The windings in each coupling transformer are poled such that when current is conducted by the associated drive means the associated transistor switch circuits are biased ~FF and when the associated drive means is OFF the transistor switch circuits are turned ON.
The signal s~ream generating means includes a storir,g means for storing data bytes each representative of a period of time. A first means responsive to clock signals repetitively generates a sequential ~ 9~
series of data bytes. A second means generates a per;od signal in response to each occurrence of a completed sequence of the sequential series of data bytes. A comparator generates a time signal in response to a predetermined correspondence between a selected one of the stored data bytes and an instant one of the data bytes at the output of the first means. A third means generates the signal stream consisting of a pulse width modulated signal with assertion periods being defined by consecutive occurrences of the period and time signals.
In one embodiment, the storage means is a function storage and retrieval circuit which includes a memory with data bytes stored in ranges of address accessible locations. At each address at the conclusion of a range, the corresponding data byte has a predeter~ined data bit of one state, the remaining data bytes having said predetermined data bit of the other state. A counter includes data inputs and a load input, and generates addresses corresponding to addresses in the ranges. This causes the memory to read out the associated data bytes. The counter is operable to count from a starting point which is determined by the signal states of its data inputs at the moment of a signal assertion at the load input. A connection is provided between the memory and the load input with each occurrence of said predetermined data bit of the one state. Hence when the generated address corresponds to the end of a range the counter is automatically reset to a starting pDint at the beginning of a range.
The invention also includes a method for generating the pulse width mDdulated signal and comprises the steps of: registering a data byte representat;ve of a period of time; generating a sequential series of data bytes at a predetermined rate; generating a period signal with the occurrenee of the latter step; generating a time signal in response to a predetenmined correspondence between the registered data byte and an instant one of the data bytes in said series of data bytes; and generating a pulse signal having an assertion width defined by the occurrences of the period signal and the time signal. - -An example embodiment of the invention will now be describedwith reference to the accompanying drawings in which:
Figure 1 is a block circuit diagram of an improved telephone switching facility with distributed high level signalling; and Figure 2 is a block schematic diagram of one of a plurality of universal hi~h level signal generators in the ielephone switching facility in figure 1.
Referring to figure 1, the telephone switching facility includes a controller 100 connected to a switching network 101 via a data bus 102, a control bus 103, an address bus 104 and a clock lead 105. The controller 100 is also connected to a plurality of line equipment shelves 106, only one of which is shown. Each line equ;pment shelf includes a group of line circuits 114 and a universal high level signal generator (UHLSG~ 111.
The UHLSG 111 is connected to a source of clock signals in the controller 100, by a clock lead 105. A single control lead 113 from the control bus 103 and the address bus 104 are also connected to the UHLSG 111. Other UHLSGs 111 on the other line equipment shelves are similarly connected except that a separate control lead in the control bus 103 is connected to each UHLSG 111.
A central battery 110 is connected via a talking battery bus bar 109 to each line c;rcuit 114 in the telephone s~itching system. Each line circui t i 5 connected to the switching matrix such that supervision and communication paths 107 and 108 are provided therebetween. In this instance, separate conductors are illustrated by way of example. ~ime multiplexinQ methods and apparatus for this purpose are well known which serve tD reduce the actual numbers of hard wire connections to the network. A local ringing battery z~ ~

bus 112 is connected from the output of the UHLSG 111 to each of the line circuits 114 on the equipment shelf 106. A cross connection between the local ringing buses on adjacent pairs of equipment shelves is provided by relay transfer contacts 131 which when actuated feed the local ringing bus 112 from the UHLSG 111 on the adjacent equipment shelf. The cross connection, as exemplified by contacts 131, is provided to improve the reliability of the system and is actuated upon the failure of an adjacent UHLSG.
Each line circuit 114 includes voice coupling and supervision circuits generally residing at 115 which are not the subject of this invention and hence are not shown. Various circuit arrangements for performing these functions are well kno~n in telephony. Talking battery for energizing a telephone line 123 is supplied from the talking battery bus bar 109.
Battery feed resistor 116 and 117 are connected in series between the telephone line 123 and the talking battery bus bar 109 via the break portion of transfer relay contacts 121. When high level signalling is required on the telephone line 123, the relay contacts 121 are actuated by the supervision circuits at 11~ to cause the telephone line to be disconnected from the talking battery bus bar 109 and connected via the make portion of the transfer contacts 121, through ringing battery feed resistors 118 and 119 to the local ringing battery bus 112. The state of the telephone line 123 at any one instant is available to the line circuitry at 115 either through the conductors 120 or the conductors 12~ in the talking battery or ringing battery modes respectively.
The actual detailed operation of the illustrated telephone switching facility is not essential to the understanding of the invention;
however, further details of the operation as they pertain to the provision and control of high level signalling in a telephone system will become apparent in the following description of the UHLSG illustrate~ in figure 2 of the drawinys.
Referrin~ to figure 2~ the elements identified by numerals 2 through 29 function to provide a pulse width modulation signal generator which generates a signal stream of periodically occurring low and high signal states. The elements identified by numerals in the range of 30 to 75 include a switching bridge which functions to provide high level signals while the remaining elements are concerned with providing a maintenance function and the cross-connection function. The structure and operation of the pulse width modulation signal generator and the high level signal generator will become apparent in the following functional description of these circuits.
The pulse width modulation signal generator includes counter circuits 2 and 3 connected to repetitively generate a sequential series of data bytes on a real time bus 4, in response to clock signals supplied on the clock lead 105. In one example, the clock signal on the clock lead 105 has a pulse repetition frequency (PRF) of 5.12 MHz. There are 160 codes in the sequential series which yields a sequential repetition frequency of 32 KHz. The clock signal is applied to the count input C of the counter circuit 2 and counted to provide ~our least significant bits~ 0 - 3, on a real time bus 4 and is divided by 16 to yield a carry signal with a PRF of 320 KHz at a carry output C0 of the counter circuit 2. The carry output C0 of the counter circuit 2 is applied to the count input C of the counter circuit 3.
The counter circuit 3 counts the 320 KHz PRF signal to provide the four remaining bits, 4 - 7, on the real time bus 4. A NAND gate 5 is connected with the counter circuits 2 and 3 so as to cause ~he counter 3 to act as a divide-by-ten circuit whereby the most signi~icant bit 7 on the real time bus as a PRF of 3Z KHæ. The output of the NAND gate ~ is connected to the clear input CLR of the counter circuits 2 and 3 and becomes asser~ed with each sccurrence of 160 pulses on the clock lead 105. This causes the counter '' ~ .

circuits 2 and 3 to be cleared to all zeros and commence to generate another sequential series of the data bytes. The output of the NAND gate 5 is also buffered by an inverter 7 which has an output connected to the count input C of a counter circuit 6 and to the D input of a D type flip-flop 12.
The 32 KHz signal from the NAND gate 5 is divided by four in the counter circuit 6 and used to generate complementary phased 8 KHz timing signals at the output of NAND gates 8 and 11 respectively. The flip-flop 12 includes a clock input CK which is connected to receive the 5.12 MHz PRF clock signal on the clock lead 5. The clock signal in combination with the inverted output of the NAND gate 5 causes the flip flop 12 to generate a period signal at the 32 KHz rate at its output Q. The period signal coincides with the occurrence of each highest value data byte on the real time hus 4.
Binary data bytes each representative of a discrete period of time are stored at address accessible locations in a read only memory (ROM) 18. These data bytes are arranged in groups of address ranges, each range corresponding to a predetermined high level power signal. An address range relating to a direct current signal consists of only one address while an address range relating to an alternating current component signal consists of a plurality of addresses. In this particular example the stored data bytes include one data bit which is used to control access to the ROM 18.
This data bit is consistently in one state throughout the address range except for the last address o~ the range where the stored data bit is of the other state. When there is only one address in a range, the data bit is of the other state at that one address. When this bit occurs, in a readout, the next readout from the ROM is derived from the beginning of an address range.
The desirability and use of this circuit function will become more apparent in the following description which culminates in the generation of a time signal. The time signal is used in combination with the period signal to define the width modulation of the pulses in the signal stream.
The circuit ele~ents identified with numerals in the range of 15 and 25 perfonm the function of generating the time signal as it is selected by the coincidence of a load signal on the control lead 113 and a function address on the address bus 104. Fhe function address bus 104 is registered in a register circuit 15 under the control of the load signal.
The function address is available from the output of the register circuit 15 at the data input o~ a counter circuit 17. The counter circuit 17 also includes a count input C which receives the 8 KHz PRF signal from the output of the NAND gate 8 and a load input LD, connected to the output of an inverter 21. If the output of the in~verter 21 is asserted, the counter circuit 17 is set at the function address in the register circuit 15 from which point it is caused to count at the 8 KHz rate. The output of the counter circuit 17 is connected to the address input of the ROM 1~ which reads out time related data bytes from its corresponding addressed storage locations as the counter circuit 17 progresses through a range. Register circuits 19 and 20 are connected in series with the output of the ROM 18 and are controlled by the outputs of the NAND gate 11 and the inverted output of the NAND gate 8 respective7y to provide the time related data bytes at the output of the register circuit 20 delayed by one 8 KHz period.
One of the data bits from the output of the register circuit 20 is inverted in the inverter 21 and applied at the LD input of the counter circuit 17.
By this means the counter is again loaded with ei$her the previous counting start point or, in the event that a new function is required by the controller 100, at the required new start point. An adder circuit 22 includes an A input connected to the output of the register circuit 20 and a B input connected ~o a hard wircd constant, value 16, via 2 plurality Qf leads 23. In this embodiment the ROM 1~ includes ar, eight bit data byte output. As one of these bits is used for the load control of the counter circuit 17, there are seven remaining bits yieldinQ 128 codes. However there are 160 real time data bytes produced on the bus 4. Hence ~he output of the ROM 18 is augmented by the constant 16 in the adder circuit 22 to proYide a usable code range from 16 to 144 which is adequate for the operation of the on-fol~owing circuitry. A function time bus 24 carries the sum of the A plus B function of the adder circuit 22 to an A input of a digital comparator 25. The digital comparator 25 also includes an A = B output and a B input. The B input is connected to receive the repetitive sequence of data bytes from the real time bus 4. Each time the states of the inputs A and B correspond, the A = B output of the comparator 25 becomes asserted, providing the time signal.
The signal stream of width modulated pulses is generated with a 32 KHz PRF on a lead 28 connected at the Q output of a D type flip-flop 26.
The flip-flop 26 operates under the control of the time signal applied at its clock input CK and the period signal applied via a lead 27 at its clear input CLR. The pulses of the signal stream are raised to a higher Yoltage level. suitable for the operation of the switching bridge, in an inverter 2g having an output connected to a +Y power source via a resistor 29a. A twenty to thirty volt positive power supply is typically included in a telephone switching facility and is suitable power source for this embodiment. The high level signal generation function requires a higher potential supply. A floating power supply 70 provides about 300 Ynlts across its output leads 71 and 72 which are connected to power tenminals -Vl and ~Yl respectiYely. An impulse fllter includes a choke 73 connected in parallel with a flyback network having a diode 74 and a resistor 75. The impulse filter is connected in series with the power tenminal ~Yl~ Alternately, the impulse filter may be connected in series with the other power terminal or two impulse filters may be used.

2 6 Ihe switching brid~e includes four switches 50A - 50D and three drive circuits 30, 30a and 30b. The switches 50A and 50B are connected to the output of the drive circuit 30 via an RC network 42, and a transfor~er 40 having a primary winding 41 and a pair of secondary windings 44. The switches 50C and 50D are connected to the output of the drive circuit 30b via an RC network 47 and a transfonmer 45 having a primary winding 4~ and two secondary windings 49. The transformers 4D and 45 are each poled such that when the primary winding is conducting rurrent, the secondary windings provide turn OFF bias to the switches. When current flow through the primary winding is halted, turn ON current is provided by the secondary windings.
Each driver circuit 30 and 30a includes an input c~nnected to the output o~ the inverter 29. A resistor 38 is also connected between the output of the inverter 29 and ground. The output of the driver circuit 30a is connected to a load resistor 39 and to the input of the driver circuit 30b.
The driver circuits each function as inverting amplifiers and by this means the signal stream and its comp1ement are used to drive pairs of the switches 50 in complement.
The signal stream is received at an input port 31 in each drive circuit 30 a~d 30a. Each drive circuit includes a metal oxide silicon field effect transistor (MOSFET) 34 with source, drain and gate electrodes s, d and g respectively. The drain electrode d is connected to an output port 37, the source electrode is connected to ground and the gate electrode g is connected to the input port 31 via the parallel combination of a resistor 32 and a capacitor 33. A diode 36 and a resistor 35 are connected in parallel across the gate electrode g and the source electrode s.
In operation each driYer circuit acts as an inverting amplifier. The signal at the output of the driYer circuit 30a is received and inverted by the driver circuit 30b to generate at its outp~t port the complement of the signal at the output port of the driver circuit 30. The use of a MOSFET type 2N6661 was found to yield better dynamic turn ON and turn OFF
definition with respect to the signal pulse stream than did various bipolar transistors of the NPN type.
Each of the switches 50A - 50D includes a series string of a resistor 51, a diode 52 and a resistor 53 connected across the associated secondary winding. A NPN transistor 54 includes an emitter electrode connected at the junction of the resistor 53 and the secondary winding. A resistor S5 is connected at the junction of the secondary winding and the resistor 51 and in series with two diodes 56 and 57 to the base electrode of the transistor 54. The base electrode is also connected to the junction of the diode 5~ and the resistor 53. A diode 58 is connected between the collector electrode and the transistor 54 and the junction of the resistor 55 and the diode 56. A diode 59 is connected across the collector and emitter electrode in current opposing relationship. In operation, turn ON current from the associated secondary winding flows via the resistor 55, the diodes 56 and 57 and via the base emitter junction of the transistor 54, to cause the transistor 54 to conduct current. Turn OFF
bias is developed at the base electrode when current flows in the opposite direction through the secondary winding via the series string of the resistors 53 and 51 and the diode 52, to cause the transistor 54 to cease conduction. Diodes 56, 57 and 58 provide an anti-saturation network to ensure rapid switching of the transistor 54. The diode 59 provides a conducting path for inverse reactive load c~rrents.
The switches 50a and 50b provide a first set of two switches connected to apply a voltage Vl in one direction across the network 60 in response to the signal stream being of one instant state. The switches 50C

- lZ -and 50D provide a second set of two switches connected to apply the voltage Vl in the reverse direction across the network 60 in response to the signal stream being of the other instant state. The network 60 includes a series connection of an inductor 61 and a capacitor 62. Signal output terminals are connected across the capacitor 62, across which the selected high level signal is derived.
In this embodiment the switching bridge is operated by the pulse width modulated signal at the 32 KHz PRF. A value for the inductor 61 in this case has been found to be 50 mh, to produce an output high level signal of suitable quality. However, if the switching bridge were operated by a signal having a lower PRF~ for example 8 KHz, the value sf the inductor 61 must be correspondingly increased to obtain an output high level signal of similar quality. Each of the switches 50A - 50D includes a voltage terminal connected as indicated to the negative -Vl or positive +Vl power terminals associated with the power supply 70. The inductor 73 in the impulse filter acts to isolate the power supply 70 from the switches, to prevent excess current from being conducted during short transitional moments in operation when all four of the switches are in a conductive state. This occurs during the transition from one state to the other in the signal stream. The 20 transitionai moment is minimized in this embodiment by the use of the MOSFET 34 in each of the driver circuits 30, 30a and 30b.
The output signal across the capacitor 62 is routed through a monitor circuit 80 which includes threshold circuits for indicating if an overvoltage or oYercurrent condition exists in the supply of the high level signal to the local ringing battery bus. Various threshold circuits well known to persnns skilled in electronics are suitable for these functions. The output of the ~.onitor circuit 80 is connected to an input of an OR gate 82. A one shot multivibrator circuit 81 with a s~t period of about 32 microseconds includes an input connected to the output of the flip-flop 26, to monitor the signal stream. The output of the one shot multivibrator circuit 81 is connected to another input of the OR gate 82.
The output of the OR gate 82 provides trouble indication in the event that the periodic pulses in the signal stream cease or if one of the threshold circuits in the monitor circuit 81 is activated.
The output of the OR gate when asserted causes a relay 130 to be actiYated via a relay driver circuit 83. This causes the associated relay contacts 131, shown ln figure 1, to disconnect the universal high level signal generator (UHLSG) from the local ringing battery bus and transfer the ringing battery bus feed to a UHLSG in an adjacent shelf.
The following table is a listing of start point addresses in hexadecimal format and identified with respect to the associated high level signal functions of the generator described above.
Function Table Start Point Address _ Generator Oùtput O O volts DC
8 20 Hz at 90 volts AC on -48 volts DC
198 -48 volts DC
lAO 3Q Hz at 120 volts AC on -48 volts DC
280 40 Hz at 130 volts AC on -48 volts DC
378 +48 volts DC
380 SO Hz at 140 volts AC on -48 volts DC, 420 -130 YOl ts DC
428 60 Hz at 140 volts AC on -48 volts DC
4BO +130 volts DC

The following table is a listing in hexadecimal format of the data byte content of the ROM 18 which defines the respective high level signal functions of the generator.

Address Data Bytes O~DO ~E000000000000004B4B4~4A49494~48 0010 4847474646~5454544444~43434~4241 0020 4l4l4o4n3F3F3F3F3F3E3E3E3D3D3D3c 0030 3C3B3B3B3~3A3A3939Q93~3838373737 0040 37363636353~353534~4343433333333 0050 323232323231'1313131313030303030 0060 3030302F2~2F2F2F2F2F2F2F2F2F2F2F
0070 2F2F2F2F2F2F2F2f2F2F2F2F2f2F2F2F

0090 3232323Z3333333334343~3435353535 50A0 363636363737373B383~39393S3A3~3A

OOCO 4040414141~24243434344444545454b OODO 464747484~4~49494A4A4B4~4~4C4C4D
OOf~O 4D4D4E4E4F4F50505~SlC1~25252~;3c3 COFO 53545~555555565656575~5B5a585959 0100 595A5A5A5B5B5B5B5C5~5C5~5D5D5DSE
0110 5~5ESE5F5F5~5f~060606C606161hl~1 OlZO 6162626262626262S2636363~36363~3 0130 63636363~3~3~363~3~363~3~363~363 C140 636363b3636336363636362~2626262 0150 b262b261~16116160~06C60605Ç5F5F
016~ 5FSF5E5E55D5D5D5D5C5C5C5B5B5B5B
017~ 5A5A~A~s5s5s58585857575756~b555s 0180 555454545353~252525151505Q504F4F
Dl90 4E4E4D4D4G4C4CCBC80000~0000~000 OlAO ~95~57575555453525251504F4E4D4D
018V 4C4B4A4948~74646454443424140403F
OIC~ 3F3E3D3D3C3B3~393938373~3~353434 OlDO 3332323130302F2E2E2D2D2C2~ZB2e2A
OlEO 2A2A29292828282727272~262~2626Z6 01~0 2625Z~Z5252525~525Z525262~2~2~26 0200 26272727272~282B2S2925ZA2A2B2B2C
0210 2C2D2D2E2E2F2F303131~2~33343535 ~220 36373838'S3A3~3B3C3D3E3F3F3F4041 0230 4243~44445464748494A4A4B4C4~44F
0~40 50505~$2~545~555~575~5S595ASB5C
0230 5C5D5E5F5f606161b262~3~464656566 ~2bO 166676~686Q~96~6A6A~BbB6B6C6t6C
0270 t~C6D6D6DhD6D6D6DbD6D6r:6D6D6~6C6D
0280 6D6D6DbD~I:;b~:C6C6C~B6B6B6A6.AS~69 029~ ~9b968b8b767666$65656463636261bl OZAt7 605F5f5E5D5D5C5B~;~QDbOOOOOOOOOOaO
02~S~ 636261605F5f~5D5C5~CA5558575~5453 02fO 5Z514~4EbD4C4B494a4746444342413F
1)2D0 3F3E3D3C3A39383~36~534333231302F
02EO Z~2D2~2CZIB2A29292827272~2~:25~''24 02~0 2424232323232222Z222~22222222323 2~

hddress Data Bytes 0300 232324242425252626272~2~Z92A2d2B
0310 2C2D2E2E2F30 113Z3334353~37393A3B
03~0 3~3D3E3F40414243454b4~4~4~4~4C4D
0330 4F5051525455565758Cg5A5C5D5EcF60 0340 ~1~26364~565~6b76869b9b~686e6C6D
0350 bD6E6E6E6F6F6F7~707070~070707070 03B0 70707070706F~F6F6~ D6~6C6C~B6B
037D 6A696B686~6665E4B40000000ooooooo 0380 6D6C686~6968676664~362~C5FSD5C5A
0390 ~957565452514F4D4C4A48474543~240 03A~ 3F3E3C3~39383b353332302F2E2L2B2A
03B3 29Z827262524242322Z221Z120202ClF
03C0 lFlflFlFlF202D20202121?223232425 03D0 262728292~ZB2{2D2Ç30~132343~3?38 03E0 3A3B3D3~3F~143444~484g4~4D4E5052 03F0 ~3~55bS85A585DSE5F~162~465666768 0480 6~6B6C6D6E~E6F~0~0717Z727Z737373 0410 73737373~37373~372727171706F6FEE
0420 ~9OQ0000000000007171~0~FbEkD6C6B
0430 6A~867666462615F5D5C5A5856545Z50 0440 4~4C4A48464442403F3D3~3938363432 0450 312F2D2C282928272b2524232221Z12D
0460 Z0201Fl~lFlFlF20Z0202122Z22~2425 0470 2B27282A2~2C2EZF3133343~383A3C3~
0480 3F41434547494e4~4F515'_557585ASC
0490 SE6061b3646667~96A~B6C6E6F~f7~71 04A0 72~2~3~373737373~37373~2F20~0000 04B0 A'

Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A pulse width modulating signal generator operable in combination with a source of clock signals, the signal generator comprising:
means for storing data bytes each representative of a period of time;
first means having an output and being responsive to clock signals from said source of clock signals, for repetitively generating at the output, a sequential series of data bytes;
second means for generating a period signal in response to each occurrence of a completed sequence of said sequential series of data bytes;
a comparator means for generating a time signal in response to a predetermined correspondence between a selected one of the stored data bytes and an instant one of the data bytes at the output of the first means;
third means for generating the pulse width modulated signal at its output in response to the period and time signals, the generated pulse width modulated signal having asserted signal portions defined by consecutive occurrences of the period and time signals.

2. A pulse width modulating signal generator as defined in claim 1 and responsive to instruction words each identifying one of a plurality of predetermined signal streams of width modulated pulses, wherein said storing means comprises:

a memory for storing said data bytes in discrete ranges of address accessible locations, each range corresponding to one of the predetermined signal streams;
a clock pulse generator for generating trains of clock pulse signals in response to the output of the first means and to said clock signals, addressing means for generating addresses traversing a range as identified by an instruction word and in response to said clock pulse signals, to cause the memory to read out said time period representative signals.

3. A pulse width modulating signal generator as defined in claim 1, wherein the clock pulse generator generates one clock pulse signal in response to a predetermined plurality of occurrences of said series of data bytes from the first means, whereby a corresponding series of identical time signals are generated by the comparator.

4. A pulse width modulating signal generator as defined in claim 1 wherein the comparator comprises:
a digital comparator having one data byte input port connected to an output of the first means for receiving the data bytes and having a second data byte input, the digital comparator being responsive to a match between the signals for generating the time signal; and an adder circuit connected between the output of the memory and the second input of the digital comparator, for adding an offset to the data bytes received from the memory, whereby the assertion portion of the pulses in the signal stream are altered.

5. A method for generatoring a pulse width modulated signal comprising the steps of:
a) registering a data byte representative of a period of time;
b) generating a sequential series of data bytes at a predetermined rate;
c) generating a period signal at a predetermined time during the occurrence of step (b);
d) generating a time signal in response to a predetermined correspondence between the registered data byte and an instant one of the data bytes in said series of data bytes; and e) generating a pulse signal having an assertion width defined by the occurrences of the period signal and the time signal.

6. A method for generating a pulse width modulated signal as defined in claim 5, wherein said predetermined time in step c) is substantially coincident with an initiation of step b).

7. A method for generating a pulse width modulated signal as defined in claim 5 wherein said predetermined time in step c) is substantially coincident with a termination of step b).

8. A method for generating a pulse width modulated signal as defined in claim 5 wherein said predetermined time is substantially coincident with an occurrence of a preselected data byte in the sequential series of data bytes being generated in step b).

9. A method for generating a pulse width modulated signal as defined in claim 5 wherein the steps b), c), d), and e) are repeated, whereby a series of identical pulse width modulated signals is generated.