PT77304A - Synchronization apparatus in transmiting information a simplex bus - Google Patents

Abstract

Advantages are: (1) better bus capacity utilisation; (2) no re-clocking unit is required on a bus intermediate section (B2); and (3) the hardware is the same for each module. The bus has a first section (B1) connected to the transmitter output (S) of each module; the bus intermediate section (B2) of variable length and connected from the last connected transmitter to the first connected receiver (R); and a third section (B3) to which the receivers (R) are connected in the same order as the transmitters. The total fixed time delay through the first, final bus section (B1,B3) respectively depends on the number of modules (A-N) connected. A clock signal unit in each module is common to its own transmitter and receiver. As well as internal clock signals, this unit sends the frame synchronisation module to the input of the bus through a bus transmitter. The frame synchronising pulse for synchronising remaining slave modules is ent in parallel with the data from the respective transmitter. A time slot memory stores data written to and from the bus under the control of a control memory.