PL1812856T3 - Sposób i urządzenie do oceny sygnału systemu komputerowego z co najmniej dwiema jednostkami wykonawczymi - Google Patents

Sposób i urządzenie do oceny sygnału systemu komputerowego z co najmniej dwiema jednostkami wykonawczymi

Info

Publication number
PL1812856T3
PL1812856T3 PL05801572T PL05801572T PL1812856T3 PL 1812856 T3 PL1812856 T3 PL 1812856T3 PL 05801572 T PL05801572 T PL 05801572T PL 05801572 T PL05801572 T PL 05801572T PL 1812856 T3 PL1812856 T3 PL 1812856T3
Authority
PL
Poland
Prior art keywords
signal
computer system
evaluating
mode
mode signal
Prior art date
Application number
PL05801572T
Other languages
English (en)
Inventor
Reinhard Weiberle
Bernd Mueller
Yorck Collani
Rainer Gmehlich
Eberhard Boehl
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE200410051952 external-priority patent/DE102004051952A1/de
Priority claimed from DE200410051992 external-priority patent/DE102004051992A1/de
Priority claimed from DE200410051937 external-priority patent/DE102004051937A1/de
Priority claimed from DE200410051964 external-priority patent/DE102004051964A1/de
Priority claimed from DE200410051950 external-priority patent/DE102004051950A1/de
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of PL1812856T3 publication Critical patent/PL1812856T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
PL05801572T 2004-10-25 2005-10-25 Sposób i urządzenie do oceny sygnału systemu komputerowego z co najmniej dwiema jednostkami wykonawczymi PL1812856T3 (pl)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
DE200410051952 DE102004051952A1 (de) 2004-10-25 2004-10-25 Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem
DE200410051992 DE102004051992A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Mehrprozessorsystems
DE200410051937 DE102004051937A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Synchronisierung in einem Mehrprozessorsystem
DE200410051964 DE102004051964A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Überwachung einer Speichereinheit in einem Mehrprozessorsystem
DE200410051950 DE102004051950A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Taktumschaltung bei einem Mehrprozessorsystem
DE102005037222A DE102005037222A1 (de) 2004-10-25 2005-08-08 Verfahren und Vorrichtung zur Auswertung eines Signals eines Rechnersystems mit wenigstens zwei Ausführungseinheiten
PCT/EP2005/055504 WO2006045778A1 (de) 2004-10-25 2005-10-25 Verfahren und vorrichtung zur auswertung eines signals eines rechnersystems mit wenigstens zwei ausführungseinheiten
EP05801572A EP1812856B1 (de) 2004-10-25 2005-10-25 Verfahren und vorrichtung zur auswertung eines signals eines rechnersystems mit wenigstens zwei ausführungseinheiten

Publications (1)

Publication Number Publication Date
PL1812856T3 true PL1812856T3 (pl) 2009-02-27

Family

ID=35985207

Family Applications (1)

Application Number Title Priority Date Filing Date
PL05801572T PL1812856T3 (pl) 2004-10-25 2005-10-25 Sposób i urządzenie do oceny sygnału systemu komputerowego z co najmniej dwiema jednostkami wykonawczymi

Country Status (9)

Country Link
US (1) US20080263340A1 (pl)
EP (1) EP1812856B1 (pl)
JP (1) JP2008518299A (pl)
KR (1) KR20070062577A (pl)
AT (1) ATE407399T1 (pl)
DE (2) DE102005037222A1 (pl)
ES (1) ES2311238T3 (pl)
PL (1) PL1812856T3 (pl)
WO (1) WO2006045778A1 (pl)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
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CN101048757A (zh) * 2004-10-25 2007-10-03 罗伯特·博世有限公司 在拥有至少两个执行单元的计算机系统中切换的方法和装置
DE102006050715A1 (de) * 2006-10-10 2008-04-17 Robert Bosch Gmbh Verfahren und System zum Erzeugen eines gültigen Signals
DE102006048169A1 (de) * 2006-10-10 2008-04-17 Robert Bosch Gmbh Verfahren zur Überwachung einer Funktionsfähigkeit einer Steuerung
JP5025402B2 (ja) * 2007-09-28 2012-09-12 株式会社日立製作所 高安全制御装置
JP2010117813A (ja) * 2008-11-12 2010-05-27 Nec Electronics Corp デバッグシステム、デバッグ方法、デバッグ制御方法及びデバッグ制御プログラム
US8275977B2 (en) * 2009-04-08 2012-09-25 Freescale Semiconductor, Inc. Debug signaling in a multiple processor data processing system
JP5796311B2 (ja) 2011-03-15 2015-10-21 オムロン株式会社 制御装置およびシステムプログラム
KR102013582B1 (ko) 2012-09-07 2019-08-23 삼성전자 주식회사 혼합 모드 프로그램의 소스 코드 오류 위치 검출 장치 및 방법
DE102015216086A1 (de) * 2015-08-24 2017-03-02 Robert Bosch Gmbh Verfahren und Vorrichtung zum Überwachen eines Zustandes einer elektronischen Schaltungseinheit eines Fahrzeugs
US9547483B1 (en) * 2015-11-06 2017-01-17 International Business Machines Corporation Feedback directed optimized compiling of optimized executable code

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JPS5026345B1 (pl) * 1970-09-30 1975-08-30
JPS5028309B1 (pl) * 1970-11-20 1975-09-13
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
US3783250A (en) * 1972-02-25 1974-01-01 Nasa Adaptive voting computer system
JPS58221453A (ja) * 1982-06-17 1983-12-23 Toshiba Corp 多重系情報処理装置
AU568977B2 (en) * 1985-05-10 1988-01-14 Tandem Computers Inc. Dual processor error detection system
US4811345A (en) * 1986-12-16 1989-03-07 Advanced Micro Devices, Inc. Methods and apparatus for providing a user oriented microprocessor test interface for a complex, single chip, general purpose central processing unit
CA1320276C (en) * 1987-09-04 1993-07-13 William F. Bruckert Dual rail processors with error checking on i/o reads
GB8729901D0 (en) * 1987-12-22 1988-02-03 Lucas Ind Plc Dual computer cross-checking system
JPH08161187A (ja) * 1994-12-09 1996-06-21 Mitsubishi Electric Corp 計算機制御方式
DE19511842A1 (de) * 1995-03-31 1996-10-02 Teves Gmbh Alfred Verfahren und Schaltungsanordnung zur Überwachung einer Datenverarbeitungsschaltung
US5796935A (en) * 1995-07-20 1998-08-18 Raytheon Company Voting node for a distributed control system
JPH1063544A (ja) * 1996-08-20 1998-03-06 Toshiba Corp タイムアウト監視方式
DE19827430C2 (de) * 1997-07-22 2001-07-12 Siemens Ag Überwachungsverfahren zur Erkennung von Endlosschleifen und blockierten Prozessen in einem Rechnersystem
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US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
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US7003691B2 (en) * 2002-06-28 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for seeding differences in lock-stepped processors
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Also Published As

Publication number Publication date
EP1812856B1 (de) 2008-09-03
DE102005037222A1 (de) 2007-02-15
JP2008518299A (ja) 2008-05-29
ATE407399T1 (de) 2008-09-15
ES2311238T3 (es) 2009-02-01
WO2006045778A1 (de) 2006-05-04
EP1812856A1 (de) 2007-08-01
DE502005005285D1 (de) 2008-10-16
KR20070062577A (ko) 2007-06-15
US20080263340A1 (en) 2008-10-23

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