PH31230A - Analog macro embedded in a digital gate array. - Google Patents

Analog macro embedded in a digital gate array.

Info

Publication number
PH31230A
PH31230A PH38364A PH38364A PH31230A PH 31230 A PH31230 A PH 31230A PH 38364 A PH38364 A PH 38364A PH 38364 A PH38364 A PH 38364A PH 31230 A PH31230 A PH 31230A
Authority
PH
Philippines
Prior art keywords
gate array
digital gate
analog macro
macro embedded
embedded
Prior art date
Application number
PH38364A
Other languages
English (en)
Inventor
Edward F Culican Sr
John D Davis
John F Ewen
Scott A Mccabe
Joseph M Mosley
Allan L Mullgray Jr
Philip F Noto
Clarence I Peterson Jr
Philip E Pritzlaff Jr
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of PH31230A publication Critical patent/PH31230A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
PH38364A 1988-03-25 1989-03-21 Analog macro embedded in a digital gate array. PH31230A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/173,517 US4833425A (en) 1988-03-25 1988-03-25 Analog macro embedded in a digital gate array

Publications (1)

Publication Number Publication Date
PH31230A true PH31230A (en) 1998-06-16

Family

ID=22632383

Family Applications (1)

Application Number Title Priority Date Filing Date
PH38364A PH31230A (en) 1988-03-25 1989-03-21 Analog macro embedded in a digital gate array.

Country Status (12)

Country Link
US (1) US4833425A (de)
EP (1) EP0334784B1 (de)
JP (1) JPH0770693B2 (de)
KR (1) KR920003451B1 (de)
CN (1) CN1031305C (de)
CA (1) CA1312929C (de)
DE (1) DE68919376T2 (de)
ES (1) ES2064477T3 (de)
GB (1) GB8906479D0 (de)
HK (1) HK90495A (de)
MY (1) MY103856A (de)
PH (1) PH31230A (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943787A (en) 1989-09-05 1990-07-24 Motorola, Inc. Digital time base generator with adjustable delay between two outputs
US5241286A (en) * 1991-08-28 1993-08-31 Fred Mirow FET oscillator using voltage and temperature compensated amplifier
US5191301A (en) * 1992-05-12 1993-03-02 International Business Machines Corporation Integrated differential voltage controlled ring oscillator
US5337024A (en) * 1993-06-22 1994-08-09 Rockwell International Corporation Phase locked loop frequency modulator using fractional division
US5559842A (en) * 1994-03-30 1996-09-24 Lucent Technologies Inc. Network-controlled reference frequency generator
CN1050007C (zh) * 1995-04-05 2000-03-01 盛群半导体股份有限公司 集成电路的布局方法
CN1075667C (zh) * 1996-04-19 2001-11-28 松下电器产业株式会社 半导体集成电路及采用该电路的系统
JP2000124802A (ja) * 1998-10-20 2000-04-28 Mitsubishi Electric Corp Ｐｌｌ回路
US6779125B1 (en) * 2000-06-09 2004-08-17 Cirrus Logic, Inc. Clock generator circuitry
US6441667B1 (en) * 2001-03-29 2002-08-27 International Business Machines Corporation Multiphase clock generator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135244A (de) * 1974-09-20 1976-03-25 Hitachi Ltd
US4069462A (en) * 1976-12-13 1978-01-17 Data General Corporation Phase-locked loops
US4227158A (en) * 1979-02-01 1980-10-07 The Singer Company Multifrequency control from a single crystal
US4388597A (en) * 1980-06-03 1983-06-14 Motorola Inc. Frequency synthesizer having plural phase locked loops
US4394769A (en) * 1981-06-15 1983-07-19 Hughes Aircraft Company Dual modulus counter having non-inverting feedback
GB8329511D0 (en) * 1983-11-04 1983-12-07 Inmos Ltd Timing apparatus
US4594563A (en) * 1984-11-02 1986-06-10 Ampex Corporation Signal comparison circuit and phase-locked-loop using same
JPS61263241A (ja) * 1985-05-17 1986-11-21 Matsushita Electronics Corp ゲ−トアレイ

Also Published As

Publication number Publication date
JPH0770693B2 (ja) 1995-07-31
JPH0210768A (ja) 1990-01-16
EP0334784A3 (en) 1990-11-28
KR890015419A (ko) 1989-10-30
DE68919376T2 (de) 1995-05-24
CA1312929C (en) 1993-01-19
DE68919376D1 (de) 1994-12-22
EP0334784B1 (de) 1994-11-17
CN1039329A (zh) 1990-01-31
KR920003451B1 (ko) 1992-05-01
MY103856A (en) 1993-09-30
ES2064477T3 (es) 1995-02-01
EP0334784A2 (de) 1989-09-27
GB8906479D0 (en) 1989-05-04
CN1031305C (zh) 1996-03-13
HK90495A (en) 1995-06-16
US4833425A (en) 1989-05-23

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